diff options
Diffstat (limited to 'arch/arm/mach-omap2/clock3xxx_data.c')
-rw-r--r-- | arch/arm/mach-omap2/clock3xxx_data.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 480fb8f09aed..f4a626f7c79e 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c | |||
@@ -747,7 +747,7 @@ static struct clk dpll4_m3_ck = { | |||
747 | .parent = &dpll4_ck, | 747 | .parent = &dpll4_ck, |
748 | .init = &omap2_init_clksel_parent, | 748 | .init = &omap2_init_clksel_parent, |
749 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | 749 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), |
750 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, | 750 | .clksel_mask = OMAP3630_CLKSEL_TV_MASK, |
751 | .clksel = dpll4_clksel, | 751 | .clksel = dpll4_clksel, |
752 | .clkdm_name = "dpll4_clkdm", | 752 | .clkdm_name = "dpll4_clkdm", |
753 | .recalc = &omap2_clksel_recalc, | 753 | .recalc = &omap2_clksel_recalc, |
@@ -832,7 +832,7 @@ static struct clk dpll4_m4_ck = { | |||
832 | .parent = &dpll4_ck, | 832 | .parent = &dpll4_ck, |
833 | .init = &omap2_init_clksel_parent, | 833 | .init = &omap2_init_clksel_parent, |
834 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | 834 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), |
835 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, | 835 | .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK, |
836 | .clksel = dpll4_clksel, | 836 | .clksel = dpll4_clksel, |
837 | .clkdm_name = "dpll4_clkdm", | 837 | .clkdm_name = "dpll4_clkdm", |
838 | .recalc = &omap2_clksel_recalc, | 838 | .recalc = &omap2_clksel_recalc, |
@@ -859,7 +859,7 @@ static struct clk dpll4_m5_ck = { | |||
859 | .parent = &dpll4_ck, | 859 | .parent = &dpll4_ck, |
860 | .init = &omap2_init_clksel_parent, | 860 | .init = &omap2_init_clksel_parent, |
861 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), | 861 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), |
862 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, | 862 | .clksel_mask = OMAP3630_CLKSEL_CAM_MASK, |
863 | .clksel = dpll4_clksel, | 863 | .clksel = dpll4_clksel, |
864 | .clkdm_name = "dpll4_clkdm", | 864 | .clkdm_name = "dpll4_clkdm", |
865 | .set_rate = &omap2_clksel_set_rate, | 865 | .set_rate = &omap2_clksel_set_rate, |
@@ -886,7 +886,7 @@ static struct clk dpll4_m6_ck = { | |||
886 | .parent = &dpll4_ck, | 886 | .parent = &dpll4_ck, |
887 | .init = &omap2_init_clksel_parent, | 887 | .init = &omap2_init_clksel_parent, |
888 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 888 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
889 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, | 889 | .clksel_mask = OMAP3630_DIV_DPLL4_MASK, |
890 | .clksel = dpll4_clksel, | 890 | .clksel = dpll4_clksel, |
891 | .clkdm_name = "dpll4_clkdm", | 891 | .clkdm_name = "dpll4_clkdm", |
892 | .recalc = &omap2_clksel_recalc, | 892 | .recalc = &omap2_clksel_recalc, |
@@ -1394,6 +1394,7 @@ static struct clk cpefuse_fck = { | |||
1394 | .name = "cpefuse_fck", | 1394 | .name = "cpefuse_fck", |
1395 | .ops = &clkops_omap2_dflt, | 1395 | .ops = &clkops_omap2_dflt, |
1396 | .parent = &sys_ck, | 1396 | .parent = &sys_ck, |
1397 | .clkdm_name = "core_l4_clkdm", | ||
1397 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | 1398 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
1398 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, | 1399 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, |
1399 | .recalc = &followparent_recalc, | 1400 | .recalc = &followparent_recalc, |
@@ -1403,6 +1404,7 @@ static struct clk ts_fck = { | |||
1403 | .name = "ts_fck", | 1404 | .name = "ts_fck", |
1404 | .ops = &clkops_omap2_dflt, | 1405 | .ops = &clkops_omap2_dflt, |
1405 | .parent = &omap_32k_fck, | 1406 | .parent = &omap_32k_fck, |
1407 | .clkdm_name = "core_l4_clkdm", | ||
1406 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | 1408 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
1407 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, | 1409 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, |
1408 | .recalc = &followparent_recalc, | 1410 | .recalc = &followparent_recalc, |
@@ -1412,6 +1414,7 @@ static struct clk usbtll_fck = { | |||
1412 | .name = "usbtll_fck", | 1414 | .name = "usbtll_fck", |
1413 | .ops = &clkops_omap2_dflt_wait, | 1415 | .ops = &clkops_omap2_dflt_wait, |
1414 | .parent = &dpll5_m2_ck, | 1416 | .parent = &dpll5_m2_ck, |
1417 | .clkdm_name = "core_l4_clkdm", | ||
1415 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | 1418 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
1416 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | 1419 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
1417 | .recalc = &followparent_recalc, | 1420 | .recalc = &followparent_recalc, |
@@ -1617,6 +1620,7 @@ static struct clk fshostusb_fck = { | |||
1617 | .name = "fshostusb_fck", | 1620 | .name = "fshostusb_fck", |
1618 | .ops = &clkops_omap2_dflt_wait, | 1621 | .ops = &clkops_omap2_dflt_wait, |
1619 | .parent = &core_48m_fck, | 1622 | .parent = &core_48m_fck, |
1623 | .clkdm_name = "core_l4_clkdm", | ||
1620 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1624 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1621 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | 1625 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, |
1622 | .recalc = &followparent_recalc, | 1626 | .recalc = &followparent_recalc, |
@@ -2043,6 +2047,7 @@ static struct clk omapctrl_ick = { | |||
2043 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2047 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2044 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, | 2048 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, |
2045 | .flags = ENABLE_ON_INIT, | 2049 | .flags = ENABLE_ON_INIT, |
2050 | .clkdm_name = "core_l4_clkdm", | ||
2046 | .recalc = &followparent_recalc, | 2051 | .recalc = &followparent_recalc, |
2047 | }; | 2052 | }; |
2048 | 2053 | ||
@@ -2094,6 +2099,7 @@ static struct clk usb_l4_ick = { | |||
2094 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | 2099 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
2095 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, | 2100 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, |
2096 | .clksel = usb_l4_clksel, | 2101 | .clksel = usb_l4_clksel, |
2102 | .clkdm_name = "core_l4_clkdm", | ||
2097 | .recalc = &omap2_clksel_recalc, | 2103 | .recalc = &omap2_clksel_recalc, |
2098 | }; | 2104 | }; |
2099 | 2105 | ||
@@ -3467,8 +3473,8 @@ static struct omap_clk omap3xxx_clks[] = { | |||
3467 | CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), | 3473 | CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), |
3468 | CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), | 3474 | CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), |
3469 | CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), | 3475 | CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), |
3470 | CLK("davinci_emac", "emac_clk", &emac_ick, CK_AM35XX), | 3476 | CLK("davinci_emac", NULL, &emac_ick, CK_AM35XX), |
3471 | CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX), | 3477 | CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), |
3472 | CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), | 3478 | CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), |
3473 | CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), | 3479 | CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), |
3474 | CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), | 3480 | CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), |