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Diffstat (limited to 'arch/arm/mach-omap2/clock3xxx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c34
1 files changed, 33 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index c73906d17458..d85ecd5aebfd 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -20,7 +20,6 @@
20#include <linux/clk.h> 20#include <linux/clk.h>
21#include <linux/list.h> 21#include <linux/list.h>
22 22
23#include <plat/control.h>
24#include <plat/clkdev_omap.h> 23#include <plat/clkdev_omap.h>
25 24
26#include "clock.h" 25#include "clock.h"
@@ -33,6 +32,7 @@
33#include "cm-regbits-34xx.h" 32#include "cm-regbits-34xx.h"
34#include "prm.h" 33#include "prm.h"
35#include "prm-regbits-34xx.h" 34#include "prm-regbits-34xx.h"
35#include "control.h"
36 36
37/* 37/*
38 * clocks 38 * clocks
@@ -2465,6 +2465,16 @@ static struct clk uart3_fck = {
2465 .recalc = &followparent_recalc, 2465 .recalc = &followparent_recalc,
2466}; 2466};
2467 2467
2468static struct clk uart4_fck = {
2469 .name = "uart4_fck",
2470 .ops = &clkops_omap2_dflt_wait,
2471 .parent = &per_48m_fck,
2472 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2473 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2474 .clkdm_name = "per_clkdm",
2475 .recalc = &followparent_recalc,
2476};
2477
2468static struct clk gpt2_fck = { 2478static struct clk gpt2_fck = {
2469 .name = "gpt2_fck", 2479 .name = "gpt2_fck",
2470 .ops = &clkops_omap2_dflt_wait, 2480 .ops = &clkops_omap2_dflt_wait,
@@ -2715,6 +2725,16 @@ static struct clk uart3_ick = {
2715 .recalc = &followparent_recalc, 2725 .recalc = &followparent_recalc,
2716}; 2726};
2717 2727
2728static struct clk uart4_ick = {
2729 .name = "uart4_ick",
2730 .ops = &clkops_omap2_dflt_wait,
2731 .parent = &per_l4_ick,
2732 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2733 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2734 .clkdm_name = "per_clkdm",
2735 .recalc = &followparent_recalc,
2736};
2737
2718static struct clk gpt9_ick = { 2738static struct clk gpt9_ick = {
2719 .name = "gpt9_ick", 2739 .name = "gpt9_ick",
2720 .ops = &clkops_omap2_dflt_wait, 2740 .ops = &clkops_omap2_dflt_wait,
@@ -3188,6 +3208,11 @@ static struct omap_clk omap3xxx_clks[] = {
3188 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), 3208 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3189 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), 3209 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3190 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), 3210 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3211 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX),
3212 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX),
3213 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX),
3214 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX),
3215 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX),
3191 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), 3216 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3192 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), 3217 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3193 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), 3218 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
@@ -3253,6 +3278,8 @@ static struct omap_clk omap3xxx_clks[] = {
3253 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX), 3278 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX),
3254 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX), 3279 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX),
3255 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), 3280 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX),
3281 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3282 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3256 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), 3283 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3257 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX), 3284 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX),
3258 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), 3285 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
@@ -3346,9 +3373,13 @@ static struct omap_clk omap3xxx_clks[] = {
3346 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), 3373 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3347 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), 3374 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3348 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), 3375 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3376 CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX),
3377 CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX),
3378 CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX),
3349 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), 3379 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3350 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), 3380 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3351 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), 3381 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3382 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
3352 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), 3383 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3353 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), 3384 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3354 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), 3385 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
@@ -3372,6 +3403,7 @@ static struct omap_clk omap3xxx_clks[] = {
3372 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX), 3403 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3373 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX), 3404 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3374 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX), 3405 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3406 CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX),
3375 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX), 3407 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3376 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX), 3408 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3377 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX), 3409 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),