aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/clock3xxx_data.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-omap2/clock3xxx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c218
1 files changed, 112 insertions, 106 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index ee8aa39269f3..9ab817e6c300 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -28,9 +28,9 @@
28#include "clock36xx.h" 28#include "clock36xx.h"
29#include "clock3517.h" 29#include "clock3517.h"
30 30
31#include "cm.h" 31#include "cm2xxx_3xxx.h"
32#include "cm-regbits-34xx.h" 32#include "cm-regbits-34xx.h"
33#include "prm.h" 33#include "prm2xxx_3xxx.h"
34#include "prm-regbits-34xx.h" 34#include "prm-regbits-34xx.h"
35#include "control.h" 35#include "control.h"
36 36
@@ -120,7 +120,7 @@ static const struct clksel_rate osc_sys_13m_rates[] = {
120}; 120};
121 121
122static const struct clksel_rate osc_sys_16_8m_rates[] = { 122static const struct clksel_rate osc_sys_16_8m_rates[] = {
123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS }, 123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
124 { .div = 0 } 124 { .div = 0 }
125}; 125};
126 126
@@ -452,35 +452,35 @@ static struct clk dpll3_x2_ck = {
452static const struct clksel_rate div31_dpll3_rates[] = { 452static const struct clksel_rate div31_dpll3_rates[] = {
453 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 453 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
454 { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, 454 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS }, 455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS }, 456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
457 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS }, 457 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
458 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS }, 458 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
459 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS }, 459 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
460 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS }, 460 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
461 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS }, 461 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
462 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS }, 462 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
463 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS }, 463 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
464 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS }, 464 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
465 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS }, 465 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
466 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS }, 466 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
467 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS }, 467 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
468 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS }, 468 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
469 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS }, 469 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
470 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS }, 470 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
471 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS }, 471 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
472 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS }, 472 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
473 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS }, 473 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
474 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS }, 474 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
475 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS }, 475 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
476 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS }, 476 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
477 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS }, 477 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
478 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS }, 478 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
479 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS }, 479 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
480 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS }, 480 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
481 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS }, 481 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
482 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS }, 482 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
483 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS }, 483 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
484 { .div = 0 }, 484 { .div = 0 },
485}; 485};
486 486
@@ -602,6 +602,8 @@ static struct dpll_data dpll4_dd_3630 __initdata = {
602 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, 602 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
603 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 603 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
604 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, 604 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
605 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
606 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
605 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, 607 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
606 .min_divider = 1, 608 .min_divider = 1,
607 .max_divider = OMAP3_MAX_DPLL_DIV, 609 .max_divider = OMAP3_MAX_DPLL_DIV,
@@ -1558,6 +1560,7 @@ static struct clk mcspi4_fck = {
1558 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1560 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1561 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1560 .recalc = &followparent_recalc, 1562 .recalc = &followparent_recalc,
1563 .clkdm_name = "core_l4_clkdm",
1561}; 1564};
1562 1565
1563static struct clk mcspi3_fck = { 1566static struct clk mcspi3_fck = {
@@ -1567,6 +1570,7 @@ static struct clk mcspi3_fck = {
1567 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1570 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1568 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1571 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1569 .recalc = &followparent_recalc, 1572 .recalc = &followparent_recalc,
1573 .clkdm_name = "core_l4_clkdm",
1570}; 1574};
1571 1575
1572static struct clk mcspi2_fck = { 1576static struct clk mcspi2_fck = {
@@ -1576,6 +1580,7 @@ static struct clk mcspi2_fck = {
1576 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1580 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1577 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1581 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1578 .recalc = &followparent_recalc, 1582 .recalc = &followparent_recalc,
1583 .clkdm_name = "core_l4_clkdm",
1579}; 1584};
1580 1585
1581static struct clk mcspi1_fck = { 1586static struct clk mcspi1_fck = {
@@ -1585,6 +1590,7 @@ static struct clk mcspi1_fck = {
1585 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1590 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1586 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1591 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1587 .recalc = &followparent_recalc, 1592 .recalc = &followparent_recalc,
1593 .clkdm_name = "core_l4_clkdm",
1588}; 1594};
1589 1595
1590static struct clk uart2_fck = { 1596static struct clk uart2_fck = {
@@ -3044,6 +3050,7 @@ static struct clk sr1_fck = {
3044 .parent = &sys_ck, 3050 .parent = &sys_ck,
3045 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 3051 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3046 .enable_bit = OMAP3430_EN_SR1_SHIFT, 3052 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3053 .clkdm_name = "wkup_clkdm",
3047 .recalc = &followparent_recalc, 3054 .recalc = &followparent_recalc,
3048}; 3055};
3049 3056
@@ -3054,6 +3061,7 @@ static struct clk sr2_fck = {
3054 .parent = &sys_ck, 3061 .parent = &sys_ck,
3055 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 3062 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3056 .enable_bit = OMAP3430_EN_SR2_SHIFT, 3063 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3064 .clkdm_name = "wkup_clkdm",
3057 .recalc = &followparent_recalc, 3065 .recalc = &followparent_recalc,
3058}; 3066};
3059 3067
@@ -3201,7 +3209,7 @@ static struct omap_clk omap3xxx_clks[] = {
3201 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), 3209 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3202 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), 3210 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3203 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), 3211 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3204 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX), 3212 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3205 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX), 3213 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3206 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX), 3214 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
3207 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), 3215 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
@@ -3218,8 +3226,8 @@ static struct omap_clk omap3xxx_clks[] = {
3218 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), 3226 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3219 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), 3227 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3220 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), 3228 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3221 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), 3229 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX),
3222 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), 3230 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX),
3223 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), 3231 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3224 CLK(NULL, "core_ck", &core_ck, CK_3XXX), 3232 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3225 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), 3233 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
@@ -3248,8 +3256,8 @@ static struct omap_clk omap3xxx_clks[] = {
3248 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), 3256 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3249 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), 3257 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3250 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), 3258 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3251 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX), 3259 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3252 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX), 3260 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3253 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), 3261 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3254 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), 3262 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3255 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), 3263 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
@@ -3257,8 +3265,8 @@ static struct omap_clk omap3xxx_clks[] = {
3257 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), 3265 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3258 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), 3266 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3259 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), 3267 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3260 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), 3268 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
3261 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), 3269 CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
3262 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), 3270 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3263 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), 3271 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3264 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), 3272 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
@@ -3267,23 +3275,23 @@ static struct omap_clk omap3xxx_clks[] = {
3267 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), 3275 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3268 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), 3276 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3269 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), 3277 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
3270 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517), 3278 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX),
3271 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517), 3279 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX),
3272 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), 3280 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3273 CLK(NULL, "modem_fck", &modem_fck, CK_343X), 3281 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
3274 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), 3282 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
3275 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), 3283 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX),
3276 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), 3284 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3277 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), 3285 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3278 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX), 3286 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3279 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX), 3287 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3280 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), 3288 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3281 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), 3289 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3282 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), 3290 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3283 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), 3291 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3284 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX), 3292 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3285 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), 3293 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
3286 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), 3294 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
3287 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX), 3295 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX),
3288 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX), 3296 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX),
3289 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX), 3297 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX),
@@ -3301,26 +3309,26 @@ static struct omap_clk omap3xxx_clks[] = {
3301 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), 3309 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3302 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), 3310 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
3303 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), 3311 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3304 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), 3312 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3305 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), 3313 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3306 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), 3314 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3307 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), 3315 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
3308 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), 3316 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3309 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), 3317 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3310 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), 3318 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3311 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), 3319 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
3312 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), 3320 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3313 CLK(NULL, "pka_ick", &pka_ick, CK_343X), 3321 CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX),
3314 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), 3322 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3315 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX), 3323 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3316 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), 3324 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3317 CLK(NULL, "icr_ick", &icr_ick, CK_343X), 3325 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
3318 CLK("omap-aes", "ick", &aes2_ick, CK_343X), 3326 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3319 CLK("omap-sham", "ick", &sha12_ick, CK_343X), 3327 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3320 CLK(NULL, "des2_ick", &des2_ick, CK_343X), 3328 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
3321 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), 3329 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX),
3322 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), 3330 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX),
3323 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), 3331 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
3324 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), 3332 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3325 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), 3333 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3326 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), 3334 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
@@ -3336,37 +3344,37 @@ static struct omap_clk omap3xxx_clks[] = {
3336 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), 3344 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3337 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), 3345 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
3338 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), 3346 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3339 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), 3347 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3340 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), 3348 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
3341 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), 3349 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX),
3342 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), 3350 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3343 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), 3351 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3344 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), 3352 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3345 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), 3353 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3346 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), 3354 CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX),
3347 CLK("omap_rng", "ick", &rng_ick, CK_343X), 3355 CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
3348 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), 3356 CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
3349 CLK(NULL, "des1_ick", &des1_ick, CK_343X), 3357 CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
3350 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), 3358 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
3351 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX), 3359 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3352 CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX), 3360 CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX),
3353 CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX), 3361 CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX),
3354 CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX), 3362 CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX),
3355 CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), 3363 CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1),
3356 CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX), 3364 CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3357 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), 3365 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
3358 CLK(NULL, "cam_ick", &cam_ick, CK_343X), 3366 CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
3359 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), 3367 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
3360 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX), 3368 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3361 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX), 3369 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3362 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX), 3370 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3363 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), 3371 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
3364 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), 3372 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3365 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), 3373 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3366 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), 3374 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3367 CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX), 3375 CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
3368 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), 3376 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
3369 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), 3377 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
3370 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), 3378 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3371 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), 3379 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3372 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), 3380 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
@@ -3424,9 +3432,9 @@ static struct omap_clk omap3xxx_clks[] = {
3424 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), 3432 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3425 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), 3433 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3426 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), 3434 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
3427 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), 3435 CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
3428 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), 3436 CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
3429 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), 3437 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
3430 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), 3438 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3431 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), 3439 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3432 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), 3440 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
@@ -3447,38 +3455,37 @@ static struct omap_clk omap3xxx_clks[] = {
3447int __init omap3xxx_clk_init(void) 3455int __init omap3xxx_clk_init(void)
3448{ 3456{
3449 struct omap_clk *c; 3457 struct omap_clk *c;
3450 u32 cpu_clkflg = CK_3XXX; 3458 u32 cpu_clkflg = 0;
3451 3459
3452 if (cpu_is_omap3517()) { 3460 if (cpu_is_omap3517()) {
3453 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; 3461 cpu_mask = RATE_IN_34XX;
3454 cpu_clkflg |= CK_3517; 3462 cpu_clkflg = CK_3517;
3455 } else if (cpu_is_omap3505()) { 3463 } else if (cpu_is_omap3505()) {
3456 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; 3464 cpu_mask = RATE_IN_34XX;
3457 cpu_clkflg |= CK_3505; 3465 cpu_clkflg = CK_3505;
3466 } else if (cpu_is_omap3630()) {
3467 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3468 cpu_clkflg = CK_36XX;
3458 } else if (cpu_is_omap34xx()) { 3469 } else if (cpu_is_omap34xx()) {
3459 cpu_mask = RATE_IN_3XXX;
3460 cpu_clkflg |= CK_343X;
3461
3462 /*
3463 * Update this if there are further clock changes between ES2
3464 * and production parts
3465 */
3466 if (omap_rev() == OMAP3430_REV_ES1_0) { 3470 if (omap_rev() == OMAP3430_REV_ES1_0) {
3467 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ 3471 cpu_mask = RATE_IN_3430ES1;
3468 cpu_clkflg |= CK_3430ES1; 3472 cpu_clkflg = CK_3430ES1;
3469 } else { 3473 } else {
3470 cpu_mask |= RATE_IN_3430ES2PLUS; 3474 /*
3471 cpu_clkflg |= CK_3430ES2; 3475 * Assume that anything that we haven't matched yet
3476 * has 3430ES2-type clocks.
3477 */
3478 cpu_mask = RATE_IN_3430ES2PLUS;
3479 cpu_clkflg = CK_3430ES2PLUS;
3472 } 3480 }
3481 } else {
3482 WARN(1, "clock: could not identify OMAP3 variant\n");
3473 } 3483 }
3474 3484
3475 if (omap3_has_192mhz_clk()) 3485 if (omap3_has_192mhz_clk())
3476 omap_96m_alwon_fck = omap_96m_alwon_fck_3630; 3486 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3477 3487
3478 if (cpu_is_omap3630()) { 3488 if (cpu_is_omap3630()) {
3479 cpu_mask |= RATE_IN_36XX;
3480 cpu_clkflg |= CK_36XX;
3481
3482 /* 3489 /*
3483 * XXX This type of dynamic rewriting of the clock tree is 3490 * XXX This type of dynamic rewriting of the clock tree is
3484 * deprecated and should be revised soon. 3491 * deprecated and should be revised soon.
@@ -3525,10 +3532,9 @@ int __init omap3xxx_clk_init(void)
3525 3532
3526 recalculate_root_clocks(); 3533 recalculate_root_clocks();
3527 3534
3528 printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " 3535 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3529 "%ld.%01ld/%ld/%ld MHz\n", 3536 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3530 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, 3537 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3531 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3532 3538
3533 /* 3539 /*
3534 * Only enable those clocks we will need, let the drivers 3540 * Only enable those clocks we will need, let the drivers
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 00:49:03 -0500