diff options
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.h')
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.h | 21 |
1 files changed, 1 insertions, 20 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 57cc2725b923..c8119781e00a 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h | |||
@@ -1020,6 +1020,7 @@ static struct clk arm_fck = { | |||
1020 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | 1020 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
1021 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | 1021 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, |
1022 | .clksel = arm_fck_clksel, | 1022 | .clksel = arm_fck_clksel, |
1023 | .clkdm_name = "mpu_clkdm", | ||
1023 | .recalc = &omap2_clksel_recalc, | 1024 | .recalc = &omap2_clksel_recalc, |
1024 | }; | 1025 | }; |
1025 | 1026 | ||
@@ -1155,7 +1156,6 @@ static struct clk gfx_cg1_ck = { | |||
1155 | .name = "gfx_cg1_ck", | 1156 | .name = "gfx_cg1_ck", |
1156 | .ops = &clkops_omap2_dflt_wait, | 1157 | .ops = &clkops_omap2_dflt_wait, |
1157 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | 1158 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
1158 | .init = &omap2_init_clk_clkdm, | ||
1159 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1159 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
1160 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, | 1160 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, |
1161 | .clkdm_name = "gfx_3430es1_clkdm", | 1161 | .clkdm_name = "gfx_3430es1_clkdm", |
@@ -1166,7 +1166,6 @@ static struct clk gfx_cg2_ck = { | |||
1166 | .name = "gfx_cg2_ck", | 1166 | .name = "gfx_cg2_ck", |
1167 | .ops = &clkops_omap2_dflt_wait, | 1167 | .ops = &clkops_omap2_dflt_wait, |
1168 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | 1168 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
1169 | .init = &omap2_init_clk_clkdm, | ||
1170 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1169 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
1171 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, | 1170 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, |
1172 | .clkdm_name = "gfx_3430es1_clkdm", | 1171 | .clkdm_name = "gfx_3430es1_clkdm", |
@@ -1210,7 +1209,6 @@ static struct clk sgx_ick = { | |||
1210 | .name = "sgx_ick", | 1209 | .name = "sgx_ick", |
1211 | .ops = &clkops_omap2_dflt_wait, | 1210 | .ops = &clkops_omap2_dflt_wait, |
1212 | .parent = &l3_ick, | 1211 | .parent = &l3_ick, |
1213 | .init = &omap2_init_clk_clkdm, | ||
1214 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), | 1212 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), |
1215 | .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, | 1213 | .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, |
1216 | .clkdm_name = "sgx_clkdm", | 1214 | .clkdm_name = "sgx_clkdm", |
@@ -1223,7 +1221,6 @@ static struct clk d2d_26m_fck = { | |||
1223 | .name = "d2d_26m_fck", | 1221 | .name = "d2d_26m_fck", |
1224 | .ops = &clkops_omap2_dflt_wait, | 1222 | .ops = &clkops_omap2_dflt_wait, |
1225 | .parent = &sys_ck, | 1223 | .parent = &sys_ck, |
1226 | .init = &omap2_init_clk_clkdm, | ||
1227 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1224 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1228 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, | 1225 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, |
1229 | .clkdm_name = "d2d_clkdm", | 1226 | .clkdm_name = "d2d_clkdm", |
@@ -1234,7 +1231,6 @@ static struct clk modem_fck = { | |||
1234 | .name = "modem_fck", | 1231 | .name = "modem_fck", |
1235 | .ops = &clkops_omap2_dflt_wait, | 1232 | .ops = &clkops_omap2_dflt_wait, |
1236 | .parent = &sys_ck, | 1233 | .parent = &sys_ck, |
1237 | .init = &omap2_init_clk_clkdm, | ||
1238 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1234 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1239 | .enable_bit = OMAP3430_EN_MODEM_SHIFT, | 1235 | .enable_bit = OMAP3430_EN_MODEM_SHIFT, |
1240 | .clkdm_name = "d2d_clkdm", | 1236 | .clkdm_name = "d2d_clkdm", |
@@ -1622,7 +1618,6 @@ static struct clk core_l3_ick = { | |||
1622 | .name = "core_l3_ick", | 1618 | .name = "core_l3_ick", |
1623 | .ops = &clkops_null, | 1619 | .ops = &clkops_null, |
1624 | .parent = &l3_ick, | 1620 | .parent = &l3_ick, |
1625 | .init = &omap2_init_clk_clkdm, | ||
1626 | .clkdm_name = "core_l3_clkdm", | 1621 | .clkdm_name = "core_l3_clkdm", |
1627 | .recalc = &followparent_recalc, | 1622 | .recalc = &followparent_recalc, |
1628 | }; | 1623 | }; |
@@ -1691,7 +1686,6 @@ static struct clk core_l4_ick = { | |||
1691 | .name = "core_l4_ick", | 1686 | .name = "core_l4_ick", |
1692 | .ops = &clkops_null, | 1687 | .ops = &clkops_null, |
1693 | .parent = &l4_ick, | 1688 | .parent = &l4_ick, |
1694 | .init = &omap2_init_clk_clkdm, | ||
1695 | .clkdm_name = "core_l4_clkdm", | 1689 | .clkdm_name = "core_l4_clkdm", |
1696 | .recalc = &followparent_recalc, | 1690 | .recalc = &followparent_recalc, |
1697 | }; | 1691 | }; |
@@ -2089,7 +2083,6 @@ static struct clk dss_tv_fck = { | |||
2089 | .name = "dss_tv_fck", | 2083 | .name = "dss_tv_fck", |
2090 | .ops = &clkops_omap2_dflt, | 2084 | .ops = &clkops_omap2_dflt, |
2091 | .parent = &omap_54m_fck, | 2085 | .parent = &omap_54m_fck, |
2092 | .init = &omap2_init_clk_clkdm, | ||
2093 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2086 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2094 | .enable_bit = OMAP3430_EN_TV_SHIFT, | 2087 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
2095 | .clkdm_name = "dss_clkdm", | 2088 | .clkdm_name = "dss_clkdm", |
@@ -2100,7 +2093,6 @@ static struct clk dss_96m_fck = { | |||
2100 | .name = "dss_96m_fck", | 2093 | .name = "dss_96m_fck", |
2101 | .ops = &clkops_omap2_dflt, | 2094 | .ops = &clkops_omap2_dflt, |
2102 | .parent = &omap_96m_fck, | 2095 | .parent = &omap_96m_fck, |
2103 | .init = &omap2_init_clk_clkdm, | ||
2104 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2096 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2105 | .enable_bit = OMAP3430_EN_TV_SHIFT, | 2097 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
2106 | .clkdm_name = "dss_clkdm", | 2098 | .clkdm_name = "dss_clkdm", |
@@ -2111,7 +2103,6 @@ static struct clk dss2_alwon_fck = { | |||
2111 | .name = "dss2_alwon_fck", | 2103 | .name = "dss2_alwon_fck", |
2112 | .ops = &clkops_omap2_dflt, | 2104 | .ops = &clkops_omap2_dflt, |
2113 | .parent = &sys_ck, | 2105 | .parent = &sys_ck, |
2114 | .init = &omap2_init_clk_clkdm, | ||
2115 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2106 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2116 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, | 2107 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, |
2117 | .clkdm_name = "dss_clkdm", | 2108 | .clkdm_name = "dss_clkdm", |
@@ -2123,7 +2114,6 @@ static struct clk dss_ick_3430es1 = { | |||
2123 | .name = "dss_ick", | 2114 | .name = "dss_ick", |
2124 | .ops = &clkops_omap2_dflt, | 2115 | .ops = &clkops_omap2_dflt, |
2125 | .parent = &l4_ick, | 2116 | .parent = &l4_ick, |
2126 | .init = &omap2_init_clk_clkdm, | ||
2127 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | 2117 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
2128 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | 2118 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, |
2129 | .clkdm_name = "dss_clkdm", | 2119 | .clkdm_name = "dss_clkdm", |
@@ -2135,7 +2125,6 @@ static struct clk dss_ick_3430es2 = { | |||
2135 | .name = "dss_ick", | 2125 | .name = "dss_ick", |
2136 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | 2126 | .ops = &clkops_omap3430es2_dss_usbhost_wait, |
2137 | .parent = &l4_ick, | 2127 | .parent = &l4_ick, |
2138 | .init = &omap2_init_clk_clkdm, | ||
2139 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | 2128 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
2140 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | 2129 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, |
2141 | .clkdm_name = "dss_clkdm", | 2130 | .clkdm_name = "dss_clkdm", |
@@ -2159,7 +2148,6 @@ static struct clk cam_ick = { | |||
2159 | .name = "cam_ick", | 2148 | .name = "cam_ick", |
2160 | .ops = &clkops_omap2_dflt, | 2149 | .ops = &clkops_omap2_dflt, |
2161 | .parent = &l4_ick, | 2150 | .parent = &l4_ick, |
2162 | .init = &omap2_init_clk_clkdm, | ||
2163 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | 2151 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), |
2164 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | 2152 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
2165 | .clkdm_name = "cam_clkdm", | 2153 | .clkdm_name = "cam_clkdm", |
@@ -2170,7 +2158,6 @@ static struct clk csi2_96m_fck = { | |||
2170 | .name = "csi2_96m_fck", | 2158 | .name = "csi2_96m_fck", |
2171 | .ops = &clkops_omap2_dflt, | 2159 | .ops = &clkops_omap2_dflt, |
2172 | .parent = &core_96m_fck, | 2160 | .parent = &core_96m_fck, |
2173 | .init = &omap2_init_clk_clkdm, | ||
2174 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | 2161 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), |
2175 | .enable_bit = OMAP3430_EN_CSI2_SHIFT, | 2162 | .enable_bit = OMAP3430_EN_CSI2_SHIFT, |
2176 | .clkdm_name = "cam_clkdm", | 2163 | .clkdm_name = "cam_clkdm", |
@@ -2183,7 +2170,6 @@ static struct clk usbhost_120m_fck = { | |||
2183 | .name = "usbhost_120m_fck", | 2170 | .name = "usbhost_120m_fck", |
2184 | .ops = &clkops_omap2_dflt, | 2171 | .ops = &clkops_omap2_dflt, |
2185 | .parent = &dpll5_m2_ck, | 2172 | .parent = &dpll5_m2_ck, |
2186 | .init = &omap2_init_clk_clkdm, | ||
2187 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | 2173 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
2188 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, | 2174 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, |
2189 | .clkdm_name = "usbhost_clkdm", | 2175 | .clkdm_name = "usbhost_clkdm", |
@@ -2194,7 +2180,6 @@ static struct clk usbhost_48m_fck = { | |||
2194 | .name = "usbhost_48m_fck", | 2180 | .name = "usbhost_48m_fck", |
2195 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | 2181 | .ops = &clkops_omap3430es2_dss_usbhost_wait, |
2196 | .parent = &omap_48m_fck, | 2182 | .parent = &omap_48m_fck, |
2197 | .init = &omap2_init_clk_clkdm, | ||
2198 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | 2183 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
2199 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, | 2184 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
2200 | .clkdm_name = "usbhost_clkdm", | 2185 | .clkdm_name = "usbhost_clkdm", |
@@ -2206,7 +2191,6 @@ static struct clk usbhost_ick = { | |||
2206 | .name = "usbhost_ick", | 2191 | .name = "usbhost_ick", |
2207 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | 2192 | .ops = &clkops_omap3430es2_dss_usbhost_wait, |
2208 | .parent = &l4_ick, | 2193 | .parent = &l4_ick, |
2209 | .init = &omap2_init_clk_clkdm, | ||
2210 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | 2194 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), |
2211 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | 2195 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, |
2212 | .clkdm_name = "usbhost_clkdm", | 2196 | .clkdm_name = "usbhost_clkdm", |
@@ -2268,7 +2252,6 @@ static struct clk gpt1_fck = { | |||
2268 | static struct clk wkup_32k_fck = { | 2252 | static struct clk wkup_32k_fck = { |
2269 | .name = "wkup_32k_fck", | 2253 | .name = "wkup_32k_fck", |
2270 | .ops = &clkops_null, | 2254 | .ops = &clkops_null, |
2271 | .init = &omap2_init_clk_clkdm, | ||
2272 | .parent = &omap_32k_fck, | 2255 | .parent = &omap_32k_fck, |
2273 | .clkdm_name = "wkup_clkdm", | 2256 | .clkdm_name = "wkup_clkdm", |
2274 | .recalc = &followparent_recalc, | 2257 | .recalc = &followparent_recalc, |
@@ -2383,7 +2366,6 @@ static struct clk per_96m_fck = { | |||
2383 | .name = "per_96m_fck", | 2366 | .name = "per_96m_fck", |
2384 | .ops = &clkops_null, | 2367 | .ops = &clkops_null, |
2385 | .parent = &omap_96m_alwon_fck, | 2368 | .parent = &omap_96m_alwon_fck, |
2386 | .init = &omap2_init_clk_clkdm, | ||
2387 | .clkdm_name = "per_clkdm", | 2369 | .clkdm_name = "per_clkdm", |
2388 | .recalc = &followparent_recalc, | 2370 | .recalc = &followparent_recalc, |
2389 | }; | 2371 | }; |
@@ -2392,7 +2374,6 @@ static struct clk per_48m_fck = { | |||
2392 | .name = "per_48m_fck", | 2374 | .name = "per_48m_fck", |
2393 | .ops = &clkops_null, | 2375 | .ops = &clkops_null, |
2394 | .parent = &omap_48m_fck, | 2376 | .parent = &omap_48m_fck, |
2395 | .init = &omap2_init_clk_clkdm, | ||
2396 | .clkdm_name = "per_clkdm", | 2377 | .clkdm_name = "per_clkdm", |
2397 | .recalc = &followparent_recalc, | 2378 | .recalc = &followparent_recalc, |
2398 | }; | 2379 | }; |