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-rw-r--r--arch/arm/mach-omap2/clock34xx.h1076
1 files changed, 380 insertions, 696 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index a826094d89b5..70ec10deb654 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -27,13 +27,14 @@
27#include "prm.h" 27#include "prm.h"
28#include "prm-regbits-34xx.h" 28#include "prm-regbits-34xx.h"
29 29
30static void omap3_dpll_recalc(struct clk *clk); 30static unsigned long omap3_dpll_recalc(struct clk *clk);
31static void omap3_clkoutx2_recalc(struct clk *clk); 31static unsigned long omap3_clkoutx2_recalc(struct clk *clk);
32static void omap3_dpll_allow_idle(struct clk *clk); 32static void omap3_dpll_allow_idle(struct clk *clk);
33static void omap3_dpll_deny_idle(struct clk *clk); 33static void omap3_dpll_deny_idle(struct clk *clk);
34static u32 omap3_dpll_autoidle_read(struct clk *clk); 34static u32 omap3_dpll_autoidle_read(struct clk *clk);
35static int omap3_noncore_dpll_enable(struct clk *clk); 35static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
36static void omap3_noncore_dpll_disable(struct clk *clk); 36static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
37static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
37 38
38/* Maximum DPLL multiplier, divider values for OMAP3 */ 39/* Maximum DPLL multiplier, divider values for OMAP3 */
39#define OMAP3_MAX_DPLL_MULT 2048 40#define OMAP3_MAX_DPLL_MULT 2048
@@ -47,6 +48,10 @@ static void omap3_noncore_dpll_disable(struct clk *clk);
47 * DPLL5 supplies other peripheral clocks (USBHOST, USIM). 48 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
48 */ 49 */
49 50
51/* Forward declarations for DPLL bypass clocks */
52static struct clk dpll1_fck;
53static struct clk dpll2_fck;
54
50/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ 55/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
51#define DPLL_LOW_POWER_STOP 0x1 56#define DPLL_LOW_POWER_STOP 0x1
52#define DPLL_LOW_POWER_BYPASS 0x5 57#define DPLL_LOW_POWER_BYPASS 0x5
@@ -57,67 +62,59 @@ static void omap3_noncore_dpll_disable(struct clk *clk);
57/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ 62/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
58static struct clk omap_32k_fck = { 63static struct clk omap_32k_fck = {
59 .name = "omap_32k_fck", 64 .name = "omap_32k_fck",
65 .ops = &clkops_null,
60 .rate = 32768, 66 .rate = 32768,
61 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 67 .flags = RATE_FIXED,
62 ALWAYS_ENABLED,
63 .recalc = &propagate_rate,
64}; 68};
65 69
66static struct clk secure_32k_fck = { 70static struct clk secure_32k_fck = {
67 .name = "secure_32k_fck", 71 .name = "secure_32k_fck",
72 .ops = &clkops_null,
68 .rate = 32768, 73 .rate = 32768,
69 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 74 .flags = RATE_FIXED,
70 ALWAYS_ENABLED,
71 .recalc = &propagate_rate,
72}; 75};
73 76
74/* Virtual source clocks for osc_sys_ck */ 77/* Virtual source clocks for osc_sys_ck */
75static struct clk virt_12m_ck = { 78static struct clk virt_12m_ck = {
76 .name = "virt_12m_ck", 79 .name = "virt_12m_ck",
80 .ops = &clkops_null,
77 .rate = 12000000, 81 .rate = 12000000,
78 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 82 .flags = RATE_FIXED,
79 ALWAYS_ENABLED,
80 .recalc = &propagate_rate,
81}; 83};
82 84
83static struct clk virt_13m_ck = { 85static struct clk virt_13m_ck = {
84 .name = "virt_13m_ck", 86 .name = "virt_13m_ck",
87 .ops = &clkops_null,
85 .rate = 13000000, 88 .rate = 13000000,
86 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 89 .flags = RATE_FIXED,
87 ALWAYS_ENABLED,
88 .recalc = &propagate_rate,
89}; 90};
90 91
91static struct clk virt_16_8m_ck = { 92static struct clk virt_16_8m_ck = {
92 .name = "virt_16_8m_ck", 93 .name = "virt_16_8m_ck",
94 .ops = &clkops_null,
93 .rate = 16800000, 95 .rate = 16800000,
94 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES | 96 .flags = RATE_FIXED,
95 ALWAYS_ENABLED,
96 .recalc = &propagate_rate,
97}; 97};
98 98
99static struct clk virt_19_2m_ck = { 99static struct clk virt_19_2m_ck = {
100 .name = "virt_19_2m_ck", 100 .name = "virt_19_2m_ck",
101 .ops = &clkops_null,
101 .rate = 19200000, 102 .rate = 19200000,
102 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 103 .flags = RATE_FIXED,
103 ALWAYS_ENABLED,
104 .recalc = &propagate_rate,
105}; 104};
106 105
107static struct clk virt_26m_ck = { 106static struct clk virt_26m_ck = {
108 .name = "virt_26m_ck", 107 .name = "virt_26m_ck",
108 .ops = &clkops_null,
109 .rate = 26000000, 109 .rate = 26000000,
110 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 110 .flags = RATE_FIXED,
111 ALWAYS_ENABLED,
112 .recalc = &propagate_rate,
113}; 111};
114 112
115static struct clk virt_38_4m_ck = { 113static struct clk virt_38_4m_ck = {
116 .name = "virt_38_4m_ck", 114 .name = "virt_38_4m_ck",
115 .ops = &clkops_null,
117 .rate = 38400000, 116 .rate = 38400000,
118 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 117 .flags = RATE_FIXED,
119 ALWAYS_ENABLED,
120 .recalc = &propagate_rate,
121}; 118};
122 119
123static const struct clksel_rate osc_sys_12m_rates[] = { 120static const struct clksel_rate osc_sys_12m_rates[] = {
@@ -164,13 +161,13 @@ static const struct clksel osc_sys_clksel[] = {
164/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ 161/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
165static struct clk osc_sys_ck = { 162static struct clk osc_sys_ck = {
166 .name = "osc_sys_ck", 163 .name = "osc_sys_ck",
164 .ops = &clkops_null,
167 .init = &omap2_init_clksel_parent, 165 .init = &omap2_init_clksel_parent,
168 .clksel_reg = OMAP3430_PRM_CLKSEL, 166 .clksel_reg = OMAP3430_PRM_CLKSEL,
169 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, 167 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
170 .clksel = osc_sys_clksel, 168 .clksel = osc_sys_clksel,
171 /* REVISIT: deal with autoextclkmode? */ 169 /* REVISIT: deal with autoextclkmode? */
172 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 170 .flags = RATE_FIXED,
173 ALWAYS_ENABLED,
174 .recalc = &omap2_clksel_recalc, 171 .recalc = &omap2_clksel_recalc,
175}; 172};
176 173
@@ -189,36 +186,34 @@ static const struct clksel sys_clksel[] = {
189/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ 186/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
190static struct clk sys_ck = { 187static struct clk sys_ck = {
191 .name = "sys_ck", 188 .name = "sys_ck",
189 .ops = &clkops_null,
192 .parent = &osc_sys_ck, 190 .parent = &osc_sys_ck,
193 .init = &omap2_init_clksel_parent, 191 .init = &omap2_init_clksel_parent,
194 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, 192 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
195 .clksel_mask = OMAP_SYSCLKDIV_MASK, 193 .clksel_mask = OMAP_SYSCLKDIV_MASK,
196 .clksel = sys_clksel, 194 .clksel = sys_clksel,
197 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
198 .recalc = &omap2_clksel_recalc, 195 .recalc = &omap2_clksel_recalc,
199}; 196};
200 197
201static struct clk sys_altclk = { 198static struct clk sys_altclk = {
202 .name = "sys_altclk", 199 .name = "sys_altclk",
203 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 200 .ops = &clkops_null,
204 .recalc = &propagate_rate,
205}; 201};
206 202
207/* Optional external clock input for some McBSPs */ 203/* Optional external clock input for some McBSPs */
208static struct clk mcbsp_clks = { 204static struct clk mcbsp_clks = {
209 .name = "mcbsp_clks", 205 .name = "mcbsp_clks",
210 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 206 .ops = &clkops_null,
211 .recalc = &propagate_rate,
212}; 207};
213 208
214/* PRM EXTERNAL CLOCK OUTPUT */ 209/* PRM EXTERNAL CLOCK OUTPUT */
215 210
216static struct clk sys_clkout1 = { 211static struct clk sys_clkout1 = {
217 .name = "sys_clkout1", 212 .name = "sys_clkout1",
213 .ops = &clkops_omap2_dflt,
218 .parent = &osc_sys_ck, 214 .parent = &osc_sys_ck,
219 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, 215 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
220 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, 216 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
221 .flags = CLOCK_IN_OMAP343X,
222 .recalc = &followparent_recalc, 217 .recalc = &followparent_recalc,
223}; 218};
224 219
@@ -226,16 +221,6 @@ static struct clk sys_clkout1 = {
226 221
227/* CM CLOCKS */ 222/* CM CLOCKS */
228 223
229static const struct clksel_rate dpll_bypass_rates[] = {
230 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
231 { .div = 0 }
232};
233
234static const struct clksel_rate dpll_locked_rates[] = {
235 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
236 { .div = 0 }
237};
238
239static const struct clksel_rate div16_dpll_rates[] = { 224static const struct clksel_rate div16_dpll_rates[] = {
240 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 225 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
241 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 226 { .div = 2, .val = 2, .flags = RATE_IN_343X },
@@ -263,6 +248,9 @@ static struct dpll_data dpll1_dd = {
263 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), 248 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
264 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, 249 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
265 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, 250 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
251 .clk_bypass = &dpll1_fck,
252 .clk_ref = &sys_ck,
253 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
266 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), 254 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
267 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, 255 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
268 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 256 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
@@ -272,18 +260,21 @@ static struct dpll_data dpll1_dd = {
272 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), 260 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
273 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, 261 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
274 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), 262 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
275 .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT, 263 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
276 .max_multiplier = OMAP3_MAX_DPLL_MULT, 264 .max_multiplier = OMAP3_MAX_DPLL_MULT,
265 .min_divider = 1,
277 .max_divider = OMAP3_MAX_DPLL_DIV, 266 .max_divider = OMAP3_MAX_DPLL_DIV,
278 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 267 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
279}; 268};
280 269
281static struct clk dpll1_ck = { 270static struct clk dpll1_ck = {
282 .name = "dpll1_ck", 271 .name = "dpll1_ck",
272 .ops = &clkops_null,
283 .parent = &sys_ck, 273 .parent = &sys_ck,
284 .dpll_data = &dpll1_dd, 274 .dpll_data = &dpll1_dd,
285 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
286 .round_rate = &omap2_dpll_round_rate, 275 .round_rate = &omap2_dpll_round_rate,
276 .set_rate = &omap3_noncore_dpll_set_rate,
277 .clkdm_name = "dpll1_clkdm",
287 .recalc = &omap3_dpll_recalc, 278 .recalc = &omap3_dpll_recalc,
288}; 279};
289 280
@@ -293,9 +284,9 @@ static struct clk dpll1_ck = {
293 */ 284 */
294static struct clk dpll1_x2_ck = { 285static struct clk dpll1_x2_ck = {
295 .name = "dpll1_x2_ck", 286 .name = "dpll1_x2_ck",
287 .ops = &clkops_null,
296 .parent = &dpll1_ck, 288 .parent = &dpll1_ck,
297 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 289 .clkdm_name = "dpll1_clkdm",
298 PARENT_CONTROLS_CLOCK,
299 .recalc = &omap3_clkoutx2_recalc, 290 .recalc = &omap3_clkoutx2_recalc,
300}; 291};
301 292
@@ -311,13 +302,13 @@ static const struct clksel div16_dpll1_x2m2_clksel[] = {
311 */ 302 */
312static struct clk dpll1_x2m2_ck = { 303static struct clk dpll1_x2m2_ck = {
313 .name = "dpll1_x2m2_ck", 304 .name = "dpll1_x2m2_ck",
305 .ops = &clkops_null,
314 .parent = &dpll1_x2_ck, 306 .parent = &dpll1_x2_ck,
315 .init = &omap2_init_clksel_parent, 307 .init = &omap2_init_clksel_parent,
316 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), 308 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
317 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, 309 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
318 .clksel = div16_dpll1_x2m2_clksel, 310 .clksel = div16_dpll1_x2m2_clksel,
319 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 311 .clkdm_name = "dpll1_clkdm",
320 PARENT_CONTROLS_CLOCK,
321 .recalc = &omap2_clksel_recalc, 312 .recalc = &omap2_clksel_recalc,
322}; 313};
323 314
@@ -329,6 +320,9 @@ static struct dpll_data dpll2_dd = {
329 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), 320 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
330 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, 321 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
331 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, 322 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
323 .clk_bypass = &dpll2_fck,
324 .clk_ref = &sys_ck,
325 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
332 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), 326 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
333 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, 327 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
334 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | 328 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
@@ -339,20 +333,21 @@ static struct dpll_data dpll2_dd = {
339 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), 333 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
340 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, 334 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
341 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), 335 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
342 .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT, 336 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
343 .max_multiplier = OMAP3_MAX_DPLL_MULT, 337 .max_multiplier = OMAP3_MAX_DPLL_MULT,
338 .min_divider = 1,
344 .max_divider = OMAP3_MAX_DPLL_DIV, 339 .max_divider = OMAP3_MAX_DPLL_DIV,
345 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 340 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
346}; 341};
347 342
348static struct clk dpll2_ck = { 343static struct clk dpll2_ck = {
349 .name = "dpll2_ck", 344 .name = "dpll2_ck",
345 .ops = &clkops_noncore_dpll_ops,
350 .parent = &sys_ck, 346 .parent = &sys_ck,
351 .dpll_data = &dpll2_dd, 347 .dpll_data = &dpll2_dd,
352 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
353 .enable = &omap3_noncore_dpll_enable,
354 .disable = &omap3_noncore_dpll_disable,
355 .round_rate = &omap2_dpll_round_rate, 348 .round_rate = &omap2_dpll_round_rate,
349 .set_rate = &omap3_noncore_dpll_set_rate,
350 .clkdm_name = "dpll2_clkdm",
356 .recalc = &omap3_dpll_recalc, 351 .recalc = &omap3_dpll_recalc,
357}; 352};
358 353
@@ -367,14 +362,14 @@ static const struct clksel div16_dpll2_m2x2_clksel[] = {
367 */ 362 */
368static struct clk dpll2_m2_ck = { 363static struct clk dpll2_m2_ck = {
369 .name = "dpll2_m2_ck", 364 .name = "dpll2_m2_ck",
365 .ops = &clkops_null,
370 .parent = &dpll2_ck, 366 .parent = &dpll2_ck,
371 .init = &omap2_init_clksel_parent, 367 .init = &omap2_init_clksel_parent,
372 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, 368 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
373 OMAP3430_CM_CLKSEL2_PLL), 369 OMAP3430_CM_CLKSEL2_PLL),
374 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, 370 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
375 .clksel = div16_dpll2_m2x2_clksel, 371 .clksel = div16_dpll2_m2x2_clksel,
376 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 372 .clkdm_name = "dpll2_clkdm",
377 PARENT_CONTROLS_CLOCK,
378 .recalc = &omap2_clksel_recalc, 373 .recalc = &omap2_clksel_recalc,
379}; 374};
380 375
@@ -387,6 +382,9 @@ static struct dpll_data dpll3_dd = {
387 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 382 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
388 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, 383 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
389 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, 384 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
385 .clk_bypass = &sys_ck,
386 .clk_ref = &sys_ck,
387 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
390 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 388 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
391 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, 389 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
392 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, 390 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
@@ -394,17 +392,21 @@ static struct dpll_data dpll3_dd = {
394 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, 392 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
395 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), 393 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
396 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, 394 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
395 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
396 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
397 .max_multiplier = OMAP3_MAX_DPLL_MULT, 397 .max_multiplier = OMAP3_MAX_DPLL_MULT,
398 .min_divider = 1,
398 .max_divider = OMAP3_MAX_DPLL_DIV, 399 .max_divider = OMAP3_MAX_DPLL_DIV,
399 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 400 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
400}; 401};
401 402
402static struct clk dpll3_ck = { 403static struct clk dpll3_ck = {
403 .name = "dpll3_ck", 404 .name = "dpll3_ck",
405 .ops = &clkops_null,
404 .parent = &sys_ck, 406 .parent = &sys_ck,
405 .dpll_data = &dpll3_dd, 407 .dpll_data = &dpll3_dd,
406 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
407 .round_rate = &omap2_dpll_round_rate, 408 .round_rate = &omap2_dpll_round_rate,
409 .clkdm_name = "dpll3_clkdm",
408 .recalc = &omap3_dpll_recalc, 410 .recalc = &omap3_dpll_recalc,
409}; 411};
410 412
@@ -414,9 +416,9 @@ static struct clk dpll3_ck = {
414 */ 416 */
415static struct clk dpll3_x2_ck = { 417static struct clk dpll3_x2_ck = {
416 .name = "dpll3_x2_ck", 418 .name = "dpll3_x2_ck",
419 .ops = &clkops_null,
417 .parent = &dpll3_ck, 420 .parent = &dpll3_ck,
418 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 421 .clkdm_name = "dpll3_clkdm",
419 PARENT_CONTROLS_CLOCK,
420 .recalc = &omap3_clkoutx2_recalc, 422 .recalc = &omap3_clkoutx2_recalc,
421}; 423};
422 424
@@ -460,55 +462,34 @@ static const struct clksel div31_dpll3m2_clksel[] = {
460 { .parent = NULL } 462 { .parent = NULL }
461}; 463};
462 464
463/* 465/* DPLL3 output M2 - primary control point for CORE speed */
464 * DPLL3 output M2
465 * REVISIT: This DPLL output divider must be changed in SRAM, so until
466 * that code is ready, this should remain a 'read-only' clksel clock.
467 */
468static struct clk dpll3_m2_ck = { 466static struct clk dpll3_m2_ck = {
469 .name = "dpll3_m2_ck", 467 .name = "dpll3_m2_ck",
468 .ops = &clkops_null,
470 .parent = &dpll3_ck, 469 .parent = &dpll3_ck,
471 .init = &omap2_init_clksel_parent, 470 .init = &omap2_init_clksel_parent,
472 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 471 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
473 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, 472 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
474 .clksel = div31_dpll3m2_clksel, 473 .clksel = div31_dpll3m2_clksel,
475 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 474 .clkdm_name = "dpll3_clkdm",
476 PARENT_CONTROLS_CLOCK, 475 .round_rate = &omap2_clksel_round_rate,
476 .set_rate = &omap3_core_dpll_m2_set_rate,
477 .recalc = &omap2_clksel_recalc, 477 .recalc = &omap2_clksel_recalc,
478}; 478};
479 479
480static const struct clksel core_ck_clksel[] = {
481 { .parent = &sys_ck, .rates = dpll_bypass_rates },
482 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
483 { .parent = NULL }
484};
485
486static struct clk core_ck = { 480static struct clk core_ck = {
487 .name = "core_ck", 481 .name = "core_ck",
488 .init = &omap2_init_clksel_parent, 482 .ops = &clkops_null,
489 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 483 .parent = &dpll3_m2_ck,
490 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, 484 .recalc = &followparent_recalc,
491 .clksel = core_ck_clksel,
492 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
493 PARENT_CONTROLS_CLOCK,
494 .recalc = &omap2_clksel_recalc,
495};
496
497static const struct clksel dpll3_m2x2_ck_clksel[] = {
498 { .parent = &sys_ck, .rates = dpll_bypass_rates },
499 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
500 { .parent = NULL }
501}; 485};
502 486
503static struct clk dpll3_m2x2_ck = { 487static struct clk dpll3_m2x2_ck = {
504 .name = "dpll3_m2x2_ck", 488 .name = "dpll3_m2x2_ck",
505 .init = &omap2_init_clksel_parent, 489 .ops = &clkops_null,
506 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 490 .parent = &dpll3_x2_ck,
507 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, 491 .clkdm_name = "dpll3_clkdm",
508 .clksel = dpll3_m2x2_ck_clksel, 492 .recalc = &followparent_recalc,
509 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
510 PARENT_CONTROLS_CLOCK,
511 .recalc = &omap2_clksel_recalc,
512}; 493};
513 494
514/* The PWRDN bit is apparently only available on 3430ES2 and above */ 495/* The PWRDN bit is apparently only available on 3430ES2 and above */
@@ -520,42 +501,34 @@ static const struct clksel div16_dpll3_clksel[] = {
520/* This virtual clock is the source for dpll3_m3x2_ck */ 501/* This virtual clock is the source for dpll3_m3x2_ck */
521static struct clk dpll3_m3_ck = { 502static struct clk dpll3_m3_ck = {
522 .name = "dpll3_m3_ck", 503 .name = "dpll3_m3_ck",
504 .ops = &clkops_null,
523 .parent = &dpll3_ck, 505 .parent = &dpll3_ck,
524 .init = &omap2_init_clksel_parent, 506 .init = &omap2_init_clksel_parent,
525 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 507 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
526 .clksel_mask = OMAP3430_DIV_DPLL3_MASK, 508 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
527 .clksel = div16_dpll3_clksel, 509 .clksel = div16_dpll3_clksel,
528 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 510 .clkdm_name = "dpll3_clkdm",
529 PARENT_CONTROLS_CLOCK,
530 .recalc = &omap2_clksel_recalc, 511 .recalc = &omap2_clksel_recalc,
531}; 512};
532 513
533/* The PWRDN bit is apparently only available on 3430ES2 and above */ 514/* The PWRDN bit is apparently only available on 3430ES2 and above */
534static struct clk dpll3_m3x2_ck = { 515static struct clk dpll3_m3x2_ck = {
535 .name = "dpll3_m3x2_ck", 516 .name = "dpll3_m3x2_ck",
517 .ops = &clkops_omap2_dflt_wait,
536 .parent = &dpll3_m3_ck, 518 .parent = &dpll3_m3_ck,
537 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 519 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
538 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, 520 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
539 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 521 .flags = INVERT_ENABLE,
522 .clkdm_name = "dpll3_clkdm",
540 .recalc = &omap3_clkoutx2_recalc, 523 .recalc = &omap3_clkoutx2_recalc,
541}; 524};
542 525
543static const struct clksel emu_core_alwon_ck_clksel[] = {
544 { .parent = &sys_ck, .rates = dpll_bypass_rates },
545 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
546 { .parent = NULL }
547};
548
549static struct clk emu_core_alwon_ck = { 526static struct clk emu_core_alwon_ck = {
550 .name = "emu_core_alwon_ck", 527 .name = "emu_core_alwon_ck",
528 .ops = &clkops_null,
551 .parent = &dpll3_m3x2_ck, 529 .parent = &dpll3_m3x2_ck,
552 .init = &omap2_init_clksel_parent, 530 .clkdm_name = "dpll3_clkdm",
553 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 531 .recalc = &followparent_recalc,
554 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
555 .clksel = emu_core_alwon_ck_clksel,
556 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
557 PARENT_CONTROLS_CLOCK,
558 .recalc = &omap2_clksel_recalc,
559}; 532};
560 533
561/* DPLL4 */ 534/* DPLL4 */
@@ -565,6 +538,9 @@ static struct dpll_data dpll4_dd = {
565 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), 538 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
566 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, 539 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
567 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, 540 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
541 .clk_bypass = &sys_ck,
542 .clk_ref = &sys_ck,
543 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
568 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 544 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
569 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, 545 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
570 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 546 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
@@ -574,20 +550,21 @@ static struct dpll_data dpll4_dd = {
574 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), 550 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
575 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, 551 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
576 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 552 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
577 .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT, 553 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
578 .max_multiplier = OMAP3_MAX_DPLL_MULT, 554 .max_multiplier = OMAP3_MAX_DPLL_MULT,
555 .min_divider = 1,
579 .max_divider = OMAP3_MAX_DPLL_DIV, 556 .max_divider = OMAP3_MAX_DPLL_DIV,
580 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 557 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
581}; 558};
582 559
583static struct clk dpll4_ck = { 560static struct clk dpll4_ck = {
584 .name = "dpll4_ck", 561 .name = "dpll4_ck",
562 .ops = &clkops_noncore_dpll_ops,
585 .parent = &sys_ck, 563 .parent = &sys_ck,
586 .dpll_data = &dpll4_dd, 564 .dpll_data = &dpll4_dd,
587 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
588 .enable = &omap3_noncore_dpll_enable,
589 .disable = &omap3_noncore_dpll_disable,
590 .round_rate = &omap2_dpll_round_rate, 565 .round_rate = &omap2_dpll_round_rate,
566 .set_rate = &omap3_dpll4_set_rate,
567 .clkdm_name = "dpll4_clkdm",
591 .recalc = &omap3_dpll_recalc, 568 .recalc = &omap3_dpll_recalc,
592}; 569};
593 570
@@ -598,9 +575,9 @@ static struct clk dpll4_ck = {
598 */ 575 */
599static struct clk dpll4_x2_ck = { 576static struct clk dpll4_x2_ck = {
600 .name = "dpll4_x2_ck", 577 .name = "dpll4_x2_ck",
578 .ops = &clkops_null,
601 .parent = &dpll4_ck, 579 .parent = &dpll4_ck,
602 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 580 .clkdm_name = "dpll4_clkdm",
603 PARENT_CONTROLS_CLOCK,
604 .recalc = &omap3_clkoutx2_recalc, 581 .recalc = &omap3_clkoutx2_recalc,
605}; 582};
606 583
@@ -612,112 +589,101 @@ static const struct clksel div16_dpll4_clksel[] = {
612/* This virtual clock is the source for dpll4_m2x2_ck */ 589/* This virtual clock is the source for dpll4_m2x2_ck */
613static struct clk dpll4_m2_ck = { 590static struct clk dpll4_m2_ck = {
614 .name = "dpll4_m2_ck", 591 .name = "dpll4_m2_ck",
592 .ops = &clkops_null,
615 .parent = &dpll4_ck, 593 .parent = &dpll4_ck,
616 .init = &omap2_init_clksel_parent, 594 .init = &omap2_init_clksel_parent,
617 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), 595 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
618 .clksel_mask = OMAP3430_DIV_96M_MASK, 596 .clksel_mask = OMAP3430_DIV_96M_MASK,
619 .clksel = div16_dpll4_clksel, 597 .clksel = div16_dpll4_clksel,
620 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 598 .clkdm_name = "dpll4_clkdm",
621 PARENT_CONTROLS_CLOCK,
622 .recalc = &omap2_clksel_recalc, 599 .recalc = &omap2_clksel_recalc,
623}; 600};
624 601
625/* The PWRDN bit is apparently only available on 3430ES2 and above */ 602/* The PWRDN bit is apparently only available on 3430ES2 and above */
626static struct clk dpll4_m2x2_ck = { 603static struct clk dpll4_m2x2_ck = {
627 .name = "dpll4_m2x2_ck", 604 .name = "dpll4_m2x2_ck",
605 .ops = &clkops_omap2_dflt_wait,
628 .parent = &dpll4_m2_ck, 606 .parent = &dpll4_m2_ck,
629 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 607 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
630 .enable_bit = OMAP3430_PWRDN_96M_SHIFT, 608 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
631 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 609 .flags = INVERT_ENABLE,
610 .clkdm_name = "dpll4_clkdm",
632 .recalc = &omap3_clkoutx2_recalc, 611 .recalc = &omap3_clkoutx2_recalc,
633}; 612};
634 613
635static const struct clksel omap_96m_alwon_fck_clksel[] = { 614/*
636 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 615 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
637 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, 616 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
638 { .parent = NULL } 617 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
639}; 618 * CM_96K_(F)CLK.
640 619 */
641static struct clk omap_96m_alwon_fck = { 620static struct clk omap_96m_alwon_fck = {
642 .name = "omap_96m_alwon_fck", 621 .name = "omap_96m_alwon_fck",
622 .ops = &clkops_null,
643 .parent = &dpll4_m2x2_ck, 623 .parent = &dpll4_m2x2_ck,
644 .init = &omap2_init_clksel_parent, 624 .recalc = &followparent_recalc,
645 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
646 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
647 .clksel = omap_96m_alwon_fck_clksel,
648 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
649 PARENT_CONTROLS_CLOCK,
650 .recalc = &omap2_clksel_recalc,
651}; 625};
652 626
653static struct clk omap_96m_fck = { 627static struct clk cm_96m_fck = {
654 .name = "omap_96m_fck", 628 .name = "cm_96m_fck",
629 .ops = &clkops_null,
655 .parent = &omap_96m_alwon_fck, 630 .parent = &omap_96m_alwon_fck,
656 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
657 PARENT_CONTROLS_CLOCK,
658 .recalc = &followparent_recalc, 631 .recalc = &followparent_recalc,
659}; 632};
660 633
661static const struct clksel cm_96m_fck_clksel[] = { 634static const struct clksel_rate omap_96m_dpll_rates[] = {
662 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 635 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
663 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, 636 { .div = 0 }
637};
638
639static const struct clksel_rate omap_96m_sys_rates[] = {
640 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
641 { .div = 0 }
642};
643
644static const struct clksel omap_96m_fck_clksel[] = {
645 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
646 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
664 { .parent = NULL } 647 { .parent = NULL }
665}; 648};
666 649
667static struct clk cm_96m_fck = { 650static struct clk omap_96m_fck = {
668 .name = "cm_96m_fck", 651 .name = "omap_96m_fck",
669 .parent = &dpll4_m2x2_ck, 652 .ops = &clkops_null,
653 .parent = &sys_ck,
670 .init = &omap2_init_clksel_parent, 654 .init = &omap2_init_clksel_parent,
671 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 655 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
672 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 656 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
673 .clksel = cm_96m_fck_clksel, 657 .clksel = omap_96m_fck_clksel,
674 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
675 PARENT_CONTROLS_CLOCK,
676 .recalc = &omap2_clksel_recalc, 658 .recalc = &omap2_clksel_recalc,
677}; 659};
678 660
679/* This virtual clock is the source for dpll4_m3x2_ck */ 661/* This virtual clock is the source for dpll4_m3x2_ck */
680static struct clk dpll4_m3_ck = { 662static struct clk dpll4_m3_ck = {
681 .name = "dpll4_m3_ck", 663 .name = "dpll4_m3_ck",
664 .ops = &clkops_null,
682 .parent = &dpll4_ck, 665 .parent = &dpll4_ck,
683 .init = &omap2_init_clksel_parent, 666 .init = &omap2_init_clksel_parent,
684 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 667 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
685 .clksel_mask = OMAP3430_CLKSEL_TV_MASK, 668 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
686 .clksel = div16_dpll4_clksel, 669 .clksel = div16_dpll4_clksel,
687 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 670 .clkdm_name = "dpll4_clkdm",
688 PARENT_CONTROLS_CLOCK,
689 .recalc = &omap2_clksel_recalc, 671 .recalc = &omap2_clksel_recalc,
690}; 672};
691 673
692/* The PWRDN bit is apparently only available on 3430ES2 and above */ 674/* The PWRDN bit is apparently only available on 3430ES2 and above */
693static struct clk dpll4_m3x2_ck = { 675static struct clk dpll4_m3x2_ck = {
694 .name = "dpll4_m3x2_ck", 676 .name = "dpll4_m3x2_ck",
677 .ops = &clkops_omap2_dflt_wait,
695 .parent = &dpll4_m3_ck, 678 .parent = &dpll4_m3_ck,
696 .init = &omap2_init_clksel_parent, 679 .init = &omap2_init_clksel_parent,
697 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 680 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
698 .enable_bit = OMAP3430_PWRDN_TV_SHIFT, 681 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
699 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 682 .flags = INVERT_ENABLE,
683 .clkdm_name = "dpll4_clkdm",
700 .recalc = &omap3_clkoutx2_recalc, 684 .recalc = &omap3_clkoutx2_recalc,
701}; 685};
702 686
703static const struct clksel virt_omap_54m_fck_clksel[] = {
704 { .parent = &sys_ck, .rates = dpll_bypass_rates },
705 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
706 { .parent = NULL }
707};
708
709static struct clk virt_omap_54m_fck = {
710 .name = "virt_omap_54m_fck",
711 .parent = &dpll4_m3x2_ck,
712 .init = &omap2_init_clksel_parent,
713 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
714 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
715 .clksel = virt_omap_54m_fck_clksel,
716 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
717 PARENT_CONTROLS_CLOCK,
718 .recalc = &omap2_clksel_recalc,
719};
720
721static const struct clksel_rate omap_54m_d4m3x2_rates[] = { 687static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
722 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 688 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
723 { .div = 0 } 689 { .div = 0 }
@@ -729,23 +695,22 @@ static const struct clksel_rate omap_54m_alt_rates[] = {
729}; 695};
730 696
731static const struct clksel omap_54m_clksel[] = { 697static const struct clksel omap_54m_clksel[] = {
732 { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates }, 698 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
733 { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, 699 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
734 { .parent = NULL } 700 { .parent = NULL }
735}; 701};
736 702
737static struct clk omap_54m_fck = { 703static struct clk omap_54m_fck = {
738 .name = "omap_54m_fck", 704 .name = "omap_54m_fck",
705 .ops = &clkops_null,
739 .init = &omap2_init_clksel_parent, 706 .init = &omap2_init_clksel_parent,
740 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 707 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
741 .clksel_mask = OMAP3430_SOURCE_54M, 708 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
742 .clksel = omap_54m_clksel, 709 .clksel = omap_54m_clksel,
743 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
744 PARENT_CONTROLS_CLOCK,
745 .recalc = &omap2_clksel_recalc, 710 .recalc = &omap2_clksel_recalc,
746}; 711};
747 712
748static const struct clksel_rate omap_48m_96md2_rates[] = { 713static const struct clksel_rate omap_48m_cm96m_rates[] = {
749 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 714 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
750 { .div = 0 } 715 { .div = 0 }
751}; 716};
@@ -756,106 +721,112 @@ static const struct clksel_rate omap_48m_alt_rates[] = {
756}; 721};
757 722
758static const struct clksel omap_48m_clksel[] = { 723static const struct clksel omap_48m_clksel[] = {
759 { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates }, 724 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
760 { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, 725 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
761 { .parent = NULL } 726 { .parent = NULL }
762}; 727};
763 728
764static struct clk omap_48m_fck = { 729static struct clk omap_48m_fck = {
765 .name = "omap_48m_fck", 730 .name = "omap_48m_fck",
731 .ops = &clkops_null,
766 .init = &omap2_init_clksel_parent, 732 .init = &omap2_init_clksel_parent,
767 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 733 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
768 .clksel_mask = OMAP3430_SOURCE_48M, 734 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
769 .clksel = omap_48m_clksel, 735 .clksel = omap_48m_clksel,
770 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
771 PARENT_CONTROLS_CLOCK,
772 .recalc = &omap2_clksel_recalc, 736 .recalc = &omap2_clksel_recalc,
773}; 737};
774 738
775static struct clk omap_12m_fck = { 739static struct clk omap_12m_fck = {
776 .name = "omap_12m_fck", 740 .name = "omap_12m_fck",
741 .ops = &clkops_null,
777 .parent = &omap_48m_fck, 742 .parent = &omap_48m_fck,
778 .fixed_div = 4, 743 .fixed_div = 4,
779 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
780 PARENT_CONTROLS_CLOCK,
781 .recalc = &omap2_fixed_divisor_recalc, 744 .recalc = &omap2_fixed_divisor_recalc,
782}; 745};
783 746
784/* This virstual clock is the source for dpll4_m4x2_ck */ 747/* This virstual clock is the source for dpll4_m4x2_ck */
785static struct clk dpll4_m4_ck = { 748static struct clk dpll4_m4_ck = {
786 .name = "dpll4_m4_ck", 749 .name = "dpll4_m4_ck",
750 .ops = &clkops_null,
787 .parent = &dpll4_ck, 751 .parent = &dpll4_ck,
788 .init = &omap2_init_clksel_parent, 752 .init = &omap2_init_clksel_parent,
789 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 753 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
790 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, 754 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
791 .clksel = div16_dpll4_clksel, 755 .clksel = div16_dpll4_clksel,
792 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 756 .clkdm_name = "dpll4_clkdm",
793 PARENT_CONTROLS_CLOCK,
794 .recalc = &omap2_clksel_recalc, 757 .recalc = &omap2_clksel_recalc,
758 .set_rate = &omap2_clksel_set_rate,
759 .round_rate = &omap2_clksel_round_rate,
795}; 760};
796 761
797/* The PWRDN bit is apparently only available on 3430ES2 and above */ 762/* The PWRDN bit is apparently only available on 3430ES2 and above */
798static struct clk dpll4_m4x2_ck = { 763static struct clk dpll4_m4x2_ck = {
799 .name = "dpll4_m4x2_ck", 764 .name = "dpll4_m4x2_ck",
765 .ops = &clkops_omap2_dflt_wait,
800 .parent = &dpll4_m4_ck, 766 .parent = &dpll4_m4_ck,
801 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 767 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
802 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, 768 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
803 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 769 .flags = INVERT_ENABLE,
770 .clkdm_name = "dpll4_clkdm",
804 .recalc = &omap3_clkoutx2_recalc, 771 .recalc = &omap3_clkoutx2_recalc,
805}; 772};
806 773
807/* This virtual clock is the source for dpll4_m5x2_ck */ 774/* This virtual clock is the source for dpll4_m5x2_ck */
808static struct clk dpll4_m5_ck = { 775static struct clk dpll4_m5_ck = {
809 .name = "dpll4_m5_ck", 776 .name = "dpll4_m5_ck",
777 .ops = &clkops_null,
810 .parent = &dpll4_ck, 778 .parent = &dpll4_ck,
811 .init = &omap2_init_clksel_parent, 779 .init = &omap2_init_clksel_parent,
812 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), 780 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
813 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, 781 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
814 .clksel = div16_dpll4_clksel, 782 .clksel = div16_dpll4_clksel,
815 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 783 .clkdm_name = "dpll4_clkdm",
816 PARENT_CONTROLS_CLOCK,
817 .recalc = &omap2_clksel_recalc, 784 .recalc = &omap2_clksel_recalc,
818}; 785};
819 786
820/* The PWRDN bit is apparently only available on 3430ES2 and above */ 787/* The PWRDN bit is apparently only available on 3430ES2 and above */
821static struct clk dpll4_m5x2_ck = { 788static struct clk dpll4_m5x2_ck = {
822 .name = "dpll4_m5x2_ck", 789 .name = "dpll4_m5x2_ck",
790 .ops = &clkops_omap2_dflt_wait,
823 .parent = &dpll4_m5_ck, 791 .parent = &dpll4_m5_ck,
824 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 792 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
825 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, 793 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
826 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 794 .flags = INVERT_ENABLE,
795 .clkdm_name = "dpll4_clkdm",
827 .recalc = &omap3_clkoutx2_recalc, 796 .recalc = &omap3_clkoutx2_recalc,
828}; 797};
829 798
830/* This virtual clock is the source for dpll4_m6x2_ck */ 799/* This virtual clock is the source for dpll4_m6x2_ck */
831static struct clk dpll4_m6_ck = { 800static struct clk dpll4_m6_ck = {
832 .name = "dpll4_m6_ck", 801 .name = "dpll4_m6_ck",
802 .ops = &clkops_null,
833 .parent = &dpll4_ck, 803 .parent = &dpll4_ck,
834 .init = &omap2_init_clksel_parent, 804 .init = &omap2_init_clksel_parent,
835 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 805 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
836 .clksel_mask = OMAP3430_DIV_DPLL4_MASK, 806 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
837 .clksel = div16_dpll4_clksel, 807 .clksel = div16_dpll4_clksel,
838 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 808 .clkdm_name = "dpll4_clkdm",
839 PARENT_CONTROLS_CLOCK,
840 .recalc = &omap2_clksel_recalc, 809 .recalc = &omap2_clksel_recalc,
841}; 810};
842 811
843/* The PWRDN bit is apparently only available on 3430ES2 and above */ 812/* The PWRDN bit is apparently only available on 3430ES2 and above */
844static struct clk dpll4_m6x2_ck = { 813static struct clk dpll4_m6x2_ck = {
845 .name = "dpll4_m6x2_ck", 814 .name = "dpll4_m6x2_ck",
815 .ops = &clkops_omap2_dflt_wait,
846 .parent = &dpll4_m6_ck, 816 .parent = &dpll4_m6_ck,
847 .init = &omap2_init_clksel_parent, 817 .init = &omap2_init_clksel_parent,
848 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 818 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
849 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, 819 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
850 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 820 .flags = INVERT_ENABLE,
821 .clkdm_name = "dpll4_clkdm",
851 .recalc = &omap3_clkoutx2_recalc, 822 .recalc = &omap3_clkoutx2_recalc,
852}; 823};
853 824
854static struct clk emu_per_alwon_ck = { 825static struct clk emu_per_alwon_ck = {
855 .name = "emu_per_alwon_ck", 826 .name = "emu_per_alwon_ck",
827 .ops = &clkops_null,
856 .parent = &dpll4_m6x2_ck, 828 .parent = &dpll4_m6x2_ck,
857 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 829 .clkdm_name = "dpll4_clkdm",
858 PARENT_CONTROLS_CLOCK,
859 .recalc = &followparent_recalc, 830 .recalc = &followparent_recalc,
860}; 831};
861 832
@@ -867,6 +838,9 @@ static struct dpll_data dpll5_dd = {
867 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), 838 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
868 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, 839 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
869 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, 840 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
841 .clk_bypass = &sys_ck,
842 .clk_ref = &sys_ck,
843 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
870 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), 844 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
871 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, 845 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
872 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 846 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
@@ -876,20 +850,21 @@ static struct dpll_data dpll5_dd = {
876 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), 850 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
877 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, 851 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
878 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), 852 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
879 .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT, 853 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
880 .max_multiplier = OMAP3_MAX_DPLL_MULT, 854 .max_multiplier = OMAP3_MAX_DPLL_MULT,
855 .min_divider = 1,
881 .max_divider = OMAP3_MAX_DPLL_DIV, 856 .max_divider = OMAP3_MAX_DPLL_DIV,
882 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 857 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
883}; 858};
884 859
885static struct clk dpll5_ck = { 860static struct clk dpll5_ck = {
886 .name = "dpll5_ck", 861 .name = "dpll5_ck",
862 .ops = &clkops_noncore_dpll_ops,
887 .parent = &sys_ck, 863 .parent = &sys_ck,
888 .dpll_data = &dpll5_dd, 864 .dpll_data = &dpll5_dd,
889 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
890 .enable = &omap3_noncore_dpll_enable,
891 .disable = &omap3_noncore_dpll_disable,
892 .round_rate = &omap2_dpll_round_rate, 865 .round_rate = &omap2_dpll_round_rate,
866 .set_rate = &omap3_noncore_dpll_set_rate,
867 .clkdm_name = "dpll5_clkdm",
893 .recalc = &omap3_dpll_recalc, 868 .recalc = &omap3_dpll_recalc,
894}; 869};
895 870
@@ -900,31 +875,13 @@ static const struct clksel div16_dpll5_clksel[] = {
900 875
901static struct clk dpll5_m2_ck = { 876static struct clk dpll5_m2_ck = {
902 .name = "dpll5_m2_ck", 877 .name = "dpll5_m2_ck",
878 .ops = &clkops_null,
903 .parent = &dpll5_ck, 879 .parent = &dpll5_ck,
904 .init = &omap2_init_clksel_parent, 880 .init = &omap2_init_clksel_parent,
905 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), 881 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
906 .clksel_mask = OMAP3430ES2_DIV_120M_MASK, 882 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
907 .clksel = div16_dpll5_clksel, 883 .clksel = div16_dpll5_clksel,
908 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | 884 .clkdm_name = "dpll5_clkdm",
909 PARENT_CONTROLS_CLOCK,
910 .recalc = &omap2_clksel_recalc,
911};
912
913static const struct clksel omap_120m_fck_clksel[] = {
914 { .parent = &sys_ck, .rates = dpll_bypass_rates },
915 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
916 { .parent = NULL }
917};
918
919static struct clk omap_120m_fck = {
920 .name = "omap_120m_fck",
921 .parent = &dpll5_m2_ck,
922 .init = &omap2_init_clksel_parent,
923 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
924 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
925 .clksel = omap_120m_fck_clksel,
926 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
927 PARENT_CONTROLS_CLOCK,
928 .recalc = &omap2_clksel_recalc, 885 .recalc = &omap2_clksel_recalc,
929}; 886};
930 887
@@ -951,22 +908,23 @@ static const struct clksel_rate clkout2_src_54m_rates[] = {
951}; 908};
952 909
953static const struct clksel clkout2_src_clksel[] = { 910static const struct clksel clkout2_src_clksel[] = {
954 { .parent = &core_ck, .rates = clkout2_src_core_rates }, 911 { .parent = &core_ck, .rates = clkout2_src_core_rates },
955 { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, 912 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
956 { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates }, 913 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
957 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, 914 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
958 { .parent = NULL } 915 { .parent = NULL }
959}; 916};
960 917
961static struct clk clkout2_src_ck = { 918static struct clk clkout2_src_ck = {
962 .name = "clkout2_src_ck", 919 .name = "clkout2_src_ck",
920 .ops = &clkops_omap2_dflt,
963 .init = &omap2_init_clksel_parent, 921 .init = &omap2_init_clksel_parent,
964 .enable_reg = OMAP3430_CM_CLKOUT_CTRL, 922 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
965 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, 923 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
966 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, 924 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
967 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, 925 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
968 .clksel = clkout2_src_clksel, 926 .clksel = clkout2_src_clksel,
969 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 927 .clkdm_name = "core_clkdm",
970 .recalc = &omap2_clksel_recalc, 928 .recalc = &omap2_clksel_recalc,
971}; 929};
972 930
@@ -986,11 +944,11 @@ static const struct clksel sys_clkout2_clksel[] = {
986 944
987static struct clk sys_clkout2 = { 945static struct clk sys_clkout2 = {
988 .name = "sys_clkout2", 946 .name = "sys_clkout2",
947 .ops = &clkops_null,
989 .init = &omap2_init_clksel_parent, 948 .init = &omap2_init_clksel_parent,
990 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, 949 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
991 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, 950 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
992 .clksel = sys_clkout2_clksel, 951 .clksel = sys_clkout2_clksel,
993 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
994 .recalc = &omap2_clksel_recalc, 952 .recalc = &omap2_clksel_recalc,
995}; 953};
996 954
@@ -998,16 +956,22 @@ static struct clk sys_clkout2 = {
998 956
999static struct clk corex2_fck = { 957static struct clk corex2_fck = {
1000 .name = "corex2_fck", 958 .name = "corex2_fck",
959 .ops = &clkops_null,
1001 .parent = &dpll3_m2x2_ck, 960 .parent = &dpll3_m2x2_ck,
1002 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1003 PARENT_CONTROLS_CLOCK,
1004 .recalc = &followparent_recalc, 961 .recalc = &followparent_recalc,
1005}; 962};
1006 963
1007/* DPLL power domain clock controls */ 964/* DPLL power domain clock controls */
1008 965
1009static const struct clksel div2_core_clksel[] = { 966static const struct clksel_rate div4_rates[] = {
1010 { .parent = &core_ck, .rates = div2_rates }, 967 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
968 { .div = 2, .val = 2, .flags = RATE_IN_343X },
969 { .div = 4, .val = 4, .flags = RATE_IN_343X },
970 { .div = 0 }
971};
972
973static const struct clksel div4_core_clksel[] = {
974 { .parent = &core_ck, .rates = div4_rates },
1011 { .parent = NULL } 975 { .parent = NULL }
1012}; 976};
1013 977
@@ -1017,39 +981,21 @@ static const struct clksel div2_core_clksel[] = {
1017 */ 981 */
1018static struct clk dpll1_fck = { 982static struct clk dpll1_fck = {
1019 .name = "dpll1_fck", 983 .name = "dpll1_fck",
984 .ops = &clkops_null,
1020 .parent = &core_ck, 985 .parent = &core_ck,
1021 .init = &omap2_init_clksel_parent, 986 .init = &omap2_init_clksel_parent,
1022 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), 987 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1023 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, 988 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1024 .clksel = div2_core_clksel, 989 .clksel = div4_core_clksel,
1025 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1026 PARENT_CONTROLS_CLOCK,
1027 .recalc = &omap2_clksel_recalc, 990 .recalc = &omap2_clksel_recalc,
1028}; 991};
1029 992
1030/*
1031 * MPU clksel:
1032 * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1033 * derives from the high-frequency bypass clock originating from DPLL3,
1034 * called 'dpll1_fck'
1035 */
1036static const struct clksel mpu_clksel[] = {
1037 { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
1038 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1039 { .parent = NULL }
1040};
1041
1042static struct clk mpu_ck = { 993static struct clk mpu_ck = {
1043 .name = "mpu_ck", 994 .name = "mpu_ck",
995 .ops = &clkops_null,
1044 .parent = &dpll1_x2m2_ck, 996 .parent = &dpll1_x2m2_ck,
1045 .init = &omap2_init_clksel_parent,
1046 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1047 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1048 .clksel = mpu_clksel,
1049 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1050 PARENT_CONTROLS_CLOCK,
1051 .clkdm_name = "mpu_clkdm", 997 .clkdm_name = "mpu_clkdm",
1052 .recalc = &omap2_clksel_recalc, 998 .recalc = &followparent_recalc,
1053}; 999};
1054 1000
1055/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ 1001/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
@@ -1066,13 +1012,12 @@ static const struct clksel arm_fck_clksel[] = {
1066 1012
1067static struct clk arm_fck = { 1013static struct clk arm_fck = {
1068 .name = "arm_fck", 1014 .name = "arm_fck",
1015 .ops = &clkops_null,
1069 .parent = &mpu_ck, 1016 .parent = &mpu_ck,
1070 .init = &omap2_init_clksel_parent, 1017 .init = &omap2_init_clksel_parent,
1071 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), 1018 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1072 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, 1019 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1073 .clksel = arm_fck_clksel, 1020 .clksel = arm_fck_clksel,
1074 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1075 PARENT_CONTROLS_CLOCK,
1076 .recalc = &omap2_clksel_recalc, 1021 .recalc = &omap2_clksel_recalc,
1077}; 1022};
1078 1023
@@ -1084,63 +1029,48 @@ static struct clk arm_fck = {
1084 */ 1029 */
1085static struct clk emu_mpu_alwon_ck = { 1030static struct clk emu_mpu_alwon_ck = {
1086 .name = "emu_mpu_alwon_ck", 1031 .name = "emu_mpu_alwon_ck",
1032 .ops = &clkops_null,
1087 .parent = &mpu_ck, 1033 .parent = &mpu_ck,
1088 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1089 PARENT_CONTROLS_CLOCK,
1090 .recalc = &followparent_recalc, 1034 .recalc = &followparent_recalc,
1091}; 1035};
1092 1036
1093static struct clk dpll2_fck = { 1037static struct clk dpll2_fck = {
1094 .name = "dpll2_fck", 1038 .name = "dpll2_fck",
1039 .ops = &clkops_null,
1095 .parent = &core_ck, 1040 .parent = &core_ck,
1096 .init = &omap2_init_clksel_parent, 1041 .init = &omap2_init_clksel_parent,
1097 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), 1042 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1098 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, 1043 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1099 .clksel = div2_core_clksel, 1044 .clksel = div4_core_clksel,
1100 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1101 PARENT_CONTROLS_CLOCK,
1102 .recalc = &omap2_clksel_recalc, 1045 .recalc = &omap2_clksel_recalc,
1103}; 1046};
1104 1047
1105/*
1106 * IVA2 clksel:
1107 * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1108 * derives from the high-frequency bypass clock originating from DPLL3,
1109 * called 'dpll2_fck'
1110 */
1111
1112static const struct clksel iva2_clksel[] = {
1113 { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
1114 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1115 { .parent = NULL }
1116};
1117
1118static struct clk iva2_ck = { 1048static struct clk iva2_ck = {
1119 .name = "iva2_ck", 1049 .name = "iva2_ck",
1050 .ops = &clkops_omap2_dflt_wait,
1120 .parent = &dpll2_m2_ck, 1051 .parent = &dpll2_m2_ck,
1121 .init = &omap2_init_clksel_parent, 1052 .init = &omap2_init_clksel_parent,
1122 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), 1053 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1123 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 1054 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1124 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1125 OMAP3430_CM_IDLEST_PLL),
1126 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1127 .clksel = iva2_clksel,
1128 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1129 .clkdm_name = "iva2_clkdm", 1055 .clkdm_name = "iva2_clkdm",
1130 .recalc = &omap2_clksel_recalc, 1056 .recalc = &followparent_recalc,
1131}; 1057};
1132 1058
1133/* Common interface clocks */ 1059/* Common interface clocks */
1134 1060
1061static const struct clksel div2_core_clksel[] = {
1062 { .parent = &core_ck, .rates = div2_rates },
1063 { .parent = NULL }
1064};
1065
1135static struct clk l3_ick = { 1066static struct clk l3_ick = {
1136 .name = "l3_ick", 1067 .name = "l3_ick",
1068 .ops = &clkops_null,
1137 .parent = &core_ck, 1069 .parent = &core_ck,
1138 .init = &omap2_init_clksel_parent, 1070 .init = &omap2_init_clksel_parent,
1139 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1071 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1140 .clksel_mask = OMAP3430_CLKSEL_L3_MASK, 1072 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1141 .clksel = div2_core_clksel, 1073 .clksel = div2_core_clksel,
1142 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1143 PARENT_CONTROLS_CLOCK,
1144 .clkdm_name = "core_l3_clkdm", 1074 .clkdm_name = "core_l3_clkdm",
1145 .recalc = &omap2_clksel_recalc, 1075 .recalc = &omap2_clksel_recalc,
1146}; 1076};
@@ -1152,13 +1082,12 @@ static const struct clksel div2_l3_clksel[] = {
1152 1082
1153static struct clk l4_ick = { 1083static struct clk l4_ick = {
1154 .name = "l4_ick", 1084 .name = "l4_ick",
1085 .ops = &clkops_null,
1155 .parent = &l3_ick, 1086 .parent = &l3_ick,
1156 .init = &omap2_init_clksel_parent, 1087 .init = &omap2_init_clksel_parent,
1157 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1088 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1158 .clksel_mask = OMAP3430_CLKSEL_L4_MASK, 1089 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1159 .clksel = div2_l3_clksel, 1090 .clksel = div2_l3_clksel,
1160 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1161 PARENT_CONTROLS_CLOCK,
1162 .clkdm_name = "core_l4_clkdm", 1091 .clkdm_name = "core_l4_clkdm",
1163 .recalc = &omap2_clksel_recalc, 1092 .recalc = &omap2_clksel_recalc,
1164 1093
@@ -1171,12 +1100,12 @@ static const struct clksel div2_l4_clksel[] = {
1171 1100
1172static struct clk rm_ick = { 1101static struct clk rm_ick = {
1173 .name = "rm_ick", 1102 .name = "rm_ick",
1103 .ops = &clkops_null,
1174 .parent = &l4_ick, 1104 .parent = &l4_ick,
1175 .init = &omap2_init_clksel_parent, 1105 .init = &omap2_init_clksel_parent,
1176 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), 1106 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1177 .clksel_mask = OMAP3430_CLKSEL_RM_MASK, 1107 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1178 .clksel = div2_l4_clksel, 1108 .clksel = div2_l4_clksel,
1179 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1180 .recalc = &omap2_clksel_recalc, 1109 .recalc = &omap2_clksel_recalc,
1181}; 1110};
1182 1111
@@ -1192,53 +1121,52 @@ static const struct clksel gfx_l3_clksel[] = {
1192/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ 1121/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1193static struct clk gfx_l3_ck = { 1122static struct clk gfx_l3_ck = {
1194 .name = "gfx_l3_ck", 1123 .name = "gfx_l3_ck",
1124 .ops = &clkops_omap2_dflt_wait,
1195 .parent = &l3_ick, 1125 .parent = &l3_ick,
1196 .init = &omap2_init_clksel_parent, 1126 .init = &omap2_init_clksel_parent,
1197 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1127 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1198 .enable_bit = OMAP_EN_GFX_SHIFT, 1128 .enable_bit = OMAP_EN_GFX_SHIFT,
1199 .flags = CLOCK_IN_OMAP3430ES1,
1200 .recalc = &followparent_recalc, 1129 .recalc = &followparent_recalc,
1201}; 1130};
1202 1131
1203static struct clk gfx_l3_fck = { 1132static struct clk gfx_l3_fck = {
1204 .name = "gfx_l3_fck", 1133 .name = "gfx_l3_fck",
1134 .ops = &clkops_null,
1205 .parent = &gfx_l3_ck, 1135 .parent = &gfx_l3_ck,
1206 .init = &omap2_init_clksel_parent, 1136 .init = &omap2_init_clksel_parent,
1207 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1137 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1208 .clksel_mask = OMAP_CLKSEL_GFX_MASK, 1138 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1209 .clksel = gfx_l3_clksel, 1139 .clksel = gfx_l3_clksel,
1210 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1211 PARENT_CONTROLS_CLOCK,
1212 .clkdm_name = "gfx_3430es1_clkdm", 1140 .clkdm_name = "gfx_3430es1_clkdm",
1213 .recalc = &omap2_clksel_recalc, 1141 .recalc = &omap2_clksel_recalc,
1214}; 1142};
1215 1143
1216static struct clk gfx_l3_ick = { 1144static struct clk gfx_l3_ick = {
1217 .name = "gfx_l3_ick", 1145 .name = "gfx_l3_ick",
1146 .ops = &clkops_null,
1218 .parent = &gfx_l3_ck, 1147 .parent = &gfx_l3_ck,
1219 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1220 .clkdm_name = "gfx_3430es1_clkdm", 1148 .clkdm_name = "gfx_3430es1_clkdm",
1221 .recalc = &followparent_recalc, 1149 .recalc = &followparent_recalc,
1222}; 1150};
1223 1151
1224static struct clk gfx_cg1_ck = { 1152static struct clk gfx_cg1_ck = {
1225 .name = "gfx_cg1_ck", 1153 .name = "gfx_cg1_ck",
1154 .ops = &clkops_omap2_dflt_wait,
1226 .parent = &gfx_l3_fck, /* REVISIT: correct? */ 1155 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1227 .init = &omap2_init_clk_clkdm, 1156 .init = &omap2_init_clk_clkdm,
1228 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1157 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1229 .enable_bit = OMAP3430ES1_EN_2D_SHIFT, 1158 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1230 .flags = CLOCK_IN_OMAP3430ES1,
1231 .clkdm_name = "gfx_3430es1_clkdm", 1159 .clkdm_name = "gfx_3430es1_clkdm",
1232 .recalc = &followparent_recalc, 1160 .recalc = &followparent_recalc,
1233}; 1161};
1234 1162
1235static struct clk gfx_cg2_ck = { 1163static struct clk gfx_cg2_ck = {
1236 .name = "gfx_cg2_ck", 1164 .name = "gfx_cg2_ck",
1165 .ops = &clkops_omap2_dflt_wait,
1237 .parent = &gfx_l3_fck, /* REVISIT: correct? */ 1166 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1238 .init = &omap2_init_clk_clkdm, 1167 .init = &omap2_init_clk_clkdm,
1239 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1168 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1240 .enable_bit = OMAP3430ES1_EN_3D_SHIFT, 1169 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1241 .flags = CLOCK_IN_OMAP3430ES1,
1242 .clkdm_name = "gfx_3430es1_clkdm", 1170 .clkdm_name = "gfx_3430es1_clkdm",
1243 .recalc = &followparent_recalc, 1171 .recalc = &followparent_recalc,
1244}; 1172};
@@ -1265,24 +1193,24 @@ static const struct clksel sgx_clksel[] = {
1265 1193
1266static struct clk sgx_fck = { 1194static struct clk sgx_fck = {
1267 .name = "sgx_fck", 1195 .name = "sgx_fck",
1196 .ops = &clkops_omap2_dflt_wait,
1268 .init = &omap2_init_clksel_parent, 1197 .init = &omap2_init_clksel_parent,
1269 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), 1198 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1270 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, 1199 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1271 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), 1200 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1272 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, 1201 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1273 .clksel = sgx_clksel, 1202 .clksel = sgx_clksel,
1274 .flags = CLOCK_IN_OMAP3430ES2,
1275 .clkdm_name = "sgx_clkdm", 1203 .clkdm_name = "sgx_clkdm",
1276 .recalc = &omap2_clksel_recalc, 1204 .recalc = &omap2_clksel_recalc,
1277}; 1205};
1278 1206
1279static struct clk sgx_ick = { 1207static struct clk sgx_ick = {
1280 .name = "sgx_ick", 1208 .name = "sgx_ick",
1209 .ops = &clkops_omap2_dflt_wait,
1281 .parent = &l3_ick, 1210 .parent = &l3_ick,
1282 .init = &omap2_init_clk_clkdm, 1211 .init = &omap2_init_clk_clkdm,
1283 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), 1212 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1284 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, 1213 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1285 .flags = CLOCK_IN_OMAP3430ES2,
1286 .clkdm_name = "sgx_clkdm", 1214 .clkdm_name = "sgx_clkdm",
1287 .recalc = &followparent_recalc, 1215 .recalc = &followparent_recalc,
1288}; 1216};
@@ -1291,11 +1219,11 @@ static struct clk sgx_ick = {
1291 1219
1292static struct clk d2d_26m_fck = { 1220static struct clk d2d_26m_fck = {
1293 .name = "d2d_26m_fck", 1221 .name = "d2d_26m_fck",
1222 .ops = &clkops_omap2_dflt_wait,
1294 .parent = &sys_ck, 1223 .parent = &sys_ck,
1295 .init = &omap2_init_clk_clkdm, 1224 .init = &omap2_init_clk_clkdm,
1296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1225 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1297 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, 1226 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1298 .flags = CLOCK_IN_OMAP3430ES1,
1299 .clkdm_name = "d2d_clkdm", 1227 .clkdm_name = "d2d_clkdm",
1300 .recalc = &followparent_recalc, 1228 .recalc = &followparent_recalc,
1301}; 1229};
@@ -1308,6 +1236,7 @@ static const struct clksel omap343x_gpt_clksel[] = {
1308 1236
1309static struct clk gpt10_fck = { 1237static struct clk gpt10_fck = {
1310 .name = "gpt10_fck", 1238 .name = "gpt10_fck",
1239 .ops = &clkops_omap2_dflt_wait,
1311 .parent = &sys_ck, 1240 .parent = &sys_ck,
1312 .init = &omap2_init_clksel_parent, 1241 .init = &omap2_init_clksel_parent,
1313 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1242 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1315,13 +1244,13 @@ static struct clk gpt10_fck = {
1315 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1244 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1316 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, 1245 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1317 .clksel = omap343x_gpt_clksel, 1246 .clksel = omap343x_gpt_clksel,
1318 .flags = CLOCK_IN_OMAP343X,
1319 .clkdm_name = "core_l4_clkdm", 1247 .clkdm_name = "core_l4_clkdm",
1320 .recalc = &omap2_clksel_recalc, 1248 .recalc = &omap2_clksel_recalc,
1321}; 1249};
1322 1250
1323static struct clk gpt11_fck = { 1251static struct clk gpt11_fck = {
1324 .name = "gpt11_fck", 1252 .name = "gpt11_fck",
1253 .ops = &clkops_omap2_dflt_wait,
1325 .parent = &sys_ck, 1254 .parent = &sys_ck,
1326 .init = &omap2_init_clksel_parent, 1255 .init = &omap2_init_clksel_parent,
1327 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1329,35 +1258,34 @@ static struct clk gpt11_fck = {
1329 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1258 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1330 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, 1259 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1331 .clksel = omap343x_gpt_clksel, 1260 .clksel = omap343x_gpt_clksel,
1332 .flags = CLOCK_IN_OMAP343X,
1333 .clkdm_name = "core_l4_clkdm", 1261 .clkdm_name = "core_l4_clkdm",
1334 .recalc = &omap2_clksel_recalc, 1262 .recalc = &omap2_clksel_recalc,
1335}; 1263};
1336 1264
1337static struct clk cpefuse_fck = { 1265static struct clk cpefuse_fck = {
1338 .name = "cpefuse_fck", 1266 .name = "cpefuse_fck",
1267 .ops = &clkops_omap2_dflt,
1339 .parent = &sys_ck, 1268 .parent = &sys_ck,
1340 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1269 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1341 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, 1270 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1342 .flags = CLOCK_IN_OMAP3430ES2,
1343 .recalc = &followparent_recalc, 1271 .recalc = &followparent_recalc,
1344}; 1272};
1345 1273
1346static struct clk ts_fck = { 1274static struct clk ts_fck = {
1347 .name = "ts_fck", 1275 .name = "ts_fck",
1276 .ops = &clkops_omap2_dflt,
1348 .parent = &omap_32k_fck, 1277 .parent = &omap_32k_fck,
1349 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1278 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1350 .enable_bit = OMAP3430ES2_EN_TS_SHIFT, 1279 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1351 .flags = CLOCK_IN_OMAP3430ES2,
1352 .recalc = &followparent_recalc, 1280 .recalc = &followparent_recalc,
1353}; 1281};
1354 1282
1355static struct clk usbtll_fck = { 1283static struct clk usbtll_fck = {
1356 .name = "usbtll_fck", 1284 .name = "usbtll_fck",
1357 .parent = &omap_120m_fck, 1285 .ops = &clkops_omap2_dflt,
1286 .parent = &dpll5_m2_ck,
1358 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1287 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1359 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1288 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1360 .flags = CLOCK_IN_OMAP3430ES2,
1361 .recalc = &followparent_recalc, 1289 .recalc = &followparent_recalc,
1362}; 1290};
1363 1291
@@ -1365,84 +1293,83 @@ static struct clk usbtll_fck = {
1365 1293
1366static struct clk core_96m_fck = { 1294static struct clk core_96m_fck = {
1367 .name = "core_96m_fck", 1295 .name = "core_96m_fck",
1296 .ops = &clkops_null,
1368 .parent = &omap_96m_fck, 1297 .parent = &omap_96m_fck,
1369 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1370 PARENT_CONTROLS_CLOCK,
1371 .clkdm_name = "core_l4_clkdm", 1298 .clkdm_name = "core_l4_clkdm",
1372 .recalc = &followparent_recalc, 1299 .recalc = &followparent_recalc,
1373}; 1300};
1374 1301
1375static struct clk mmchs3_fck = { 1302static struct clk mmchs3_fck = {
1376 .name = "mmchs_fck", 1303 .name = "mmchs_fck",
1304 .ops = &clkops_omap2_dflt_wait,
1377 .id = 2, 1305 .id = 2,
1378 .parent = &core_96m_fck, 1306 .parent = &core_96m_fck,
1379 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1380 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1308 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1381 .flags = CLOCK_IN_OMAP3430ES2,
1382 .clkdm_name = "core_l4_clkdm", 1309 .clkdm_name = "core_l4_clkdm",
1383 .recalc = &followparent_recalc, 1310 .recalc = &followparent_recalc,
1384}; 1311};
1385 1312
1386static struct clk mmchs2_fck = { 1313static struct clk mmchs2_fck = {
1387 .name = "mmchs_fck", 1314 .name = "mmchs_fck",
1315 .ops = &clkops_omap2_dflt_wait,
1388 .id = 1, 1316 .id = 1,
1389 .parent = &core_96m_fck, 1317 .parent = &core_96m_fck,
1390 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1391 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1319 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1392 .flags = CLOCK_IN_OMAP343X,
1393 .clkdm_name = "core_l4_clkdm", 1320 .clkdm_name = "core_l4_clkdm",
1394 .recalc = &followparent_recalc, 1321 .recalc = &followparent_recalc,
1395}; 1322};
1396 1323
1397static struct clk mspro_fck = { 1324static struct clk mspro_fck = {
1398 .name = "mspro_fck", 1325 .name = "mspro_fck",
1326 .ops = &clkops_omap2_dflt_wait,
1399 .parent = &core_96m_fck, 1327 .parent = &core_96m_fck,
1400 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1328 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1401 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1329 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1402 .flags = CLOCK_IN_OMAP343X,
1403 .clkdm_name = "core_l4_clkdm", 1330 .clkdm_name = "core_l4_clkdm",
1404 .recalc = &followparent_recalc, 1331 .recalc = &followparent_recalc,
1405}; 1332};
1406 1333
1407static struct clk mmchs1_fck = { 1334static struct clk mmchs1_fck = {
1408 .name = "mmchs_fck", 1335 .name = "mmchs_fck",
1336 .ops = &clkops_omap2_dflt_wait,
1409 .parent = &core_96m_fck, 1337 .parent = &core_96m_fck,
1410 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1338 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1411 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1339 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1412 .flags = CLOCK_IN_OMAP343X,
1413 .clkdm_name = "core_l4_clkdm", 1340 .clkdm_name = "core_l4_clkdm",
1414 .recalc = &followparent_recalc, 1341 .recalc = &followparent_recalc,
1415}; 1342};
1416 1343
1417static struct clk i2c3_fck = { 1344static struct clk i2c3_fck = {
1418 .name = "i2c_fck", 1345 .name = "i2c_fck",
1346 .ops = &clkops_omap2_dflt_wait,
1419 .id = 3, 1347 .id = 3,
1420 .parent = &core_96m_fck, 1348 .parent = &core_96m_fck,
1421 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1349 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1422 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1350 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1423 .flags = CLOCK_IN_OMAP343X,
1424 .clkdm_name = "core_l4_clkdm", 1351 .clkdm_name = "core_l4_clkdm",
1425 .recalc = &followparent_recalc, 1352 .recalc = &followparent_recalc,
1426}; 1353};
1427 1354
1428static struct clk i2c2_fck = { 1355static struct clk i2c2_fck = {
1429 .name = "i2c_fck", 1356 .name = "i2c_fck",
1357 .ops = &clkops_omap2_dflt_wait,
1430 .id = 2, 1358 .id = 2,
1431 .parent = &core_96m_fck, 1359 .parent = &core_96m_fck,
1432 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1360 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1433 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1361 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1434 .flags = CLOCK_IN_OMAP343X,
1435 .clkdm_name = "core_l4_clkdm", 1362 .clkdm_name = "core_l4_clkdm",
1436 .recalc = &followparent_recalc, 1363 .recalc = &followparent_recalc,
1437}; 1364};
1438 1365
1439static struct clk i2c1_fck = { 1366static struct clk i2c1_fck = {
1440 .name = "i2c_fck", 1367 .name = "i2c_fck",
1368 .ops = &clkops_omap2_dflt_wait,
1441 .id = 1, 1369 .id = 1,
1442 .parent = &core_96m_fck, 1370 .parent = &core_96m_fck,
1443 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1444 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1372 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1445 .flags = CLOCK_IN_OMAP343X,
1446 .clkdm_name = "core_l4_clkdm", 1373 .clkdm_name = "core_l4_clkdm",
1447 .recalc = &followparent_recalc, 1374 .recalc = &followparent_recalc,
1448}; 1375};
@@ -1469,6 +1396,7 @@ static const struct clksel mcbsp_15_clksel[] = {
1469 1396
1470static struct clk mcbsp5_fck = { 1397static struct clk mcbsp5_fck = {
1471 .name = "mcbsp_fck", 1398 .name = "mcbsp_fck",
1399 .ops = &clkops_omap2_dflt_wait,
1472 .id = 5, 1400 .id = 5,
1473 .init = &omap2_init_clksel_parent, 1401 .init = &omap2_init_clksel_parent,
1474 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1402 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1476,13 +1404,13 @@ static struct clk mcbsp5_fck = {
1476 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), 1404 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1477 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, 1405 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1478 .clksel = mcbsp_15_clksel, 1406 .clksel = mcbsp_15_clksel,
1479 .flags = CLOCK_IN_OMAP343X,
1480 .clkdm_name = "core_l4_clkdm", 1407 .clkdm_name = "core_l4_clkdm",
1481 .recalc = &omap2_clksel_recalc, 1408 .recalc = &omap2_clksel_recalc,
1482}; 1409};
1483 1410
1484static struct clk mcbsp1_fck = { 1411static struct clk mcbsp1_fck = {
1485 .name = "mcbsp_fck", 1412 .name = "mcbsp_fck",
1413 .ops = &clkops_omap2_dflt_wait,
1486 .id = 1, 1414 .id = 1,
1487 .init = &omap2_init_clksel_parent, 1415 .init = &omap2_init_clksel_parent,
1488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1416 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1490,7 +1418,6 @@ static struct clk mcbsp1_fck = {
1490 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), 1418 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1491 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, 1419 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1492 .clksel = mcbsp_15_clksel, 1420 .clksel = mcbsp_15_clksel,
1493 .flags = CLOCK_IN_OMAP343X,
1494 .clkdm_name = "core_l4_clkdm", 1421 .clkdm_name = "core_l4_clkdm",
1495 .recalc = &omap2_clksel_recalc, 1422 .recalc = &omap2_clksel_recalc,
1496}; 1423};
@@ -1499,77 +1426,76 @@ static struct clk mcbsp1_fck = {
1499 1426
1500static struct clk core_48m_fck = { 1427static struct clk core_48m_fck = {
1501 .name = "core_48m_fck", 1428 .name = "core_48m_fck",
1429 .ops = &clkops_null,
1502 .parent = &omap_48m_fck, 1430 .parent = &omap_48m_fck,
1503 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1504 PARENT_CONTROLS_CLOCK,
1505 .clkdm_name = "core_l4_clkdm", 1431 .clkdm_name = "core_l4_clkdm",
1506 .recalc = &followparent_recalc, 1432 .recalc = &followparent_recalc,
1507}; 1433};
1508 1434
1509static struct clk mcspi4_fck = { 1435static struct clk mcspi4_fck = {
1510 .name = "mcspi_fck", 1436 .name = "mcspi_fck",
1437 .ops = &clkops_omap2_dflt_wait,
1511 .id = 4, 1438 .id = 4,
1512 .parent = &core_48m_fck, 1439 .parent = &core_48m_fck,
1513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1440 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1514 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1441 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1515 .flags = CLOCK_IN_OMAP343X,
1516 .recalc = &followparent_recalc, 1442 .recalc = &followparent_recalc,
1517}; 1443};
1518 1444
1519static struct clk mcspi3_fck = { 1445static struct clk mcspi3_fck = {
1520 .name = "mcspi_fck", 1446 .name = "mcspi_fck",
1447 .ops = &clkops_omap2_dflt_wait,
1521 .id = 3, 1448 .id = 3,
1522 .parent = &core_48m_fck, 1449 .parent = &core_48m_fck,
1523 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1450 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1451 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1525 .flags = CLOCK_IN_OMAP343X,
1526 .recalc = &followparent_recalc, 1452 .recalc = &followparent_recalc,
1527}; 1453};
1528 1454
1529static struct clk mcspi2_fck = { 1455static struct clk mcspi2_fck = {
1530 .name = "mcspi_fck", 1456 .name = "mcspi_fck",
1457 .ops = &clkops_omap2_dflt_wait,
1531 .id = 2, 1458 .id = 2,
1532 .parent = &core_48m_fck, 1459 .parent = &core_48m_fck,
1533 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1460 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1534 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1461 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1535 .flags = CLOCK_IN_OMAP343X,
1536 .recalc = &followparent_recalc, 1462 .recalc = &followparent_recalc,
1537}; 1463};
1538 1464
1539static struct clk mcspi1_fck = { 1465static struct clk mcspi1_fck = {
1540 .name = "mcspi_fck", 1466 .name = "mcspi_fck",
1467 .ops = &clkops_omap2_dflt_wait,
1541 .id = 1, 1468 .id = 1,
1542 .parent = &core_48m_fck, 1469 .parent = &core_48m_fck,
1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1470 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1544 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1471 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1545 .flags = CLOCK_IN_OMAP343X,
1546 .recalc = &followparent_recalc, 1472 .recalc = &followparent_recalc,
1547}; 1473};
1548 1474
1549static struct clk uart2_fck = { 1475static struct clk uart2_fck = {
1550 .name = "uart2_fck", 1476 .name = "uart2_fck",
1477 .ops = &clkops_omap2_dflt_wait,
1551 .parent = &core_48m_fck, 1478 .parent = &core_48m_fck,
1552 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1479 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1553 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1480 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1554 .flags = CLOCK_IN_OMAP343X,
1555 .recalc = &followparent_recalc, 1481 .recalc = &followparent_recalc,
1556}; 1482};
1557 1483
1558static struct clk uart1_fck = { 1484static struct clk uart1_fck = {
1559 .name = "uart1_fck", 1485 .name = "uart1_fck",
1486 .ops = &clkops_omap2_dflt_wait,
1560 .parent = &core_48m_fck, 1487 .parent = &core_48m_fck,
1561 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1562 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1489 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1563 .flags = CLOCK_IN_OMAP343X,
1564 .recalc = &followparent_recalc, 1490 .recalc = &followparent_recalc,
1565}; 1491};
1566 1492
1567static struct clk fshostusb_fck = { 1493static struct clk fshostusb_fck = {
1568 .name = "fshostusb_fck", 1494 .name = "fshostusb_fck",
1495 .ops = &clkops_omap2_dflt_wait,
1569 .parent = &core_48m_fck, 1496 .parent = &core_48m_fck,
1570 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1497 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1571 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, 1498 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1572 .flags = CLOCK_IN_OMAP3430ES1,
1573 .recalc = &followparent_recalc, 1499 .recalc = &followparent_recalc,
1574}; 1500};
1575 1501
@@ -1577,19 +1503,18 @@ static struct clk fshostusb_fck = {
1577 1503
1578static struct clk core_12m_fck = { 1504static struct clk core_12m_fck = {
1579 .name = "core_12m_fck", 1505 .name = "core_12m_fck",
1506 .ops = &clkops_null,
1580 .parent = &omap_12m_fck, 1507 .parent = &omap_12m_fck,
1581 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1582 PARENT_CONTROLS_CLOCK,
1583 .clkdm_name = "core_l4_clkdm", 1508 .clkdm_name = "core_l4_clkdm",
1584 .recalc = &followparent_recalc, 1509 .recalc = &followparent_recalc,
1585}; 1510};
1586 1511
1587static struct clk hdq_fck = { 1512static struct clk hdq_fck = {
1588 .name = "hdq_fck", 1513 .name = "hdq_fck",
1514 .ops = &clkops_omap2_dflt_wait,
1589 .parent = &core_12m_fck, 1515 .parent = &core_12m_fck,
1590 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1516 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1591 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1517 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1592 .flags = CLOCK_IN_OMAP343X,
1593 .recalc = &followparent_recalc, 1518 .recalc = &followparent_recalc,
1594}; 1519};
1595 1520
@@ -1612,22 +1537,22 @@ static const struct clksel ssi_ssr_clksel[] = {
1612 1537
1613static struct clk ssi_ssr_fck = { 1538static struct clk ssi_ssr_fck = {
1614 .name = "ssi_ssr_fck", 1539 .name = "ssi_ssr_fck",
1540 .ops = &clkops_omap2_dflt,
1615 .init = &omap2_init_clksel_parent, 1541 .init = &omap2_init_clksel_parent,
1616 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1542 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1617 .enable_bit = OMAP3430_EN_SSI_SHIFT, 1543 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1618 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1544 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1619 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, 1545 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1620 .clksel = ssi_ssr_clksel, 1546 .clksel = ssi_ssr_clksel,
1621 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1622 .clkdm_name = "core_l4_clkdm", 1547 .clkdm_name = "core_l4_clkdm",
1623 .recalc = &omap2_clksel_recalc, 1548 .recalc = &omap2_clksel_recalc,
1624}; 1549};
1625 1550
1626static struct clk ssi_sst_fck = { 1551static struct clk ssi_sst_fck = {
1627 .name = "ssi_sst_fck", 1552 .name = "ssi_sst_fck",
1553 .ops = &clkops_null,
1628 .parent = &ssi_ssr_fck, 1554 .parent = &ssi_ssr_fck,
1629 .fixed_div = 2, 1555 .fixed_div = 2,
1630 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1631 .recalc = &omap2_fixed_divisor_recalc, 1556 .recalc = &omap2_fixed_divisor_recalc,
1632}; 1557};
1633 1558
@@ -1641,39 +1566,39 @@ static struct clk ssi_sst_fck = {
1641 */ 1566 */
1642static struct clk core_l3_ick = { 1567static struct clk core_l3_ick = {
1643 .name = "core_l3_ick", 1568 .name = "core_l3_ick",
1569 .ops = &clkops_null,
1644 .parent = &l3_ick, 1570 .parent = &l3_ick,
1645 .init = &omap2_init_clk_clkdm, 1571 .init = &omap2_init_clk_clkdm,
1646 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1647 PARENT_CONTROLS_CLOCK,
1648 .clkdm_name = "core_l3_clkdm", 1572 .clkdm_name = "core_l3_clkdm",
1649 .recalc = &followparent_recalc, 1573 .recalc = &followparent_recalc,
1650}; 1574};
1651 1575
1652static struct clk hsotgusb_ick = { 1576static struct clk hsotgusb_ick = {
1653 .name = "hsotgusb_ick", 1577 .name = "hsotgusb_ick",
1578 .ops = &clkops_omap2_dflt_wait,
1654 .parent = &core_l3_ick, 1579 .parent = &core_l3_ick,
1655 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1580 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1656 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1581 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1657 .flags = CLOCK_IN_OMAP343X,
1658 .clkdm_name = "core_l3_clkdm", 1582 .clkdm_name = "core_l3_clkdm",
1659 .recalc = &followparent_recalc, 1583 .recalc = &followparent_recalc,
1660}; 1584};
1661 1585
1662static struct clk sdrc_ick = { 1586static struct clk sdrc_ick = {
1663 .name = "sdrc_ick", 1587 .name = "sdrc_ick",
1588 .ops = &clkops_omap2_dflt_wait,
1664 .parent = &core_l3_ick, 1589 .parent = &core_l3_ick,
1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1590 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1666 .enable_bit = OMAP3430_EN_SDRC_SHIFT, 1591 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1667 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, 1592 .flags = ENABLE_ON_INIT,
1668 .clkdm_name = "core_l3_clkdm", 1593 .clkdm_name = "core_l3_clkdm",
1669 .recalc = &followparent_recalc, 1594 .recalc = &followparent_recalc,
1670}; 1595};
1671 1596
1672static struct clk gpmc_fck = { 1597static struct clk gpmc_fck = {
1673 .name = "gpmc_fck", 1598 .name = "gpmc_fck",
1599 .ops = &clkops_null,
1674 .parent = &core_l3_ick, 1600 .parent = &core_l3_ick,
1675 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | 1601 .flags = ENABLE_ON_INIT, /* huh? */
1676 ENABLE_ON_INIT,
1677 .clkdm_name = "core_l3_clkdm", 1602 .clkdm_name = "core_l3_clkdm",
1678 .recalc = &followparent_recalc, 1603 .recalc = &followparent_recalc,
1679}; 1604};
@@ -1682,18 +1607,17 @@ static struct clk gpmc_fck = {
1682 1607
1683static struct clk security_l3_ick = { 1608static struct clk security_l3_ick = {
1684 .name = "security_l3_ick", 1609 .name = "security_l3_ick",
1610 .ops = &clkops_null,
1685 .parent = &l3_ick, 1611 .parent = &l3_ick,
1686 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1687 PARENT_CONTROLS_CLOCK,
1688 .recalc = &followparent_recalc, 1612 .recalc = &followparent_recalc,
1689}; 1613};
1690 1614
1691static struct clk pka_ick = { 1615static struct clk pka_ick = {
1692 .name = "pka_ick", 1616 .name = "pka_ick",
1617 .ops = &clkops_omap2_dflt_wait,
1693 .parent = &security_l3_ick, 1618 .parent = &security_l3_ick,
1694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1619 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1695 .enable_bit = OMAP3430_EN_PKA_SHIFT, 1620 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1696 .flags = CLOCK_IN_OMAP343X,
1697 .recalc = &followparent_recalc, 1621 .recalc = &followparent_recalc,
1698}; 1622};
1699 1623
@@ -1701,31 +1625,30 @@ static struct clk pka_ick = {
1701 1625
1702static struct clk core_l4_ick = { 1626static struct clk core_l4_ick = {
1703 .name = "core_l4_ick", 1627 .name = "core_l4_ick",
1628 .ops = &clkops_null,
1704 .parent = &l4_ick, 1629 .parent = &l4_ick,
1705 .init = &omap2_init_clk_clkdm, 1630 .init = &omap2_init_clk_clkdm,
1706 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1707 PARENT_CONTROLS_CLOCK,
1708 .clkdm_name = "core_l4_clkdm", 1631 .clkdm_name = "core_l4_clkdm",
1709 .recalc = &followparent_recalc, 1632 .recalc = &followparent_recalc,
1710}; 1633};
1711 1634
1712static struct clk usbtll_ick = { 1635static struct clk usbtll_ick = {
1713 .name = "usbtll_ick", 1636 .name = "usbtll_ick",
1637 .ops = &clkops_omap2_dflt_wait,
1714 .parent = &core_l4_ick, 1638 .parent = &core_l4_ick,
1715 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1639 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1716 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1640 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1717 .flags = CLOCK_IN_OMAP3430ES2,
1718 .clkdm_name = "core_l4_clkdm", 1641 .clkdm_name = "core_l4_clkdm",
1719 .recalc = &followparent_recalc, 1642 .recalc = &followparent_recalc,
1720}; 1643};
1721 1644
1722static struct clk mmchs3_ick = { 1645static struct clk mmchs3_ick = {
1723 .name = "mmchs_ick", 1646 .name = "mmchs_ick",
1647 .ops = &clkops_omap2_dflt_wait,
1724 .id = 2, 1648 .id = 2,
1725 .parent = &core_l4_ick, 1649 .parent = &core_l4_ick,
1726 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1727 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1651 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1728 .flags = CLOCK_IN_OMAP3430ES2,
1729 .clkdm_name = "core_l4_clkdm", 1652 .clkdm_name = "core_l4_clkdm",
1730 .recalc = &followparent_recalc, 1653 .recalc = &followparent_recalc,
1731}; 1654};
@@ -1733,250 +1656,251 @@ static struct clk mmchs3_ick = {
1733/* Intersystem Communication Registers - chassis mode only */ 1656/* Intersystem Communication Registers - chassis mode only */
1734static struct clk icr_ick = { 1657static struct clk icr_ick = {
1735 .name = "icr_ick", 1658 .name = "icr_ick",
1659 .ops = &clkops_omap2_dflt_wait,
1736 .parent = &core_l4_ick, 1660 .parent = &core_l4_ick,
1737 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1661 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1738 .enable_bit = OMAP3430_EN_ICR_SHIFT, 1662 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1739 .flags = CLOCK_IN_OMAP343X,
1740 .clkdm_name = "core_l4_clkdm", 1663 .clkdm_name = "core_l4_clkdm",
1741 .recalc = &followparent_recalc, 1664 .recalc = &followparent_recalc,
1742}; 1665};
1743 1666
1744static struct clk aes2_ick = { 1667static struct clk aes2_ick = {
1745 .name = "aes2_ick", 1668 .name = "aes2_ick",
1669 .ops = &clkops_omap2_dflt_wait,
1746 .parent = &core_l4_ick, 1670 .parent = &core_l4_ick,
1747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1671 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1748 .enable_bit = OMAP3430_EN_AES2_SHIFT, 1672 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1749 .flags = CLOCK_IN_OMAP343X,
1750 .clkdm_name = "core_l4_clkdm", 1673 .clkdm_name = "core_l4_clkdm",
1751 .recalc = &followparent_recalc, 1674 .recalc = &followparent_recalc,
1752}; 1675};
1753 1676
1754static struct clk sha12_ick = { 1677static struct clk sha12_ick = {
1755 .name = "sha12_ick", 1678 .name = "sha12_ick",
1679 .ops = &clkops_omap2_dflt_wait,
1756 .parent = &core_l4_ick, 1680 .parent = &core_l4_ick,
1757 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1681 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1758 .enable_bit = OMAP3430_EN_SHA12_SHIFT, 1682 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1759 .flags = CLOCK_IN_OMAP343X,
1760 .clkdm_name = "core_l4_clkdm", 1683 .clkdm_name = "core_l4_clkdm",
1761 .recalc = &followparent_recalc, 1684 .recalc = &followparent_recalc,
1762}; 1685};
1763 1686
1764static struct clk des2_ick = { 1687static struct clk des2_ick = {
1765 .name = "des2_ick", 1688 .name = "des2_ick",
1689 .ops = &clkops_omap2_dflt_wait,
1766 .parent = &core_l4_ick, 1690 .parent = &core_l4_ick,
1767 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1691 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1768 .enable_bit = OMAP3430_EN_DES2_SHIFT, 1692 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1769 .flags = CLOCK_IN_OMAP343X,
1770 .clkdm_name = "core_l4_clkdm", 1693 .clkdm_name = "core_l4_clkdm",
1771 .recalc = &followparent_recalc, 1694 .recalc = &followparent_recalc,
1772}; 1695};
1773 1696
1774static struct clk mmchs2_ick = { 1697static struct clk mmchs2_ick = {
1775 .name = "mmchs_ick", 1698 .name = "mmchs_ick",
1699 .ops = &clkops_omap2_dflt_wait,
1776 .id = 1, 1700 .id = 1,
1777 .parent = &core_l4_ick, 1701 .parent = &core_l4_ick,
1778 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1702 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1779 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1703 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1780 .flags = CLOCK_IN_OMAP343X,
1781 .clkdm_name = "core_l4_clkdm", 1704 .clkdm_name = "core_l4_clkdm",
1782 .recalc = &followparent_recalc, 1705 .recalc = &followparent_recalc,
1783}; 1706};
1784 1707
1785static struct clk mmchs1_ick = { 1708static struct clk mmchs1_ick = {
1786 .name = "mmchs_ick", 1709 .name = "mmchs_ick",
1710 .ops = &clkops_omap2_dflt_wait,
1787 .parent = &core_l4_ick, 1711 .parent = &core_l4_ick,
1788 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1712 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1789 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1713 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1790 .flags = CLOCK_IN_OMAP343X,
1791 .clkdm_name = "core_l4_clkdm", 1714 .clkdm_name = "core_l4_clkdm",
1792 .recalc = &followparent_recalc, 1715 .recalc = &followparent_recalc,
1793}; 1716};
1794 1717
1795static struct clk mspro_ick = { 1718static struct clk mspro_ick = {
1796 .name = "mspro_ick", 1719 .name = "mspro_ick",
1720 .ops = &clkops_omap2_dflt_wait,
1797 .parent = &core_l4_ick, 1721 .parent = &core_l4_ick,
1798 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1722 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1799 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1723 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1800 .flags = CLOCK_IN_OMAP343X,
1801 .clkdm_name = "core_l4_clkdm", 1724 .clkdm_name = "core_l4_clkdm",
1802 .recalc = &followparent_recalc, 1725 .recalc = &followparent_recalc,
1803}; 1726};
1804 1727
1805static struct clk hdq_ick = { 1728static struct clk hdq_ick = {
1806 .name = "hdq_ick", 1729 .name = "hdq_ick",
1730 .ops = &clkops_omap2_dflt_wait,
1807 .parent = &core_l4_ick, 1731 .parent = &core_l4_ick,
1808 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1732 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1809 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1733 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1810 .flags = CLOCK_IN_OMAP343X,
1811 .clkdm_name = "core_l4_clkdm", 1734 .clkdm_name = "core_l4_clkdm",
1812 .recalc = &followparent_recalc, 1735 .recalc = &followparent_recalc,
1813}; 1736};
1814 1737
1815static struct clk mcspi4_ick = { 1738static struct clk mcspi4_ick = {
1816 .name = "mcspi_ick", 1739 .name = "mcspi_ick",
1740 .ops = &clkops_omap2_dflt_wait,
1817 .id = 4, 1741 .id = 4,
1818 .parent = &core_l4_ick, 1742 .parent = &core_l4_ick,
1819 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1743 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1820 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1744 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1821 .flags = CLOCK_IN_OMAP343X,
1822 .clkdm_name = "core_l4_clkdm", 1745 .clkdm_name = "core_l4_clkdm",
1823 .recalc = &followparent_recalc, 1746 .recalc = &followparent_recalc,
1824}; 1747};
1825 1748
1826static struct clk mcspi3_ick = { 1749static struct clk mcspi3_ick = {
1827 .name = "mcspi_ick", 1750 .name = "mcspi_ick",
1751 .ops = &clkops_omap2_dflt_wait,
1828 .id = 3, 1752 .id = 3,
1829 .parent = &core_l4_ick, 1753 .parent = &core_l4_ick,
1830 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1754 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1831 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1755 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1832 .flags = CLOCK_IN_OMAP343X,
1833 .clkdm_name = "core_l4_clkdm", 1756 .clkdm_name = "core_l4_clkdm",
1834 .recalc = &followparent_recalc, 1757 .recalc = &followparent_recalc,
1835}; 1758};
1836 1759
1837static struct clk mcspi2_ick = { 1760static struct clk mcspi2_ick = {
1838 .name = "mcspi_ick", 1761 .name = "mcspi_ick",
1762 .ops = &clkops_omap2_dflt_wait,
1839 .id = 2, 1763 .id = 2,
1840 .parent = &core_l4_ick, 1764 .parent = &core_l4_ick,
1841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1842 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1766 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1843 .flags = CLOCK_IN_OMAP343X,
1844 .clkdm_name = "core_l4_clkdm", 1767 .clkdm_name = "core_l4_clkdm",
1845 .recalc = &followparent_recalc, 1768 .recalc = &followparent_recalc,
1846}; 1769};
1847 1770
1848static struct clk mcspi1_ick = { 1771static struct clk mcspi1_ick = {
1849 .name = "mcspi_ick", 1772 .name = "mcspi_ick",
1773 .ops = &clkops_omap2_dflt_wait,
1850 .id = 1, 1774 .id = 1,
1851 .parent = &core_l4_ick, 1775 .parent = &core_l4_ick,
1852 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1776 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1853 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1777 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1854 .flags = CLOCK_IN_OMAP343X,
1855 .clkdm_name = "core_l4_clkdm", 1778 .clkdm_name = "core_l4_clkdm",
1856 .recalc = &followparent_recalc, 1779 .recalc = &followparent_recalc,
1857}; 1780};
1858 1781
1859static struct clk i2c3_ick = { 1782static struct clk i2c3_ick = {
1860 .name = "i2c_ick", 1783 .name = "i2c_ick",
1784 .ops = &clkops_omap2_dflt_wait,
1861 .id = 3, 1785 .id = 3,
1862 .parent = &core_l4_ick, 1786 .parent = &core_l4_ick,
1863 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1787 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1864 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1788 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1865 .flags = CLOCK_IN_OMAP343X,
1866 .clkdm_name = "core_l4_clkdm", 1789 .clkdm_name = "core_l4_clkdm",
1867 .recalc = &followparent_recalc, 1790 .recalc = &followparent_recalc,
1868}; 1791};
1869 1792
1870static struct clk i2c2_ick = { 1793static struct clk i2c2_ick = {
1871 .name = "i2c_ick", 1794 .name = "i2c_ick",
1795 .ops = &clkops_omap2_dflt_wait,
1872 .id = 2, 1796 .id = 2,
1873 .parent = &core_l4_ick, 1797 .parent = &core_l4_ick,
1874 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1798 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1875 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1799 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1876 .flags = CLOCK_IN_OMAP343X,
1877 .clkdm_name = "core_l4_clkdm", 1800 .clkdm_name = "core_l4_clkdm",
1878 .recalc = &followparent_recalc, 1801 .recalc = &followparent_recalc,
1879}; 1802};
1880 1803
1881static struct clk i2c1_ick = { 1804static struct clk i2c1_ick = {
1882 .name = "i2c_ick", 1805 .name = "i2c_ick",
1806 .ops = &clkops_omap2_dflt_wait,
1883 .id = 1, 1807 .id = 1,
1884 .parent = &core_l4_ick, 1808 .parent = &core_l4_ick,
1885 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1809 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1886 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1810 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1887 .flags = CLOCK_IN_OMAP343X,
1888 .clkdm_name = "core_l4_clkdm", 1811 .clkdm_name = "core_l4_clkdm",
1889 .recalc = &followparent_recalc, 1812 .recalc = &followparent_recalc,
1890}; 1813};
1891 1814
1892static struct clk uart2_ick = { 1815static struct clk uart2_ick = {
1893 .name = "uart2_ick", 1816 .name = "uart2_ick",
1817 .ops = &clkops_omap2_dflt_wait,
1894 .parent = &core_l4_ick, 1818 .parent = &core_l4_ick,
1895 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1819 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1896 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1820 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1897 .flags = CLOCK_IN_OMAP343X,
1898 .clkdm_name = "core_l4_clkdm", 1821 .clkdm_name = "core_l4_clkdm",
1899 .recalc = &followparent_recalc, 1822 .recalc = &followparent_recalc,
1900}; 1823};
1901 1824
1902static struct clk uart1_ick = { 1825static struct clk uart1_ick = {
1903 .name = "uart1_ick", 1826 .name = "uart1_ick",
1827 .ops = &clkops_omap2_dflt_wait,
1904 .parent = &core_l4_ick, 1828 .parent = &core_l4_ick,
1905 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1829 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1906 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1830 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1907 .flags = CLOCK_IN_OMAP343X,
1908 .clkdm_name = "core_l4_clkdm", 1831 .clkdm_name = "core_l4_clkdm",
1909 .recalc = &followparent_recalc, 1832 .recalc = &followparent_recalc,
1910}; 1833};
1911 1834
1912static struct clk gpt11_ick = { 1835static struct clk gpt11_ick = {
1913 .name = "gpt11_ick", 1836 .name = "gpt11_ick",
1837 .ops = &clkops_omap2_dflt_wait,
1914 .parent = &core_l4_ick, 1838 .parent = &core_l4_ick,
1915 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1839 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1916 .enable_bit = OMAP3430_EN_GPT11_SHIFT, 1840 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1917 .flags = CLOCK_IN_OMAP343X,
1918 .clkdm_name = "core_l4_clkdm", 1841 .clkdm_name = "core_l4_clkdm",
1919 .recalc = &followparent_recalc, 1842 .recalc = &followparent_recalc,
1920}; 1843};
1921 1844
1922static struct clk gpt10_ick = { 1845static struct clk gpt10_ick = {
1923 .name = "gpt10_ick", 1846 .name = "gpt10_ick",
1847 .ops = &clkops_omap2_dflt_wait,
1924 .parent = &core_l4_ick, 1848 .parent = &core_l4_ick,
1925 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1849 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1926 .enable_bit = OMAP3430_EN_GPT10_SHIFT, 1850 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1927 .flags = CLOCK_IN_OMAP343X,
1928 .clkdm_name = "core_l4_clkdm", 1851 .clkdm_name = "core_l4_clkdm",
1929 .recalc = &followparent_recalc, 1852 .recalc = &followparent_recalc,
1930}; 1853};
1931 1854
1932static struct clk mcbsp5_ick = { 1855static struct clk mcbsp5_ick = {
1933 .name = "mcbsp_ick", 1856 .name = "mcbsp_ick",
1857 .ops = &clkops_omap2_dflt_wait,
1934 .id = 5, 1858 .id = 5,
1935 .parent = &core_l4_ick, 1859 .parent = &core_l4_ick,
1936 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1860 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1937 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 1861 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1938 .flags = CLOCK_IN_OMAP343X,
1939 .clkdm_name = "core_l4_clkdm", 1862 .clkdm_name = "core_l4_clkdm",
1940 .recalc = &followparent_recalc, 1863 .recalc = &followparent_recalc,
1941}; 1864};
1942 1865
1943static struct clk mcbsp1_ick = { 1866static struct clk mcbsp1_ick = {
1944 .name = "mcbsp_ick", 1867 .name = "mcbsp_ick",
1868 .ops = &clkops_omap2_dflt_wait,
1945 .id = 1, 1869 .id = 1,
1946 .parent = &core_l4_ick, 1870 .parent = &core_l4_ick,
1947 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1948 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 1872 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1949 .flags = CLOCK_IN_OMAP343X,
1950 .clkdm_name = "core_l4_clkdm", 1873 .clkdm_name = "core_l4_clkdm",
1951 .recalc = &followparent_recalc, 1874 .recalc = &followparent_recalc,
1952}; 1875};
1953 1876
1954static struct clk fac_ick = { 1877static struct clk fac_ick = {
1955 .name = "fac_ick", 1878 .name = "fac_ick",
1879 .ops = &clkops_omap2_dflt_wait,
1956 .parent = &core_l4_ick, 1880 .parent = &core_l4_ick,
1957 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1958 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, 1882 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1959 .flags = CLOCK_IN_OMAP3430ES1,
1960 .clkdm_name = "core_l4_clkdm", 1883 .clkdm_name = "core_l4_clkdm",
1961 .recalc = &followparent_recalc, 1884 .recalc = &followparent_recalc,
1962}; 1885};
1963 1886
1964static struct clk mailboxes_ick = { 1887static struct clk mailboxes_ick = {
1965 .name = "mailboxes_ick", 1888 .name = "mailboxes_ick",
1889 .ops = &clkops_omap2_dflt_wait,
1966 .parent = &core_l4_ick, 1890 .parent = &core_l4_ick,
1967 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1968 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, 1892 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1969 .flags = CLOCK_IN_OMAP343X,
1970 .clkdm_name = "core_l4_clkdm", 1893 .clkdm_name = "core_l4_clkdm",
1971 .recalc = &followparent_recalc, 1894 .recalc = &followparent_recalc,
1972}; 1895};
1973 1896
1974static struct clk omapctrl_ick = { 1897static struct clk omapctrl_ick = {
1975 .name = "omapctrl_ick", 1898 .name = "omapctrl_ick",
1899 .ops = &clkops_omap2_dflt_wait,
1976 .parent = &core_l4_ick, 1900 .parent = &core_l4_ick,
1977 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1901 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1978 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, 1902 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
1979 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, 1903 .flags = ENABLE_ON_INIT,
1980 .recalc = &followparent_recalc, 1904 .recalc = &followparent_recalc,
1981}; 1905};
1982 1906
@@ -1984,19 +1908,18 @@ static struct clk omapctrl_ick = {
1984 1908
1985static struct clk ssi_l4_ick = { 1909static struct clk ssi_l4_ick = {
1986 .name = "ssi_l4_ick", 1910 .name = "ssi_l4_ick",
1911 .ops = &clkops_null,
1987 .parent = &l4_ick, 1912 .parent = &l4_ick,
1988 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1989 PARENT_CONTROLS_CLOCK,
1990 .clkdm_name = "core_l4_clkdm", 1913 .clkdm_name = "core_l4_clkdm",
1991 .recalc = &followparent_recalc, 1914 .recalc = &followparent_recalc,
1992}; 1915};
1993 1916
1994static struct clk ssi_ick = { 1917static struct clk ssi_ick = {
1995 .name = "ssi_ick", 1918 .name = "ssi_ick",
1919 .ops = &clkops_omap2_dflt,
1996 .parent = &ssi_l4_ick, 1920 .parent = &ssi_l4_ick,
1997 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1921 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1998 .enable_bit = OMAP3430_EN_SSI_SHIFT, 1922 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1999 .flags = CLOCK_IN_OMAP343X,
2000 .clkdm_name = "core_l4_clkdm", 1923 .clkdm_name = "core_l4_clkdm",
2001 .recalc = &followparent_recalc, 1924 .recalc = &followparent_recalc,
2002}; 1925};
@@ -2011,6 +1934,7 @@ static const struct clksel usb_l4_clksel[] = {
2011 1934
2012static struct clk usb_l4_ick = { 1935static struct clk usb_l4_ick = {
2013 .name = "usb_l4_ick", 1936 .name = "usb_l4_ick",
1937 .ops = &clkops_omap2_dflt_wait,
2014 .parent = &l4_ick, 1938 .parent = &l4_ick,
2015 .init = &omap2_init_clksel_parent, 1939 .init = &omap2_init_clksel_parent,
2016 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -2018,7 +1942,6 @@ static struct clk usb_l4_ick = {
2018 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1942 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2019 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, 1943 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2020 .clksel = usb_l4_clksel, 1944 .clksel = usb_l4_clksel,
2021 .flags = CLOCK_IN_OMAP3430ES1,
2022 .recalc = &omap2_clksel_recalc, 1945 .recalc = &omap2_clksel_recalc,
2023}; 1946};
2024 1947
@@ -2028,98 +1951,87 @@ static struct clk usb_l4_ick = {
2028 1951
2029static struct clk security_l4_ick2 = { 1952static struct clk security_l4_ick2 = {
2030 .name = "security_l4_ick2", 1953 .name = "security_l4_ick2",
1954 .ops = &clkops_null,
2031 .parent = &l4_ick, 1955 .parent = &l4_ick,
2032 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2033 PARENT_CONTROLS_CLOCK,
2034 .recalc = &followparent_recalc, 1956 .recalc = &followparent_recalc,
2035}; 1957};
2036 1958
2037static struct clk aes1_ick = { 1959static struct clk aes1_ick = {
2038 .name = "aes1_ick", 1960 .name = "aes1_ick",
1961 .ops = &clkops_omap2_dflt_wait,
2039 .parent = &security_l4_ick2, 1962 .parent = &security_l4_ick2,
2040 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1963 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2041 .enable_bit = OMAP3430_EN_AES1_SHIFT, 1964 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2042 .flags = CLOCK_IN_OMAP343X,
2043 .recalc = &followparent_recalc, 1965 .recalc = &followparent_recalc,
2044}; 1966};
2045 1967
2046static struct clk rng_ick = { 1968static struct clk rng_ick = {
2047 .name = "rng_ick", 1969 .name = "rng_ick",
1970 .ops = &clkops_omap2_dflt_wait,
2048 .parent = &security_l4_ick2, 1971 .parent = &security_l4_ick2,
2049 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2050 .enable_bit = OMAP3430_EN_RNG_SHIFT, 1973 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2051 .flags = CLOCK_IN_OMAP343X,
2052 .recalc = &followparent_recalc, 1974 .recalc = &followparent_recalc,
2053}; 1975};
2054 1976
2055static struct clk sha11_ick = { 1977static struct clk sha11_ick = {
2056 .name = "sha11_ick", 1978 .name = "sha11_ick",
1979 .ops = &clkops_omap2_dflt_wait,
2057 .parent = &security_l4_ick2, 1980 .parent = &security_l4_ick2,
2058 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1981 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2059 .enable_bit = OMAP3430_EN_SHA11_SHIFT, 1982 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2060 .flags = CLOCK_IN_OMAP343X,
2061 .recalc = &followparent_recalc, 1983 .recalc = &followparent_recalc,
2062}; 1984};
2063 1985
2064static struct clk des1_ick = { 1986static struct clk des1_ick = {
2065 .name = "des1_ick", 1987 .name = "des1_ick",
1988 .ops = &clkops_omap2_dflt_wait,
2066 .parent = &security_l4_ick2, 1989 .parent = &security_l4_ick2,
2067 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1990 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2068 .enable_bit = OMAP3430_EN_DES1_SHIFT, 1991 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2069 .flags = CLOCK_IN_OMAP343X,
2070 .recalc = &followparent_recalc, 1992 .recalc = &followparent_recalc,
2071}; 1993};
2072 1994
2073/* DSS */ 1995/* DSS */
2074static const struct clksel dss1_alwon_fck_clksel[] = {
2075 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2076 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2077 { .parent = NULL }
2078};
2079
2080static struct clk dss1_alwon_fck = { 1996static struct clk dss1_alwon_fck = {
2081 .name = "dss1_alwon_fck", 1997 .name = "dss1_alwon_fck",
1998 .ops = &clkops_omap2_dflt,
2082 .parent = &dpll4_m4x2_ck, 1999 .parent = &dpll4_m4x2_ck,
2083 .init = &omap2_init_clksel_parent,
2084 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2000 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2085 .enable_bit = OMAP3430_EN_DSS1_SHIFT, 2001 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2086 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2087 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2088 .clksel = dss1_alwon_fck_clksel,
2089 .flags = CLOCK_IN_OMAP343X,
2090 .clkdm_name = "dss_clkdm", 2002 .clkdm_name = "dss_clkdm",
2091 .recalc = &omap2_clksel_recalc, 2003 .recalc = &followparent_recalc,
2092}; 2004};
2093 2005
2094static struct clk dss_tv_fck = { 2006static struct clk dss_tv_fck = {
2095 .name = "dss_tv_fck", 2007 .name = "dss_tv_fck",
2008 .ops = &clkops_omap2_dflt,
2096 .parent = &omap_54m_fck, 2009 .parent = &omap_54m_fck,
2097 .init = &omap2_init_clk_clkdm, 2010 .init = &omap2_init_clk_clkdm,
2098 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2011 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2099 .enable_bit = OMAP3430_EN_TV_SHIFT, 2012 .enable_bit = OMAP3430_EN_TV_SHIFT,
2100 .flags = CLOCK_IN_OMAP343X,
2101 .clkdm_name = "dss_clkdm", 2013 .clkdm_name = "dss_clkdm",
2102 .recalc = &followparent_recalc, 2014 .recalc = &followparent_recalc,
2103}; 2015};
2104 2016
2105static struct clk dss_96m_fck = { 2017static struct clk dss_96m_fck = {
2106 .name = "dss_96m_fck", 2018 .name = "dss_96m_fck",
2019 .ops = &clkops_omap2_dflt,
2107 .parent = &omap_96m_fck, 2020 .parent = &omap_96m_fck,
2108 .init = &omap2_init_clk_clkdm, 2021 .init = &omap2_init_clk_clkdm,
2109 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2022 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2110 .enable_bit = OMAP3430_EN_TV_SHIFT, 2023 .enable_bit = OMAP3430_EN_TV_SHIFT,
2111 .flags = CLOCK_IN_OMAP343X,
2112 .clkdm_name = "dss_clkdm", 2024 .clkdm_name = "dss_clkdm",
2113 .recalc = &followparent_recalc, 2025 .recalc = &followparent_recalc,
2114}; 2026};
2115 2027
2116static struct clk dss2_alwon_fck = { 2028static struct clk dss2_alwon_fck = {
2117 .name = "dss2_alwon_fck", 2029 .name = "dss2_alwon_fck",
2030 .ops = &clkops_omap2_dflt,
2118 .parent = &sys_ck, 2031 .parent = &sys_ck,
2119 .init = &omap2_init_clk_clkdm, 2032 .init = &omap2_init_clk_clkdm,
2120 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2033 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2121 .enable_bit = OMAP3430_EN_DSS2_SHIFT, 2034 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2122 .flags = CLOCK_IN_OMAP343X,
2123 .clkdm_name = "dss_clkdm", 2035 .clkdm_name = "dss_clkdm",
2124 .recalc = &followparent_recalc, 2036 .recalc = &followparent_recalc,
2125}; 2037};
@@ -2127,45 +2039,46 @@ static struct clk dss2_alwon_fck = {
2127static struct clk dss_ick = { 2039static struct clk dss_ick = {
2128 /* Handles both L3 and L4 clocks */ 2040 /* Handles both L3 and L4 clocks */
2129 .name = "dss_ick", 2041 .name = "dss_ick",
2042 .ops = &clkops_omap2_dflt,
2130 .parent = &l4_ick, 2043 .parent = &l4_ick,
2131 .init = &omap2_init_clk_clkdm, 2044 .init = &omap2_init_clk_clkdm,
2132 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), 2045 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2133 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, 2046 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2134 .flags = CLOCK_IN_OMAP343X,
2135 .clkdm_name = "dss_clkdm", 2047 .clkdm_name = "dss_clkdm",
2136 .recalc = &followparent_recalc, 2048 .recalc = &followparent_recalc,
2137}; 2049};
2138 2050
2139/* CAM */ 2051/* CAM */
2140 2052
2141static const struct clksel cam_mclk_clksel[] = {
2142 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2143 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2144 { .parent = NULL }
2145};
2146
2147static struct clk cam_mclk = { 2053static struct clk cam_mclk = {
2148 .name = "cam_mclk", 2054 .name = "cam_mclk",
2055 .ops = &clkops_omap2_dflt_wait,
2149 .parent = &dpll4_m5x2_ck, 2056 .parent = &dpll4_m5x2_ck,
2150 .init = &omap2_init_clksel_parent,
2151 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2152 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2153 .clksel = cam_mclk_clksel,
2154 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), 2057 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2155 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2058 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2156 .flags = CLOCK_IN_OMAP343X,
2157 .clkdm_name = "cam_clkdm", 2059 .clkdm_name = "cam_clkdm",
2158 .recalc = &omap2_clksel_recalc, 2060 .recalc = &followparent_recalc,
2159}; 2061};
2160 2062
2161static struct clk cam_ick = { 2063static struct clk cam_ick = {
2162 /* Handles both L3 and L4 clocks */ 2064 /* Handles both L3 and L4 clocks */
2163 .name = "cam_ick", 2065 .name = "cam_ick",
2066 .ops = &clkops_omap2_dflt_wait,
2164 .parent = &l4_ick, 2067 .parent = &l4_ick,
2165 .init = &omap2_init_clk_clkdm, 2068 .init = &omap2_init_clk_clkdm,
2166 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), 2069 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2167 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2070 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2168 .flags = CLOCK_IN_OMAP343X, 2071 .clkdm_name = "cam_clkdm",
2072 .recalc = &followparent_recalc,
2073};
2074
2075static struct clk csi2_96m_fck = {
2076 .name = "csi2_96m_fck",
2077 .ops = &clkops_omap2_dflt_wait,
2078 .parent = &core_96m_fck,
2079 .init = &omap2_init_clk_clkdm,
2080 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2081 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2169 .clkdm_name = "cam_clkdm", 2082 .clkdm_name = "cam_clkdm",
2170 .recalc = &followparent_recalc, 2083 .recalc = &followparent_recalc,
2171}; 2084};
@@ -2174,22 +2087,22 @@ static struct clk cam_ick = {
2174 2087
2175static struct clk usbhost_120m_fck = { 2088static struct clk usbhost_120m_fck = {
2176 .name = "usbhost_120m_fck", 2089 .name = "usbhost_120m_fck",
2177 .parent = &omap_120m_fck, 2090 .ops = &clkops_omap2_dflt_wait,
2091 .parent = &dpll5_m2_ck,
2178 .init = &omap2_init_clk_clkdm, 2092 .init = &omap2_init_clk_clkdm,
2179 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2093 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2180 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, 2094 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2181 .flags = CLOCK_IN_OMAP3430ES2,
2182 .clkdm_name = "usbhost_clkdm", 2095 .clkdm_name = "usbhost_clkdm",
2183 .recalc = &followparent_recalc, 2096 .recalc = &followparent_recalc,
2184}; 2097};
2185 2098
2186static struct clk usbhost_48m_fck = { 2099static struct clk usbhost_48m_fck = {
2187 .name = "usbhost_48m_fck", 2100 .name = "usbhost_48m_fck",
2101 .ops = &clkops_omap2_dflt_wait,
2188 .parent = &omap_48m_fck, 2102 .parent = &omap_48m_fck,
2189 .init = &omap2_init_clk_clkdm, 2103 .init = &omap2_init_clk_clkdm,
2190 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2104 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2191 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, 2105 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2192 .flags = CLOCK_IN_OMAP3430ES2,
2193 .clkdm_name = "usbhost_clkdm", 2106 .clkdm_name = "usbhost_clkdm",
2194 .recalc = &followparent_recalc, 2107 .recalc = &followparent_recalc,
2195}; 2108};
@@ -2197,22 +2110,11 @@ static struct clk usbhost_48m_fck = {
2197static struct clk usbhost_ick = { 2110static struct clk usbhost_ick = {
2198 /* Handles both L3 and L4 clocks */ 2111 /* Handles both L3 and L4 clocks */
2199 .name = "usbhost_ick", 2112 .name = "usbhost_ick",
2113 .ops = &clkops_omap2_dflt_wait,
2200 .parent = &l4_ick, 2114 .parent = &l4_ick,
2201 .init = &omap2_init_clk_clkdm, 2115 .init = &omap2_init_clk_clkdm,
2202 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), 2116 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2203 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, 2117 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2204 .flags = CLOCK_IN_OMAP3430ES2,
2205 .clkdm_name = "usbhost_clkdm",
2206 .recalc = &followparent_recalc,
2207};
2208
2209static struct clk usbhost_sar_fck = {
2210 .name = "usbhost_sar_fck",
2211 .parent = &osc_sys_ck,
2212 .init = &omap2_init_clk_clkdm,
2213 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2214 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2215 .flags = CLOCK_IN_OMAP3430ES2,
2216 .clkdm_name = "usbhost_clkdm", 2118 .clkdm_name = "usbhost_clkdm",
2217 .recalc = &followparent_recalc, 2119 .recalc = &followparent_recalc,
2218}; 2120};
@@ -2237,7 +2139,7 @@ static const struct clksel_rate usim_120m_rates[] = {
2237 2139
2238static const struct clksel usim_clksel[] = { 2140static const struct clksel usim_clksel[] = {
2239 { .parent = &omap_96m_fck, .rates = usim_96m_rates }, 2141 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2240 { .parent = &omap_120m_fck, .rates = usim_120m_rates }, 2142 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2241 { .parent = &sys_ck, .rates = div2_rates }, 2143 { .parent = &sys_ck, .rates = div2_rates },
2242 { .parent = NULL }, 2144 { .parent = NULL },
2243}; 2145};
@@ -2245,63 +2147,63 @@ static const struct clksel usim_clksel[] = {
2245/* 3430ES2 only */ 2147/* 3430ES2 only */
2246static struct clk usim_fck = { 2148static struct clk usim_fck = {
2247 .name = "usim_fck", 2149 .name = "usim_fck",
2150 .ops = &clkops_omap2_dflt_wait,
2248 .init = &omap2_init_clksel_parent, 2151 .init = &omap2_init_clksel_parent,
2249 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2152 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2250 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, 2153 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2251 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), 2154 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2252 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, 2155 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2253 .clksel = usim_clksel, 2156 .clksel = usim_clksel,
2254 .flags = CLOCK_IN_OMAP3430ES2,
2255 .recalc = &omap2_clksel_recalc, 2157 .recalc = &omap2_clksel_recalc,
2256}; 2158};
2257 2159
2258/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ 2160/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2259static struct clk gpt1_fck = { 2161static struct clk gpt1_fck = {
2260 .name = "gpt1_fck", 2162 .name = "gpt1_fck",
2163 .ops = &clkops_omap2_dflt_wait,
2261 .init = &omap2_init_clksel_parent, 2164 .init = &omap2_init_clksel_parent,
2262 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2165 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2263 .enable_bit = OMAP3430_EN_GPT1_SHIFT, 2166 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2264 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), 2167 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2265 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, 2168 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2266 .clksel = omap343x_gpt_clksel, 2169 .clksel = omap343x_gpt_clksel,
2267 .flags = CLOCK_IN_OMAP343X,
2268 .clkdm_name = "wkup_clkdm", 2170 .clkdm_name = "wkup_clkdm",
2269 .recalc = &omap2_clksel_recalc, 2171 .recalc = &omap2_clksel_recalc,
2270}; 2172};
2271 2173
2272static struct clk wkup_32k_fck = { 2174static struct clk wkup_32k_fck = {
2273 .name = "wkup_32k_fck", 2175 .name = "wkup_32k_fck",
2176 .ops = &clkops_null,
2274 .init = &omap2_init_clk_clkdm, 2177 .init = &omap2_init_clk_clkdm,
2275 .parent = &omap_32k_fck, 2178 .parent = &omap_32k_fck,
2276 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2277 .clkdm_name = "wkup_clkdm", 2179 .clkdm_name = "wkup_clkdm",
2278 .recalc = &followparent_recalc, 2180 .recalc = &followparent_recalc,
2279}; 2181};
2280 2182
2281static struct clk gpio1_dbck = { 2183static struct clk gpio1_dbck = {
2282 .name = "gpio1_dbck", 2184 .name = "gpio1_dbck",
2185 .ops = &clkops_omap2_dflt_wait,
2283 .parent = &wkup_32k_fck, 2186 .parent = &wkup_32k_fck,
2284 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2187 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2285 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2188 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2286 .flags = CLOCK_IN_OMAP343X,
2287 .clkdm_name = "wkup_clkdm", 2189 .clkdm_name = "wkup_clkdm",
2288 .recalc = &followparent_recalc, 2190 .recalc = &followparent_recalc,
2289}; 2191};
2290 2192
2291static struct clk wdt2_fck = { 2193static struct clk wdt2_fck = {
2292 .name = "wdt2_fck", 2194 .name = "wdt2_fck",
2195 .ops = &clkops_omap2_dflt_wait,
2293 .parent = &wkup_32k_fck, 2196 .parent = &wkup_32k_fck,
2294 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2197 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2295 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2198 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2296 .flags = CLOCK_IN_OMAP343X,
2297 .clkdm_name = "wkup_clkdm", 2199 .clkdm_name = "wkup_clkdm",
2298 .recalc = &followparent_recalc, 2200 .recalc = &followparent_recalc,
2299}; 2201};
2300 2202
2301static struct clk wkup_l4_ick = { 2203static struct clk wkup_l4_ick = {
2302 .name = "wkup_l4_ick", 2204 .name = "wkup_l4_ick",
2205 .ops = &clkops_null,
2303 .parent = &sys_ck, 2206 .parent = &sys_ck,
2304 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2305 .clkdm_name = "wkup_clkdm", 2207 .clkdm_name = "wkup_clkdm",
2306 .recalc = &followparent_recalc, 2208 .recalc = &followparent_recalc,
2307}; 2209};
@@ -2310,50 +2212,50 @@ static struct clk wkup_l4_ick = {
2310/* Never specifically named in the TRM, so we have to infer a likely name */ 2212/* Never specifically named in the TRM, so we have to infer a likely name */
2311static struct clk usim_ick = { 2213static struct clk usim_ick = {
2312 .name = "usim_ick", 2214 .name = "usim_ick",
2215 .ops = &clkops_omap2_dflt_wait,
2313 .parent = &wkup_l4_ick, 2216 .parent = &wkup_l4_ick,
2314 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2217 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2315 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, 2218 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2316 .flags = CLOCK_IN_OMAP3430ES2,
2317 .clkdm_name = "wkup_clkdm", 2219 .clkdm_name = "wkup_clkdm",
2318 .recalc = &followparent_recalc, 2220 .recalc = &followparent_recalc,
2319}; 2221};
2320 2222
2321static struct clk wdt2_ick = { 2223static struct clk wdt2_ick = {
2322 .name = "wdt2_ick", 2224 .name = "wdt2_ick",
2225 .ops = &clkops_omap2_dflt_wait,
2323 .parent = &wkup_l4_ick, 2226 .parent = &wkup_l4_ick,
2324 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2227 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2325 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2228 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2326 .flags = CLOCK_IN_OMAP343X,
2327 .clkdm_name = "wkup_clkdm", 2229 .clkdm_name = "wkup_clkdm",
2328 .recalc = &followparent_recalc, 2230 .recalc = &followparent_recalc,
2329}; 2231};
2330 2232
2331static struct clk wdt1_ick = { 2233static struct clk wdt1_ick = {
2332 .name = "wdt1_ick", 2234 .name = "wdt1_ick",
2235 .ops = &clkops_omap2_dflt_wait,
2333 .parent = &wkup_l4_ick, 2236 .parent = &wkup_l4_ick,
2334 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2237 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2335 .enable_bit = OMAP3430_EN_WDT1_SHIFT, 2238 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2336 .flags = CLOCK_IN_OMAP343X,
2337 .clkdm_name = "wkup_clkdm", 2239 .clkdm_name = "wkup_clkdm",
2338 .recalc = &followparent_recalc, 2240 .recalc = &followparent_recalc,
2339}; 2241};
2340 2242
2341static struct clk gpio1_ick = { 2243static struct clk gpio1_ick = {
2342 .name = "gpio1_ick", 2244 .name = "gpio1_ick",
2245 .ops = &clkops_omap2_dflt_wait,
2343 .parent = &wkup_l4_ick, 2246 .parent = &wkup_l4_ick,
2344 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2247 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2345 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2248 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2346 .flags = CLOCK_IN_OMAP343X,
2347 .clkdm_name = "wkup_clkdm", 2249 .clkdm_name = "wkup_clkdm",
2348 .recalc = &followparent_recalc, 2250 .recalc = &followparent_recalc,
2349}; 2251};
2350 2252
2351static struct clk omap_32ksync_ick = { 2253static struct clk omap_32ksync_ick = {
2352 .name = "omap_32ksync_ick", 2254 .name = "omap_32ksync_ick",
2255 .ops = &clkops_omap2_dflt_wait,
2353 .parent = &wkup_l4_ick, 2256 .parent = &wkup_l4_ick,
2354 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2257 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2355 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, 2258 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2356 .flags = CLOCK_IN_OMAP343X,
2357 .clkdm_name = "wkup_clkdm", 2259 .clkdm_name = "wkup_clkdm",
2358 .recalc = &followparent_recalc, 2260 .recalc = &followparent_recalc,
2359}; 2261};
@@ -2361,20 +2263,20 @@ static struct clk omap_32ksync_ick = {
2361/* XXX This clock no longer exists in 3430 TRM rev F */ 2263/* XXX This clock no longer exists in 3430 TRM rev F */
2362static struct clk gpt12_ick = { 2264static struct clk gpt12_ick = {
2363 .name = "gpt12_ick", 2265 .name = "gpt12_ick",
2266 .ops = &clkops_omap2_dflt_wait,
2364 .parent = &wkup_l4_ick, 2267 .parent = &wkup_l4_ick,
2365 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2268 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2366 .enable_bit = OMAP3430_EN_GPT12_SHIFT, 2269 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2367 .flags = CLOCK_IN_OMAP343X,
2368 .clkdm_name = "wkup_clkdm", 2270 .clkdm_name = "wkup_clkdm",
2369 .recalc = &followparent_recalc, 2271 .recalc = &followparent_recalc,
2370}; 2272};
2371 2273
2372static struct clk gpt1_ick = { 2274static struct clk gpt1_ick = {
2373 .name = "gpt1_ick", 2275 .name = "gpt1_ick",
2276 .ops = &clkops_omap2_dflt_wait,
2374 .parent = &wkup_l4_ick, 2277 .parent = &wkup_l4_ick,
2375 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2278 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2376 .enable_bit = OMAP3430_EN_GPT1_SHIFT, 2279 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2377 .flags = CLOCK_IN_OMAP343X,
2378 .clkdm_name = "wkup_clkdm", 2280 .clkdm_name = "wkup_clkdm",
2379 .recalc = &followparent_recalc, 2281 .recalc = &followparent_recalc,
2380}; 2282};
@@ -2385,406 +2287,404 @@ static struct clk gpt1_ick = {
2385 2287
2386static struct clk per_96m_fck = { 2288static struct clk per_96m_fck = {
2387 .name = "per_96m_fck", 2289 .name = "per_96m_fck",
2290 .ops = &clkops_null,
2388 .parent = &omap_96m_alwon_fck, 2291 .parent = &omap_96m_alwon_fck,
2389 .init = &omap2_init_clk_clkdm, 2292 .init = &omap2_init_clk_clkdm,
2390 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2391 PARENT_CONTROLS_CLOCK,
2392 .clkdm_name = "per_clkdm", 2293 .clkdm_name = "per_clkdm",
2393 .recalc = &followparent_recalc, 2294 .recalc = &followparent_recalc,
2394}; 2295};
2395 2296
2396static struct clk per_48m_fck = { 2297static struct clk per_48m_fck = {
2397 .name = "per_48m_fck", 2298 .name = "per_48m_fck",
2299 .ops = &clkops_null,
2398 .parent = &omap_48m_fck, 2300 .parent = &omap_48m_fck,
2399 .init = &omap2_init_clk_clkdm, 2301 .init = &omap2_init_clk_clkdm,
2400 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2401 PARENT_CONTROLS_CLOCK,
2402 .clkdm_name = "per_clkdm", 2302 .clkdm_name = "per_clkdm",
2403 .recalc = &followparent_recalc, 2303 .recalc = &followparent_recalc,
2404}; 2304};
2405 2305
2406static struct clk uart3_fck = { 2306static struct clk uart3_fck = {
2407 .name = "uart3_fck", 2307 .name = "uart3_fck",
2308 .ops = &clkops_omap2_dflt_wait,
2408 .parent = &per_48m_fck, 2309 .parent = &per_48m_fck,
2409 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2310 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2410 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2311 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2411 .flags = CLOCK_IN_OMAP343X,
2412 .clkdm_name = "per_clkdm", 2312 .clkdm_name = "per_clkdm",
2413 .recalc = &followparent_recalc, 2313 .recalc = &followparent_recalc,
2414}; 2314};
2415 2315
2416static struct clk gpt2_fck = { 2316static struct clk gpt2_fck = {
2417 .name = "gpt2_fck", 2317 .name = "gpt2_fck",
2318 .ops = &clkops_omap2_dflt_wait,
2418 .init = &omap2_init_clksel_parent, 2319 .init = &omap2_init_clksel_parent,
2419 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2320 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2420 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2321 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2421 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2322 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2422 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, 2323 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2423 .clksel = omap343x_gpt_clksel, 2324 .clksel = omap343x_gpt_clksel,
2424 .flags = CLOCK_IN_OMAP343X,
2425 .clkdm_name = "per_clkdm", 2325 .clkdm_name = "per_clkdm",
2426 .recalc = &omap2_clksel_recalc, 2326 .recalc = &omap2_clksel_recalc,
2427}; 2327};
2428 2328
2429static struct clk gpt3_fck = { 2329static struct clk gpt3_fck = {
2430 .name = "gpt3_fck", 2330 .name = "gpt3_fck",
2331 .ops = &clkops_omap2_dflt_wait,
2431 .init = &omap2_init_clksel_parent, 2332 .init = &omap2_init_clksel_parent,
2432 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2333 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2433 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2334 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2434 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2335 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2435 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, 2336 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2436 .clksel = omap343x_gpt_clksel, 2337 .clksel = omap343x_gpt_clksel,
2437 .flags = CLOCK_IN_OMAP343X,
2438 .clkdm_name = "per_clkdm", 2338 .clkdm_name = "per_clkdm",
2439 .recalc = &omap2_clksel_recalc, 2339 .recalc = &omap2_clksel_recalc,
2440}; 2340};
2441 2341
2442static struct clk gpt4_fck = { 2342static struct clk gpt4_fck = {
2443 .name = "gpt4_fck", 2343 .name = "gpt4_fck",
2344 .ops = &clkops_omap2_dflt_wait,
2444 .init = &omap2_init_clksel_parent, 2345 .init = &omap2_init_clksel_parent,
2445 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2346 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2446 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2347 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2447 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2348 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2448 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, 2349 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2449 .clksel = omap343x_gpt_clksel, 2350 .clksel = omap343x_gpt_clksel,
2450 .flags = CLOCK_IN_OMAP343X,
2451 .clkdm_name = "per_clkdm", 2351 .clkdm_name = "per_clkdm",
2452 .recalc = &omap2_clksel_recalc, 2352 .recalc = &omap2_clksel_recalc,
2453}; 2353};
2454 2354
2455static struct clk gpt5_fck = { 2355static struct clk gpt5_fck = {
2456 .name = "gpt5_fck", 2356 .name = "gpt5_fck",
2357 .ops = &clkops_omap2_dflt_wait,
2457 .init = &omap2_init_clksel_parent, 2358 .init = &omap2_init_clksel_parent,
2458 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2359 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2459 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2360 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2460 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2361 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2461 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, 2362 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2462 .clksel = omap343x_gpt_clksel, 2363 .clksel = omap343x_gpt_clksel,
2463 .flags = CLOCK_IN_OMAP343X,
2464 .clkdm_name = "per_clkdm", 2364 .clkdm_name = "per_clkdm",
2465 .recalc = &omap2_clksel_recalc, 2365 .recalc = &omap2_clksel_recalc,
2466}; 2366};
2467 2367
2468static struct clk gpt6_fck = { 2368static struct clk gpt6_fck = {
2469 .name = "gpt6_fck", 2369 .name = "gpt6_fck",
2370 .ops = &clkops_omap2_dflt_wait,
2470 .init = &omap2_init_clksel_parent, 2371 .init = &omap2_init_clksel_parent,
2471 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2372 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2472 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2373 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2473 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2374 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2474 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, 2375 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2475 .clksel = omap343x_gpt_clksel, 2376 .clksel = omap343x_gpt_clksel,
2476 .flags = CLOCK_IN_OMAP343X,
2477 .clkdm_name = "per_clkdm", 2377 .clkdm_name = "per_clkdm",
2478 .recalc = &omap2_clksel_recalc, 2378 .recalc = &omap2_clksel_recalc,
2479}; 2379};
2480 2380
2481static struct clk gpt7_fck = { 2381static struct clk gpt7_fck = {
2482 .name = "gpt7_fck", 2382 .name = "gpt7_fck",
2383 .ops = &clkops_omap2_dflt_wait,
2483 .init = &omap2_init_clksel_parent, 2384 .init = &omap2_init_clksel_parent,
2484 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2385 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2485 .enable_bit = OMAP3430_EN_GPT7_SHIFT, 2386 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2486 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2387 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2487 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, 2388 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2488 .clksel = omap343x_gpt_clksel, 2389 .clksel = omap343x_gpt_clksel,
2489 .flags = CLOCK_IN_OMAP343X,
2490 .clkdm_name = "per_clkdm", 2390 .clkdm_name = "per_clkdm",
2491 .recalc = &omap2_clksel_recalc, 2391 .recalc = &omap2_clksel_recalc,
2492}; 2392};
2493 2393
2494static struct clk gpt8_fck = { 2394static struct clk gpt8_fck = {
2495 .name = "gpt8_fck", 2395 .name = "gpt8_fck",
2396 .ops = &clkops_omap2_dflt_wait,
2496 .init = &omap2_init_clksel_parent, 2397 .init = &omap2_init_clksel_parent,
2497 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2398 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2498 .enable_bit = OMAP3430_EN_GPT8_SHIFT, 2399 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2499 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2400 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2500 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, 2401 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2501 .clksel = omap343x_gpt_clksel, 2402 .clksel = omap343x_gpt_clksel,
2502 .flags = CLOCK_IN_OMAP343X,
2503 .clkdm_name = "per_clkdm", 2403 .clkdm_name = "per_clkdm",
2504 .recalc = &omap2_clksel_recalc, 2404 .recalc = &omap2_clksel_recalc,
2505}; 2405};
2506 2406
2507static struct clk gpt9_fck = { 2407static struct clk gpt9_fck = {
2508 .name = "gpt9_fck", 2408 .name = "gpt9_fck",
2409 .ops = &clkops_omap2_dflt_wait,
2509 .init = &omap2_init_clksel_parent, 2410 .init = &omap2_init_clksel_parent,
2510 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2411 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2511 .enable_bit = OMAP3430_EN_GPT9_SHIFT, 2412 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2512 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2413 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2513 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, 2414 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2514 .clksel = omap343x_gpt_clksel, 2415 .clksel = omap343x_gpt_clksel,
2515 .flags = CLOCK_IN_OMAP343X,
2516 .clkdm_name = "per_clkdm", 2416 .clkdm_name = "per_clkdm",
2517 .recalc = &omap2_clksel_recalc, 2417 .recalc = &omap2_clksel_recalc,
2518}; 2418};
2519 2419
2520static struct clk per_32k_alwon_fck = { 2420static struct clk per_32k_alwon_fck = {
2521 .name = "per_32k_alwon_fck", 2421 .name = "per_32k_alwon_fck",
2422 .ops = &clkops_null,
2522 .parent = &omap_32k_fck, 2423 .parent = &omap_32k_fck,
2523 .clkdm_name = "per_clkdm", 2424 .clkdm_name = "per_clkdm",
2524 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2525 .recalc = &followparent_recalc, 2425 .recalc = &followparent_recalc,
2526}; 2426};
2527 2427
2528static struct clk gpio6_dbck = { 2428static struct clk gpio6_dbck = {
2529 .name = "gpio6_dbck", 2429 .name = "gpio6_dbck",
2430 .ops = &clkops_omap2_dflt_wait,
2530 .parent = &per_32k_alwon_fck, 2431 .parent = &per_32k_alwon_fck,
2531 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2432 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2532 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2433 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2533 .flags = CLOCK_IN_OMAP343X,
2534 .clkdm_name = "per_clkdm", 2434 .clkdm_name = "per_clkdm",
2535 .recalc = &followparent_recalc, 2435 .recalc = &followparent_recalc,
2536}; 2436};
2537 2437
2538static struct clk gpio5_dbck = { 2438static struct clk gpio5_dbck = {
2539 .name = "gpio5_dbck", 2439 .name = "gpio5_dbck",
2440 .ops = &clkops_omap2_dflt_wait,
2540 .parent = &per_32k_alwon_fck, 2441 .parent = &per_32k_alwon_fck,
2541 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2442 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2542 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2443 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2543 .flags = CLOCK_IN_OMAP343X,
2544 .clkdm_name = "per_clkdm", 2444 .clkdm_name = "per_clkdm",
2545 .recalc = &followparent_recalc, 2445 .recalc = &followparent_recalc,
2546}; 2446};
2547 2447
2548static struct clk gpio4_dbck = { 2448static struct clk gpio4_dbck = {
2549 .name = "gpio4_dbck", 2449 .name = "gpio4_dbck",
2450 .ops = &clkops_omap2_dflt_wait,
2550 .parent = &per_32k_alwon_fck, 2451 .parent = &per_32k_alwon_fck,
2551 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2452 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2552 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2453 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2553 .flags = CLOCK_IN_OMAP343X,
2554 .clkdm_name = "per_clkdm", 2454 .clkdm_name = "per_clkdm",
2555 .recalc = &followparent_recalc, 2455 .recalc = &followparent_recalc,
2556}; 2456};
2557 2457
2558static struct clk gpio3_dbck = { 2458static struct clk gpio3_dbck = {
2559 .name = "gpio3_dbck", 2459 .name = "gpio3_dbck",
2460 .ops = &clkops_omap2_dflt_wait,
2560 .parent = &per_32k_alwon_fck, 2461 .parent = &per_32k_alwon_fck,
2561 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2462 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2562 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2463 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2563 .flags = CLOCK_IN_OMAP343X,
2564 .clkdm_name = "per_clkdm", 2464 .clkdm_name = "per_clkdm",
2565 .recalc = &followparent_recalc, 2465 .recalc = &followparent_recalc,
2566}; 2466};
2567 2467
2568static struct clk gpio2_dbck = { 2468static struct clk gpio2_dbck = {
2569 .name = "gpio2_dbck", 2469 .name = "gpio2_dbck",
2470 .ops = &clkops_omap2_dflt_wait,
2570 .parent = &per_32k_alwon_fck, 2471 .parent = &per_32k_alwon_fck,
2571 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2472 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2572 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2473 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2573 .flags = CLOCK_IN_OMAP343X,
2574 .clkdm_name = "per_clkdm", 2474 .clkdm_name = "per_clkdm",
2575 .recalc = &followparent_recalc, 2475 .recalc = &followparent_recalc,
2576}; 2476};
2577 2477
2578static struct clk wdt3_fck = { 2478static struct clk wdt3_fck = {
2579 .name = "wdt3_fck", 2479 .name = "wdt3_fck",
2480 .ops = &clkops_omap2_dflt_wait,
2580 .parent = &per_32k_alwon_fck, 2481 .parent = &per_32k_alwon_fck,
2581 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2482 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2582 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2483 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2583 .flags = CLOCK_IN_OMAP343X,
2584 .clkdm_name = "per_clkdm", 2484 .clkdm_name = "per_clkdm",
2585 .recalc = &followparent_recalc, 2485 .recalc = &followparent_recalc,
2586}; 2486};
2587 2487
2588static struct clk per_l4_ick = { 2488static struct clk per_l4_ick = {
2589 .name = "per_l4_ick", 2489 .name = "per_l4_ick",
2490 .ops = &clkops_null,
2590 .parent = &l4_ick, 2491 .parent = &l4_ick,
2591 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2592 PARENT_CONTROLS_CLOCK,
2593 .clkdm_name = "per_clkdm", 2492 .clkdm_name = "per_clkdm",
2594 .recalc = &followparent_recalc, 2493 .recalc = &followparent_recalc,
2595}; 2494};
2596 2495
2597static struct clk gpio6_ick = { 2496static struct clk gpio6_ick = {
2598 .name = "gpio6_ick", 2497 .name = "gpio6_ick",
2498 .ops = &clkops_omap2_dflt_wait,
2599 .parent = &per_l4_ick, 2499 .parent = &per_l4_ick,
2600 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2500 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2601 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2501 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2602 .flags = CLOCK_IN_OMAP343X,
2603 .clkdm_name = "per_clkdm", 2502 .clkdm_name = "per_clkdm",
2604 .recalc = &followparent_recalc, 2503 .recalc = &followparent_recalc,
2605}; 2504};
2606 2505
2607static struct clk gpio5_ick = { 2506static struct clk gpio5_ick = {
2608 .name = "gpio5_ick", 2507 .name = "gpio5_ick",
2508 .ops = &clkops_omap2_dflt_wait,
2609 .parent = &per_l4_ick, 2509 .parent = &per_l4_ick,
2610 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2510 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2611 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2511 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2612 .flags = CLOCK_IN_OMAP343X,
2613 .clkdm_name = "per_clkdm", 2512 .clkdm_name = "per_clkdm",
2614 .recalc = &followparent_recalc, 2513 .recalc = &followparent_recalc,
2615}; 2514};
2616 2515
2617static struct clk gpio4_ick = { 2516static struct clk gpio4_ick = {
2618 .name = "gpio4_ick", 2517 .name = "gpio4_ick",
2518 .ops = &clkops_omap2_dflt_wait,
2619 .parent = &per_l4_ick, 2519 .parent = &per_l4_ick,
2620 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2520 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2621 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2521 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2622 .flags = CLOCK_IN_OMAP343X,
2623 .clkdm_name = "per_clkdm", 2522 .clkdm_name = "per_clkdm",
2624 .recalc = &followparent_recalc, 2523 .recalc = &followparent_recalc,
2625}; 2524};
2626 2525
2627static struct clk gpio3_ick = { 2526static struct clk gpio3_ick = {
2628 .name = "gpio3_ick", 2527 .name = "gpio3_ick",
2528 .ops = &clkops_omap2_dflt_wait,
2629 .parent = &per_l4_ick, 2529 .parent = &per_l4_ick,
2630 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2530 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2631 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2531 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2632 .flags = CLOCK_IN_OMAP343X,
2633 .clkdm_name = "per_clkdm", 2532 .clkdm_name = "per_clkdm",
2634 .recalc = &followparent_recalc, 2533 .recalc = &followparent_recalc,
2635}; 2534};
2636 2535
2637static struct clk gpio2_ick = { 2536static struct clk gpio2_ick = {
2638 .name = "gpio2_ick", 2537 .name = "gpio2_ick",
2538 .ops = &clkops_omap2_dflt_wait,
2639 .parent = &per_l4_ick, 2539 .parent = &per_l4_ick,
2640 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2540 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2641 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2541 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2642 .flags = CLOCK_IN_OMAP343X,
2643 .clkdm_name = "per_clkdm", 2542 .clkdm_name = "per_clkdm",
2644 .recalc = &followparent_recalc, 2543 .recalc = &followparent_recalc,
2645}; 2544};
2646 2545
2647static struct clk wdt3_ick = { 2546static struct clk wdt3_ick = {
2648 .name = "wdt3_ick", 2547 .name = "wdt3_ick",
2548 .ops = &clkops_omap2_dflt_wait,
2649 .parent = &per_l4_ick, 2549 .parent = &per_l4_ick,
2650 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2550 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2651 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2551 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2652 .flags = CLOCK_IN_OMAP343X,
2653 .clkdm_name = "per_clkdm", 2552 .clkdm_name = "per_clkdm",
2654 .recalc = &followparent_recalc, 2553 .recalc = &followparent_recalc,
2655}; 2554};
2656 2555
2657static struct clk uart3_ick = { 2556static struct clk uart3_ick = {
2658 .name = "uart3_ick", 2557 .name = "uart3_ick",
2558 .ops = &clkops_omap2_dflt_wait,
2659 .parent = &per_l4_ick, 2559 .parent = &per_l4_ick,
2660 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2560 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2661 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2561 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2662 .flags = CLOCK_IN_OMAP343X,
2663 .clkdm_name = "per_clkdm", 2562 .clkdm_name = "per_clkdm",
2664 .recalc = &followparent_recalc, 2563 .recalc = &followparent_recalc,
2665}; 2564};
2666 2565
2667static struct clk gpt9_ick = { 2566static struct clk gpt9_ick = {
2668 .name = "gpt9_ick", 2567 .name = "gpt9_ick",
2568 .ops = &clkops_omap2_dflt_wait,
2669 .parent = &per_l4_ick, 2569 .parent = &per_l4_ick,
2670 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2570 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2671 .enable_bit = OMAP3430_EN_GPT9_SHIFT, 2571 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2672 .flags = CLOCK_IN_OMAP343X,
2673 .clkdm_name = "per_clkdm", 2572 .clkdm_name = "per_clkdm",
2674 .recalc = &followparent_recalc, 2573 .recalc = &followparent_recalc,
2675}; 2574};
2676 2575
2677static struct clk gpt8_ick = { 2576static struct clk gpt8_ick = {
2678 .name = "gpt8_ick", 2577 .name = "gpt8_ick",
2578 .ops = &clkops_omap2_dflt_wait,
2679 .parent = &per_l4_ick, 2579 .parent = &per_l4_ick,
2680 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2580 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2681 .enable_bit = OMAP3430_EN_GPT8_SHIFT, 2581 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2682 .flags = CLOCK_IN_OMAP343X,
2683 .clkdm_name = "per_clkdm", 2582 .clkdm_name = "per_clkdm",
2684 .recalc = &followparent_recalc, 2583 .recalc = &followparent_recalc,
2685}; 2584};
2686 2585
2687static struct clk gpt7_ick = { 2586static struct clk gpt7_ick = {
2688 .name = "gpt7_ick", 2587 .name = "gpt7_ick",
2588 .ops = &clkops_omap2_dflt_wait,
2689 .parent = &per_l4_ick, 2589 .parent = &per_l4_ick,
2690 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2590 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2691 .enable_bit = OMAP3430_EN_GPT7_SHIFT, 2591 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2692 .flags = CLOCK_IN_OMAP343X,
2693 .clkdm_name = "per_clkdm", 2592 .clkdm_name = "per_clkdm",
2694 .recalc = &followparent_recalc, 2593 .recalc = &followparent_recalc,
2695}; 2594};
2696 2595
2697static struct clk gpt6_ick = { 2596static struct clk gpt6_ick = {
2698 .name = "gpt6_ick", 2597 .name = "gpt6_ick",
2598 .ops = &clkops_omap2_dflt_wait,
2699 .parent = &per_l4_ick, 2599 .parent = &per_l4_ick,
2700 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2600 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2701 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2601 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2702 .flags = CLOCK_IN_OMAP343X,
2703 .clkdm_name = "per_clkdm", 2602 .clkdm_name = "per_clkdm",
2704 .recalc = &followparent_recalc, 2603 .recalc = &followparent_recalc,
2705}; 2604};
2706 2605
2707static struct clk gpt5_ick = { 2606static struct clk gpt5_ick = {
2708 .name = "gpt5_ick", 2607 .name = "gpt5_ick",
2608 .ops = &clkops_omap2_dflt_wait,
2709 .parent = &per_l4_ick, 2609 .parent = &per_l4_ick,
2710 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2610 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2711 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2611 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2712 .flags = CLOCK_IN_OMAP343X,
2713 .clkdm_name = "per_clkdm", 2612 .clkdm_name = "per_clkdm",
2714 .recalc = &followparent_recalc, 2613 .recalc = &followparent_recalc,
2715}; 2614};
2716 2615
2717static struct clk gpt4_ick = { 2616static struct clk gpt4_ick = {
2718 .name = "gpt4_ick", 2617 .name = "gpt4_ick",
2618 .ops = &clkops_omap2_dflt_wait,
2719 .parent = &per_l4_ick, 2619 .parent = &per_l4_ick,
2720 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2620 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2721 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2621 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2722 .flags = CLOCK_IN_OMAP343X,
2723 .clkdm_name = "per_clkdm", 2622 .clkdm_name = "per_clkdm",
2724 .recalc = &followparent_recalc, 2623 .recalc = &followparent_recalc,
2725}; 2624};
2726 2625
2727static struct clk gpt3_ick = { 2626static struct clk gpt3_ick = {
2728 .name = "gpt3_ick", 2627 .name = "gpt3_ick",
2628 .ops = &clkops_omap2_dflt_wait,
2729 .parent = &per_l4_ick, 2629 .parent = &per_l4_ick,
2730 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2630 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2731 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2631 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2732 .flags = CLOCK_IN_OMAP343X,
2733 .clkdm_name = "per_clkdm", 2632 .clkdm_name = "per_clkdm",
2734 .recalc = &followparent_recalc, 2633 .recalc = &followparent_recalc,
2735}; 2634};
2736 2635
2737static struct clk gpt2_ick = { 2636static struct clk gpt2_ick = {
2738 .name = "gpt2_ick", 2637 .name = "gpt2_ick",
2638 .ops = &clkops_omap2_dflt_wait,
2739 .parent = &per_l4_ick, 2639 .parent = &per_l4_ick,
2740 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2640 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2741 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2641 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2742 .flags = CLOCK_IN_OMAP343X,
2743 .clkdm_name = "per_clkdm", 2642 .clkdm_name = "per_clkdm",
2744 .recalc = &followparent_recalc, 2643 .recalc = &followparent_recalc,
2745}; 2644};
2746 2645
2747static struct clk mcbsp2_ick = { 2646static struct clk mcbsp2_ick = {
2748 .name = "mcbsp_ick", 2647 .name = "mcbsp_ick",
2648 .ops = &clkops_omap2_dflt_wait,
2749 .id = 2, 2649 .id = 2,
2750 .parent = &per_l4_ick, 2650 .parent = &per_l4_ick,
2751 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2651 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2752 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, 2652 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2753 .flags = CLOCK_IN_OMAP343X,
2754 .clkdm_name = "per_clkdm", 2653 .clkdm_name = "per_clkdm",
2755 .recalc = &followparent_recalc, 2654 .recalc = &followparent_recalc,
2756}; 2655};
2757 2656
2758static struct clk mcbsp3_ick = { 2657static struct clk mcbsp3_ick = {
2759 .name = "mcbsp_ick", 2658 .name = "mcbsp_ick",
2659 .ops = &clkops_omap2_dflt_wait,
2760 .id = 3, 2660 .id = 3,
2761 .parent = &per_l4_ick, 2661 .parent = &per_l4_ick,
2762 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2662 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2763 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, 2663 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2764 .flags = CLOCK_IN_OMAP343X,
2765 .clkdm_name = "per_clkdm", 2664 .clkdm_name = "per_clkdm",
2766 .recalc = &followparent_recalc, 2665 .recalc = &followparent_recalc,
2767}; 2666};
2768 2667
2769static struct clk mcbsp4_ick = { 2668static struct clk mcbsp4_ick = {
2770 .name = "mcbsp_ick", 2669 .name = "mcbsp_ick",
2670 .ops = &clkops_omap2_dflt_wait,
2771 .id = 4, 2671 .id = 4,
2772 .parent = &per_l4_ick, 2672 .parent = &per_l4_ick,
2773 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2673 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2774 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, 2674 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2775 .flags = CLOCK_IN_OMAP343X,
2776 .clkdm_name = "per_clkdm", 2675 .clkdm_name = "per_clkdm",
2777 .recalc = &followparent_recalc, 2676 .recalc = &followparent_recalc,
2778}; 2677};
2779 2678
2780static const struct clksel mcbsp_234_clksel[] = { 2679static const struct clksel mcbsp_234_clksel[] = {
2781 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, 2680 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2782 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, 2681 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2783 { .parent = NULL } 2682 { .parent = NULL }
2784}; 2683};
2785 2684
2786static struct clk mcbsp2_fck = { 2685static struct clk mcbsp2_fck = {
2787 .name = "mcbsp_fck", 2686 .name = "mcbsp_fck",
2687 .ops = &clkops_omap2_dflt_wait,
2788 .id = 2, 2688 .id = 2,
2789 .init = &omap2_init_clksel_parent, 2689 .init = &omap2_init_clksel_parent,
2790 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2690 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
@@ -2792,13 +2692,13 @@ static struct clk mcbsp2_fck = {
2792 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), 2692 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2793 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, 2693 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2794 .clksel = mcbsp_234_clksel, 2694 .clksel = mcbsp_234_clksel,
2795 .flags = CLOCK_IN_OMAP343X,
2796 .clkdm_name = "per_clkdm", 2695 .clkdm_name = "per_clkdm",
2797 .recalc = &omap2_clksel_recalc, 2696 .recalc = &omap2_clksel_recalc,
2798}; 2697};
2799 2698
2800static struct clk mcbsp3_fck = { 2699static struct clk mcbsp3_fck = {
2801 .name = "mcbsp_fck", 2700 .name = "mcbsp_fck",
2701 .ops = &clkops_omap2_dflt_wait,
2802 .id = 3, 2702 .id = 3,
2803 .init = &omap2_init_clksel_parent, 2703 .init = &omap2_init_clksel_parent,
2804 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2704 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
@@ -2806,13 +2706,13 @@ static struct clk mcbsp3_fck = {
2806 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), 2706 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2807 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, 2707 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2808 .clksel = mcbsp_234_clksel, 2708 .clksel = mcbsp_234_clksel,
2809 .flags = CLOCK_IN_OMAP343X,
2810 .clkdm_name = "per_clkdm", 2709 .clkdm_name = "per_clkdm",
2811 .recalc = &omap2_clksel_recalc, 2710 .recalc = &omap2_clksel_recalc,
2812}; 2711};
2813 2712
2814static struct clk mcbsp4_fck = { 2713static struct clk mcbsp4_fck = {
2815 .name = "mcbsp_fck", 2714 .name = "mcbsp_fck",
2715 .ops = &clkops_omap2_dflt_wait,
2816 .id = 4, 2716 .id = 4,
2817 .init = &omap2_init_clksel_parent, 2717 .init = &omap2_init_clksel_parent,
2818 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2718 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
@@ -2820,7 +2720,6 @@ static struct clk mcbsp4_fck = {
2820 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), 2720 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2821 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, 2721 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2822 .clksel = mcbsp_234_clksel, 2722 .clksel = mcbsp_234_clksel,
2823 .flags = CLOCK_IN_OMAP343X,
2824 .clkdm_name = "per_clkdm", 2723 .clkdm_name = "per_clkdm",
2825 .recalc = &omap2_clksel_recalc, 2724 .recalc = &omap2_clksel_recalc,
2826}; 2725};
@@ -2864,11 +2763,11 @@ static const struct clksel emu_src_clksel[] = {
2864 */ 2763 */
2865static struct clk emu_src_ck = { 2764static struct clk emu_src_ck = {
2866 .name = "emu_src_ck", 2765 .name = "emu_src_ck",
2766 .ops = &clkops_null,
2867 .init = &omap2_init_clksel_parent, 2767 .init = &omap2_init_clksel_parent,
2868 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2768 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2869 .clksel_mask = OMAP3430_MUX_CTRL_MASK, 2769 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2870 .clksel = emu_src_clksel, 2770 .clksel = emu_src_clksel,
2871 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2872 .clkdm_name = "emu_clkdm", 2771 .clkdm_name = "emu_clkdm",
2873 .recalc = &omap2_clksel_recalc, 2772 .recalc = &omap2_clksel_recalc,
2874}; 2773};
@@ -2888,11 +2787,11 @@ static const struct clksel pclk_emu_clksel[] = {
2888 2787
2889static struct clk pclk_fck = { 2788static struct clk pclk_fck = {
2890 .name = "pclk_fck", 2789 .name = "pclk_fck",
2790 .ops = &clkops_null,
2891 .init = &omap2_init_clksel_parent, 2791 .init = &omap2_init_clksel_parent,
2892 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2792 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2893 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, 2793 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2894 .clksel = pclk_emu_clksel, 2794 .clksel = pclk_emu_clksel,
2895 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2896 .clkdm_name = "emu_clkdm", 2795 .clkdm_name = "emu_clkdm",
2897 .recalc = &omap2_clksel_recalc, 2796 .recalc = &omap2_clksel_recalc,
2898}; 2797};
@@ -2911,11 +2810,11 @@ static const struct clksel pclkx2_emu_clksel[] = {
2911 2810
2912static struct clk pclkx2_fck = { 2811static struct clk pclkx2_fck = {
2913 .name = "pclkx2_fck", 2812 .name = "pclkx2_fck",
2813 .ops = &clkops_null,
2914 .init = &omap2_init_clksel_parent, 2814 .init = &omap2_init_clksel_parent,
2915 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2815 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2916 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, 2816 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2917 .clksel = pclkx2_emu_clksel, 2817 .clksel = pclkx2_emu_clksel,
2918 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2919 .clkdm_name = "emu_clkdm", 2818 .clkdm_name = "emu_clkdm",
2920 .recalc = &omap2_clksel_recalc, 2819 .recalc = &omap2_clksel_recalc,
2921}; 2820};
@@ -2927,22 +2826,22 @@ static const struct clksel atclk_emu_clksel[] = {
2927 2826
2928static struct clk atclk_fck = { 2827static struct clk atclk_fck = {
2929 .name = "atclk_fck", 2828 .name = "atclk_fck",
2829 .ops = &clkops_null,
2930 .init = &omap2_init_clksel_parent, 2830 .init = &omap2_init_clksel_parent,
2931 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2831 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2932 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, 2832 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2933 .clksel = atclk_emu_clksel, 2833 .clksel = atclk_emu_clksel,
2934 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2935 .clkdm_name = "emu_clkdm", 2834 .clkdm_name = "emu_clkdm",
2936 .recalc = &omap2_clksel_recalc, 2835 .recalc = &omap2_clksel_recalc,
2937}; 2836};
2938 2837
2939static struct clk traceclk_src_fck = { 2838static struct clk traceclk_src_fck = {
2940 .name = "traceclk_src_fck", 2839 .name = "traceclk_src_fck",
2840 .ops = &clkops_null,
2941 .init = &omap2_init_clksel_parent, 2841 .init = &omap2_init_clksel_parent,
2942 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2842 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2943 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, 2843 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2944 .clksel = emu_src_clksel, 2844 .clksel = emu_src_clksel,
2945 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2946 .clkdm_name = "emu_clkdm", 2845 .clkdm_name = "emu_clkdm",
2947 .recalc = &omap2_clksel_recalc, 2846 .recalc = &omap2_clksel_recalc,
2948}; 2847};
@@ -2961,11 +2860,11 @@ static const struct clksel traceclk_clksel[] = {
2961 2860
2962static struct clk traceclk_fck = { 2861static struct clk traceclk_fck = {
2963 .name = "traceclk_fck", 2862 .name = "traceclk_fck",
2863 .ops = &clkops_null,
2964 .init = &omap2_init_clksel_parent, 2864 .init = &omap2_init_clksel_parent,
2965 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2865 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2966 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, 2866 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2967 .clksel = traceclk_clksel, 2867 .clksel = traceclk_clksel,
2968 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2969 .clkdm_name = "emu_clkdm", 2868 .clkdm_name = "emu_clkdm",
2970 .recalc = &omap2_clksel_recalc, 2869 .recalc = &omap2_clksel_recalc,
2971}; 2870};
@@ -2975,27 +2874,27 @@ static struct clk traceclk_fck = {
2975/* SmartReflex fclk (VDD1) */ 2874/* SmartReflex fclk (VDD1) */
2976static struct clk sr1_fck = { 2875static struct clk sr1_fck = {
2977 .name = "sr1_fck", 2876 .name = "sr1_fck",
2877 .ops = &clkops_omap2_dflt_wait,
2978 .parent = &sys_ck, 2878 .parent = &sys_ck,
2979 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2879 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2980 .enable_bit = OMAP3430_EN_SR1_SHIFT, 2880 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2981 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2982 .recalc = &followparent_recalc, 2881 .recalc = &followparent_recalc,
2983}; 2882};
2984 2883
2985/* SmartReflex fclk (VDD2) */ 2884/* SmartReflex fclk (VDD2) */
2986static struct clk sr2_fck = { 2885static struct clk sr2_fck = {
2987 .name = "sr2_fck", 2886 .name = "sr2_fck",
2887 .ops = &clkops_omap2_dflt_wait,
2988 .parent = &sys_ck, 2888 .parent = &sys_ck,
2989 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2889 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2990 .enable_bit = OMAP3430_EN_SR2_SHIFT, 2890 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2991 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2992 .recalc = &followparent_recalc, 2891 .recalc = &followparent_recalc,
2993}; 2892};
2994 2893
2995static struct clk sr_l4_ick = { 2894static struct clk sr_l4_ick = {
2996 .name = "sr_l4_ick", 2895 .name = "sr_l4_ick",
2896 .ops = &clkops_null, /* RMK: missing? */
2997 .parent = &l4_ick, 2897 .parent = &l4_ick,
2998 .flags = CLOCK_IN_OMAP343X,
2999 .clkdm_name = "core_l4_clkdm", 2898 .clkdm_name = "core_l4_clkdm",
3000 .recalc = &followparent_recalc, 2899 .recalc = &followparent_recalc,
3001}; 2900};
@@ -3005,231 +2904,16 @@ static struct clk sr_l4_ick = {
3005/* XXX This clock no longer exists in 3430 TRM rev F */ 2904/* XXX This clock no longer exists in 3430 TRM rev F */
3006static struct clk gpt12_fck = { 2905static struct clk gpt12_fck = {
3007 .name = "gpt12_fck", 2906 .name = "gpt12_fck",
2907 .ops = &clkops_null,
3008 .parent = &secure_32k_fck, 2908 .parent = &secure_32k_fck,
3009 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3010 .recalc = &followparent_recalc, 2909 .recalc = &followparent_recalc,
3011}; 2910};
3012 2911
3013static struct clk wdt1_fck = { 2912static struct clk wdt1_fck = {
3014 .name = "wdt1_fck", 2913 .name = "wdt1_fck",
2914 .ops = &clkops_null,
3015 .parent = &secure_32k_fck, 2915 .parent = &secure_32k_fck,
3016 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, 2916 .recalc = &followparent_recalc,
3017 .recalc = &followparent_recalc,
3018};
3019
3020static struct clk *onchip_34xx_clks[] __initdata = {
3021 &omap_32k_fck,
3022 &virt_12m_ck,
3023 &virt_13m_ck,
3024 &virt_16_8m_ck,
3025 &virt_19_2m_ck,
3026 &virt_26m_ck,
3027 &virt_38_4m_ck,
3028 &osc_sys_ck,
3029 &sys_ck,
3030 &sys_altclk,
3031 &mcbsp_clks,
3032 &sys_clkout1,
3033 &dpll1_ck,
3034 &dpll1_x2_ck,
3035 &dpll1_x2m2_ck,
3036 &dpll2_ck,
3037 &dpll2_m2_ck,
3038 &dpll3_ck,
3039 &core_ck,
3040 &dpll3_x2_ck,
3041 &dpll3_m2_ck,
3042 &dpll3_m2x2_ck,
3043 &dpll3_m3_ck,
3044 &dpll3_m3x2_ck,
3045 &emu_core_alwon_ck,
3046 &dpll4_ck,
3047 &dpll4_x2_ck,
3048 &omap_96m_alwon_fck,
3049 &omap_96m_fck,
3050 &cm_96m_fck,
3051 &virt_omap_54m_fck,
3052 &omap_54m_fck,
3053 &omap_48m_fck,
3054 &omap_12m_fck,
3055 &dpll4_m2_ck,
3056 &dpll4_m2x2_ck,
3057 &dpll4_m3_ck,
3058 &dpll4_m3x2_ck,
3059 &dpll4_m4_ck,
3060 &dpll4_m4x2_ck,
3061 &dpll4_m5_ck,
3062 &dpll4_m5x2_ck,
3063 &dpll4_m6_ck,
3064 &dpll4_m6x2_ck,
3065 &emu_per_alwon_ck,
3066 &dpll5_ck,
3067 &dpll5_m2_ck,
3068 &omap_120m_fck,
3069 &clkout2_src_ck,
3070 &sys_clkout2,
3071 &corex2_fck,
3072 &dpll1_fck,
3073 &mpu_ck,
3074 &arm_fck,
3075 &emu_mpu_alwon_ck,
3076 &dpll2_fck,
3077 &iva2_ck,
3078 &l3_ick,
3079 &l4_ick,
3080 &rm_ick,
3081 &gfx_l3_ck,
3082 &gfx_l3_fck,
3083 &gfx_l3_ick,
3084 &gfx_cg1_ck,
3085 &gfx_cg2_ck,
3086 &sgx_fck,
3087 &sgx_ick,
3088 &d2d_26m_fck,
3089 &gpt10_fck,
3090 &gpt11_fck,
3091 &cpefuse_fck,
3092 &ts_fck,
3093 &usbtll_fck,
3094 &core_96m_fck,
3095 &mmchs3_fck,
3096 &mmchs2_fck,
3097 &mspro_fck,
3098 &mmchs1_fck,
3099 &i2c3_fck,
3100 &i2c2_fck,
3101 &i2c1_fck,
3102 &mcbsp5_fck,
3103 &mcbsp1_fck,
3104 &core_48m_fck,
3105 &mcspi4_fck,
3106 &mcspi3_fck,
3107 &mcspi2_fck,
3108 &mcspi1_fck,
3109 &uart2_fck,
3110 &uart1_fck,
3111 &fshostusb_fck,
3112 &core_12m_fck,
3113 &hdq_fck,
3114 &ssi_ssr_fck,
3115 &ssi_sst_fck,
3116 &core_l3_ick,
3117 &hsotgusb_ick,
3118 &sdrc_ick,
3119 &gpmc_fck,
3120 &security_l3_ick,
3121 &pka_ick,
3122 &core_l4_ick,
3123 &usbtll_ick,
3124 &mmchs3_ick,
3125 &icr_ick,
3126 &aes2_ick,
3127 &sha12_ick,
3128 &des2_ick,
3129 &mmchs2_ick,
3130 &mmchs1_ick,
3131 &mspro_ick,
3132 &hdq_ick,
3133 &mcspi4_ick,
3134 &mcspi3_ick,
3135 &mcspi2_ick,
3136 &mcspi1_ick,
3137 &i2c3_ick,
3138 &i2c2_ick,
3139 &i2c1_ick,
3140 &uart2_ick,
3141 &uart1_ick,
3142 &gpt11_ick,
3143 &gpt10_ick,
3144 &mcbsp5_ick,
3145 &mcbsp1_ick,
3146 &fac_ick,
3147 &mailboxes_ick,
3148 &omapctrl_ick,
3149 &ssi_l4_ick,
3150 &ssi_ick,
3151 &usb_l4_ick,
3152 &security_l4_ick2,
3153 &aes1_ick,
3154 &rng_ick,
3155 &sha11_ick,
3156 &des1_ick,
3157 &dss1_alwon_fck,
3158 &dss_tv_fck,
3159 &dss_96m_fck,
3160 &dss2_alwon_fck,
3161 &dss_ick,
3162 &cam_mclk,
3163 &cam_ick,
3164 &usbhost_120m_fck,
3165 &usbhost_48m_fck,
3166 &usbhost_ick,
3167 &usbhost_sar_fck,
3168 &usim_fck,
3169 &gpt1_fck,
3170 &wkup_32k_fck,
3171 &gpio1_dbck,
3172 &wdt2_fck,
3173 &wkup_l4_ick,
3174 &usim_ick,
3175 &wdt2_ick,
3176 &wdt1_ick,
3177 &gpio1_ick,
3178 &omap_32ksync_ick,
3179 &gpt12_ick,
3180 &gpt1_ick,
3181 &per_96m_fck,
3182 &per_48m_fck,
3183 &uart3_fck,
3184 &gpt2_fck,
3185 &gpt3_fck,
3186 &gpt4_fck,
3187 &gpt5_fck,
3188 &gpt6_fck,
3189 &gpt7_fck,
3190 &gpt8_fck,
3191 &gpt9_fck,
3192 &per_32k_alwon_fck,
3193 &gpio6_dbck,
3194 &gpio5_dbck,
3195 &gpio4_dbck,
3196 &gpio3_dbck,
3197 &gpio2_dbck,
3198 &wdt3_fck,
3199 &per_l4_ick,
3200 &gpio6_ick,
3201 &gpio5_ick,
3202 &gpio4_ick,
3203 &gpio3_ick,
3204 &gpio2_ick,
3205 &wdt3_ick,
3206 &uart3_ick,
3207 &gpt9_ick,
3208 &gpt8_ick,
3209 &gpt7_ick,
3210 &gpt6_ick,
3211 &gpt5_ick,
3212 &gpt4_ick,
3213 &gpt3_ick,
3214 &gpt2_ick,
3215 &mcbsp2_ick,
3216 &mcbsp3_ick,
3217 &mcbsp4_ick,
3218 &mcbsp2_fck,
3219 &mcbsp3_fck,
3220 &mcbsp4_fck,
3221 &emu_src_ck,
3222 &pclk_fck,
3223 &pclkx2_fck,
3224 &atclk_fck,
3225 &traceclk_src_fck,
3226 &traceclk_fck,
3227 &sr1_fck,
3228 &sr2_fck,
3229 &sr_l4_ick,
3230 &secure_32k_fck,
3231 &gpt12_fck,
3232 &wdt1_fck,
3233}; 2917};
3234 2918
3235#endif 2919#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 04:04:04 -0500