1 files changed, 64 insertions, 19 deletions

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 73624dc04c97..e349d48ee807 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1,14 +1,19 @@
 /*
  * OMAP3 clock framework
  *
- * Virtual clocks are introduced as a convenient tools.
- * They are sources for other clocks and not supposed
- * to be requested from drivers directly.
- *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
  * Copyright (C) 2007-2008 Nokia Corporation
  *
  * Written by Paul Walmsley
+ * With many device clock fixes by Kevin Hilman and Jouni Högander
+ * DPLL bypass clock support added by Roman Tereshonkov
+ *
+ */
+
+/*
+ * Virtual clocks are introduced as convenient tools.
+ * They are sources for other clocks and not supposed
+ * to be requested from drivers directly.
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
@@ -24,6 +29,11 @@
 
 static void omap3_dpll_recalc(struct clk *clk);
 static void omap3_clkoutx2_recalc(struct clk *clk);
+static void omap3_dpll_allow_idle(struct clk *clk);
+static void omap3_dpll_deny_idle(struct clk *clk);
+static u32 omap3_dpll_autoidle_read(struct clk *clk);
+static int omap3_noncore_dpll_enable(struct clk *clk);
+static void omap3_noncore_dpll_disable(struct clk *clk);
 
 /*
  * DPLL1 supplies clock to the MPU.
@@ -33,6 +43,11 @@ static void omap3_clkoutx2_recalc(struct clk *clk);
  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  */
 
+/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
+#define DPLL_LOW_POWER_STOP             0x1
+#define DPLL_LOW_POWER_BYPASS           0x5
+#define DPLL_LOCKED                     0x7
+
 /* PRM CLOCKS */
 
 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
@@ -246,9 +261,14 @@ static const struct dpll_data dpll1_dd = {
         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+        .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .idlest_bit     = OMAP3430_ST_MPU_CLK_SHIFT,
 };
 
 static struct clk dpll1_ck = {
@@ -303,16 +323,24 @@ static const struct dpll_data dpll2_dd = {
         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
+                                (1 << DPLL_LOW_POWER_BYPASS),
         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+        .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
+        .idlest_bit     = OMAP3430_ST_IVA2_CLK_SHIFT
 };
 
 static struct clk dpll2_ck = {
         .name           = "dpll2_ck",
         .parent         = &sys_ck,
         .dpll_data      = &dpll2_dd,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -338,9 +366,11 @@ static struct clk dpll2_m2_ck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
-/* DPLL3 */
-/* Source clock for all interfaces and for some device fclks */
-/* Type: DPLL */
+/*
+ * DPLL3
+ * Source clock for all interfaces and for some device fclks
+ * REVISIT: Also supports fast relock bypass - not included below
+ */
 static const struct dpll_data dpll3_dd = {
         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
@@ -350,6 +380,8 @@ static const struct dpll_data dpll3_dd = {
         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 };
 
 static struct clk dpll3_ck = {
@@ -439,7 +471,7 @@ static struct clk core_ck = {
         .name           = "core_ck",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
         .clksel         = core_ck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -456,7 +488,7 @@ static struct clk dpll3_m2x2_ck = {
         .name           = "dpll3_m2x2_ck",
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
         .clksel         = dpll3_m2x2_ck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -503,7 +535,7 @@ static struct clk emu_core_alwon_ck = {
         .parent         = &dpll3_m3x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel_mask    = OMAP3430_ST_CORE_CLK_MASK,
         .clksel         = emu_core_alwon_ck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -519,16 +551,23 @@ static const struct dpll_data dpll4_dd = {
         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .idlest_bit     = OMAP3430_ST_PERIPH_CLK_SHIFT,
 };
 
 static struct clk dpll4_ck = {
         .name           = "dpll4_ck",
         .parent         = &sys_ck,
         .dpll_data      = &dpll4_dd,
-        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -584,7 +623,7 @@ static struct clk omap_96m_alwon_fck = {
         .parent         = &dpll4_m2x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = omap_96m_alwon_fck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                  PARENT_CONTROLS_CLOCK,
@@ -610,7 +649,7 @@ static struct clk cm_96m_fck = {
         .parent         = &dpll4_m2x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = cm_96m_fck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -652,7 +691,7 @@ static struct clk virt_omap_54m_fck = {
         .parent         = &dpll4_m3x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = virt_omap_54m_fck_clksel,
         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
                                 PARENT_CONTROLS_CLOCK,
@@ -810,17 +849,23 @@ static const struct dpll_data dpll5_dd = {
         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
+        .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+        .idlest_bit     = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
 };
 
 static struct clk dpll5_ck = {
         .name           = "dpll5_ck",
         .parent         = &sys_ck,
         .dpll_data      = &dpll5_dd,
-        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
-                                ALWAYS_ENABLED,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
         .recalc         = &omap3_dpll_recalc,
 };
 
@@ -1939,7 +1984,7 @@ static struct clk dss1_alwon_fck = {
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = dss1_alwon_fck_clksel,
         .flags          = CLOCK_IN_OMAP343X,
         .recalc         = &omap2_clksel_recalc,
@@ -1995,7 +2040,7 @@ static struct clk cam_mclk = {
         .parent         = &dpll4_m5x2_ck,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
         .clksel         = cam_mclk_clksel,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_CAM_SHIFT,