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-rw-r--r--arch/arm/mach-omap2/clock34xx.h11
1 files changed, 0 insertions, 11 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index b08809efb0c8..9a2c07eac9ad 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -8,21 +8,10 @@
8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H 8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
9#define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H 9#define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
10 10
11unsigned long omap3_dpll_recalc(struct clk *clk);
12unsigned long omap3_clkoutx2_recalc(struct clk *clk);
13void omap3_dpll_allow_idle(struct clk *clk);
14void omap3_dpll_deny_idle(struct clk *clk);
15u32 omap3_dpll_autoidle_read(struct clk *clk);
16int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
17int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); 11int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
18int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); 12int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
19void omap3_clk_lock_dpll5(void); 13void omap3_clk_lock_dpll5(void);
20 14
21/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
22#define DPLL_LOW_POWER_STOP 0x1
23#define DPLL_LOW_POWER_BYPASS 0x5
24#define DPLL_LOCKED 0x7
25
26extern struct clk *sdrc_ick_p; 15extern struct clk *sdrc_ick_p;
27extern struct clk *arm_fck_p; 16extern struct clk *arm_fck_p;
28 17