1 files changed, 20 insertions, 11 deletions

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index e5b475f21081..084e11082f80 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -62,11 +62,14 @@ static void omap3_dpll_recalc(struct clk *clk)
 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
 {
         const struct dpll_data *dd;
+        u32 v;
 
         dd = clk->dpll_data;
 
-        cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask),
-                        dd->control_reg);
+        v = __raw_readl(dd->control_reg);
+        v &= ~dd->enable_mask;
+        v |= clken_bits << __ffs(dd->enable_mask);
+        __raw_writel(v, dd->control_reg);
 }
 
 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
@@ -82,7 +85,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
         state <<= dd->idlest_bit;
         idlest_mask = 1 << dd->idlest_bit;
 
-        while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) &&
+        while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
                i < MAX_DPLL_WAIT_TRIES) {
                 i++;
                 udelay(1);
@@ -285,7 +288,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
 
         dd = clk->dpll_data;
 
-        v = cm_read_reg(dd->autoidle_reg);
+        v = __raw_readl(dd->autoidle_reg);
         v &= dd->autoidle_mask;
         v >>= __ffs(dd->autoidle_mask);
 
@@ -304,6 +307,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
 static void omap3_dpll_allow_idle(struct clk *clk)
 {
         const struct dpll_data *dd;
+        u32 v;
 
         if (!clk || !clk->dpll_data)
                 return;
@@ -315,9 +319,10 @@ static void omap3_dpll_allow_idle(struct clk *clk)
          * by writing 0x5 instead of 0x1.  Add some mechanism to
          * optionally enter this mode.
          */
-        cm_rmw_reg_bits(dd->autoidle_mask,
-                        DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask),
-                        dd->autoidle_reg);
+        v = __raw_readl(dd->autoidle_reg);
+        v &= ~dd->autoidle_mask;
+        v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
+        __raw_writel(v, dd->autoidle_reg);
 }
 
 /**
@@ -329,15 +334,17 @@ static void omap3_dpll_allow_idle(struct clk *clk)
 static void omap3_dpll_deny_idle(struct clk *clk)
 {
         const struct dpll_data *dd;
+        u32 v;
 
         if (!clk || !clk->dpll_data)
                 return;
 
         dd = clk->dpll_data;
 
-        cm_rmw_reg_bits(dd->autoidle_mask,
-                        DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask),
-                        dd->autoidle_reg);
+        v = __raw_readl(dd->autoidle_reg);
+        v &= ~dd->autoidle_mask;
+        v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
+        __raw_writel(v, dd->autoidle_reg);
 }
 
 /* Clock control for DPLL outputs */
@@ -482,8 +489,10 @@ int __init omap2_clk_init(void)
         for (clkp = onchip_34xx_clks;
              clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
              clkp++) {
-                if ((*clkp)->flags & cpu_clkflg)
+                if ((*clkp)->flags & cpu_clkflg) {
                         clk_register(*clkp);
+                        omap2_init_clk_clkdm(*clkp);
+                }
         }
 
         /* REVISIT: Not yet ready for OMAP3 */