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-rw-r--r--arch/arm/mach-omap2/clock34xx.c268
1 files changed, 244 insertions, 24 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 52698fb4fd04..2c22750016cc 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -30,6 +30,7 @@
30#include <mach/clock.h> 30#include <mach/clock.h>
31#include <mach/sram.h> 31#include <mach/sram.h>
32#include <asm/div64.h> 32#include <asm/div64.h>
33#include <asm/clkdev.h>
33 34
34#include "memory.h" 35#include "memory.h"
35#include "clock.h" 36#include "clock.h"
@@ -42,6 +43,240 @@ static const struct clkops clkops_noncore_dpll_ops;
42 43
43#include "clock34xx.h" 44#include "clock34xx.h"
44 45
46struct omap_clk {
47 u32 cpu;
48 struct clk_lookup lk;
49};
50
51#define CLK(dev, con, ck, cp) \
52 { \
53 .cpu = cp, \
54 .lk = { \
55 .dev_id = dev, \
56 .con_id = con, \
57 .clk = ck, \
58 }, \
59 }
60
61#define CK_343X (1 << 0)
62#define CK_3430ES1 (1 << 1)
63#define CK_3430ES2 (1 << 2)
64
65static struct omap_clk omap34xx_clks[] = {
66 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
67 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
68 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
69 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
70 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
71 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
72 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
73 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
74 CLK(NULL, "sys_ck", &sys_ck, CK_343X),
75 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
76 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
77 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
78 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
79 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
80 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
81 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
82 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
83 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
84 CLK(NULL, "core_ck", &core_ck, CK_343X),
85 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
86 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
87 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
88 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
89 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
90 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
91 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
92 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
93 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
94 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
95 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
96 CLK(NULL, "virt_omap_54m_fck", &virt_omap_54m_fck, CK_343X),
97 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
98 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
99 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
100 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
101 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
102 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
103 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
104 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
105 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
106 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
107 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
108 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
109 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
110 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
111 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
112 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
113 CLK(NULL, "omap_120m_fck", &omap_120m_fck, CK_3430ES2),
114 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
115 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
116 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
117 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
118 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
119 CLK(NULL, "arm_fck", &arm_fck, CK_343X),
120 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
121 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
122 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
123 CLK(NULL, "l3_ick", &l3_ick, CK_343X),
124 CLK(NULL, "l4_ick", &l4_ick, CK_343X),
125 CLK(NULL, "rm_ick", &rm_ick, CK_343X),
126 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
127 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
128 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
129 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
130 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
131 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
132 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
133 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
134 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
135 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
136 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
137 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
138 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
139 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
140 CLK("mmci-omap-hs.2", "mmchs_fck", &mmchs3_fck, CK_3430ES2),
141 CLK("mmci-omap-hs.1", "mmchs_fck", &mmchs2_fck, CK_343X),
142 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
143 CLK("mmci-omap-hs.0", "mmchs_fck", &mmchs1_fck, CK_343X),
144 CLK("i2c_omap.3", "i2c_fck", &i2c3_fck, CK_343X),
145 CLK("i2c_omap.2", "i2c_fck", &i2c2_fck, CK_343X),
146 CLK("i2c_omap.1", "i2c_fck", &i2c1_fck, CK_343X),
147 CLK("omap-mcbsp.5", "mcbsp_fck", &mcbsp5_fck, CK_343X),
148 CLK("omap-mcbsp.1", "mcbsp_fck", &mcbsp1_fck, CK_343X),
149 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
150 CLK("omap2_mcspi.4", "mcspi_fck", &mcspi4_fck, CK_343X),
151 CLK("omap2_mcspi.3", "mcspi_fck", &mcspi3_fck, CK_343X),
152 CLK("omap2_mcspi.2", "mcspi_fck", &mcspi2_fck, CK_343X),
153 CLK("omap2_mcspi.1", "mcspi_fck", &mcspi1_fck, CK_343X),
154 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
155 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
156 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
157 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
158 CLK(NULL, "hdq_fck", &hdq_fck, CK_343X),
159 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
160 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
161 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
162 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X),
163 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
164 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
165 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
166 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
167 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
168 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
169 CLK("mmci-omap-hs.2", "mmchs_ick", &mmchs3_ick, CK_3430ES2),
170 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
171 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
172 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
173 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
174 CLK("mmci-omap-hs.1", "mmchs_ick", &mmchs2_ick, CK_343X),
175 CLK("mmci-omap-hs.0", "mmchs_ick", &mmchs1_ick, CK_343X),
176 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
177 CLK(NULL, "hdq_ick", &hdq_ick, CK_343X),
178 CLK("omap2_mcspi.4", "mcspi_ick", &mcspi4_ick, CK_343X),
179 CLK("omap2_mcspi.3", "mcspi_ick", &mcspi3_ick, CK_343X),
180 CLK("omap2_mcspi.2", "mcspi_ick", &mcspi2_ick, CK_343X),
181 CLK("omap2_mcspi.1", "mcspi_ick", &mcspi1_ick, CK_343X),
182 CLK("i2c_omap.3", "i2c_ick", &i2c3_ick, CK_343X),
183 CLK("i2c_omap.2", "i2c_ick", &i2c2_ick, CK_343X),
184 CLK("i2c_omap.1", "i2c_ick", &i2c1_ick, CK_343X),
185 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
186 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
187 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
188 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
189 CLK("omap-mcbsp.5", "mcbsp_ick", &mcbsp5_ick, CK_343X),
190 CLK("omap-mcbsp.1", "mcbsp_ick", &mcbsp1_ick, CK_343X),
191 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
192 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
193 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
194 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
195 CLK(NULL, "ssi_ick", &ssi_ick, CK_343X),
196 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
197 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
198 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
199 CLK(NULL, "rng_ick", &rng_ick, CK_343X),
200 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
201 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
202 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
203 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X),
204 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X),
205 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
206 CLK(NULL, "dss_ick", &dss_ick, CK_343X),
207 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
208 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
209 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
210 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
211 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
212 CLK(NULL, "usbhost_sar_fck", &usbhost_sar_fck, CK_3430ES2),
213 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
214 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
215 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
216 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
217 CLK(NULL, "wdt2_fck", &wdt2_fck, CK_343X),
218 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
219 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
220 CLK(NULL, "wdt2_ick", &wdt2_ick, CK_343X),
221 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
222 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
223 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
224 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
225 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
226 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
227 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
228 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
229 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
230 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
231 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
232 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
233 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
234 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
235 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
236 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
237 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
238 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
239 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
240 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
241 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
242 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
243 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
244 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
245 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
246 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
247 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
248 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
249 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
250 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
251 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
252 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
253 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
254 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
255 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
256 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
257 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
258 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
259 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
260 CLK("omap-mcbsp.2", "mcbsp_ick", &mcbsp2_ick, CK_343X),
261 CLK("omap-mcbsp.3", "mcbsp_ick", &mcbsp3_ick, CK_343X),
262 CLK("omap-mcbsp.4", "mcbsp_ick", &mcbsp4_ick, CK_343X),
263 CLK("omap-mcbsp.2", "mcbsp_fck", &mcbsp2_fck, CK_343X),
264 CLK("omap-mcbsp.3", "mcbsp_fck", &mcbsp3_fck, CK_343X),
265 CLK("omap-mcbsp.4", "mcbsp_fck", &mcbsp4_fck, CK_343X),
266 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
267 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
268 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
269 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
270 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
271 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
272 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
273 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
274 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
275 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
276 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
277 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
278};
279
45/* CM_AUTOIDLE_PLL*.AUTO_* bit values */ 280/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
46#define DPLL_AUTOIDLE_DISABLE 0x0 281#define DPLL_AUTOIDLE_DISABLE 0x0
47#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 282#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
@@ -453,26 +688,13 @@ arch_initcall(omap2_clk_arch_init);
453int __init omap2_clk_init(void) 688int __init omap2_clk_init(void)
454{ 689{
455 /* struct prcm_config *prcm; */ 690 /* struct prcm_config *prcm; */
456 struct clk **clkp; 691 struct omap_clk *c;
457 /* u32 clkrate; */ 692 /* u32 clkrate; */
458 u32 cpu_clkflg; 693 u32 cpu_clkflg;
459 694
460 /* REVISIT: Ultimately this will be used for multiboot */
461#if 0
462 if (cpu_is_omap242x()) {
463 cpu_mask = RATE_IN_242X;
464 cpu_clkflg = CLOCK_IN_OMAP242X;
465 clkp = onchip_24xx_clks;
466 } else if (cpu_is_omap2430()) {
467 cpu_mask = RATE_IN_243X;
468 cpu_clkflg = CLOCK_IN_OMAP243X;
469 clkp = onchip_24xx_clks;
470 }
471#endif
472 if (cpu_is_omap34xx()) { 695 if (cpu_is_omap34xx()) {
473 cpu_mask = RATE_IN_343X; 696 cpu_mask = RATE_IN_343X;
474 cpu_clkflg = CLOCK_IN_OMAP343X; 697 cpu_clkflg = CK_343X;
475 clkp = onchip_34xx_clks;
476 698
477 /* 699 /*
478 * Update this if there are further clock changes between ES2 700 * Update this if there are further clock changes between ES2
@@ -480,23 +702,21 @@ int __init omap2_clk_init(void)
480 */ 702 */
481 if (omap_rev() == OMAP3430_REV_ES1_0) { 703 if (omap_rev() == OMAP3430_REV_ES1_0) {
482 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ 704 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
483 cpu_clkflg |= CLOCK_IN_OMAP3430ES1; 705 cpu_clkflg |= CK_3430ES1;
484 } else { 706 } else {
485 cpu_mask |= RATE_IN_3430ES2; 707 cpu_mask |= RATE_IN_3430ES2;
486 cpu_clkflg |= CLOCK_IN_OMAP3430ES2; 708 cpu_clkflg |= CK_3430ES2;
487 } 709 }
488 } 710 }
489 711
490 clk_init(&omap2_clk_functions); 712 clk_init(&omap2_clk_functions);
491 713
492 for (clkp = onchip_34xx_clks; 714 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
493 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); 715 if (c->cpu & cpu_clkflg) {
494 clkp++) { 716 clkdev_add(&c->lk);
495 if ((*clkp)->flags & cpu_clkflg) { 717 clk_register(c->lk.clk);
496 clk_register(*clkp); 718 omap2_init_clk_clkdm(c->lk.clk);
497 omap2_init_clk_clkdm(*clkp);
498 } 719 }
499 }
500 720
501 /* REVISIT: Not yet ready for OMAP3 */ 721 /* REVISIT: Not yet ready for OMAP3 */
502#if 0 722#if 0
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 17:08:24 -0500