1 files changed, 14 insertions, 109 deletions

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index ae9e2c82eb6a..6febd5f11e85 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -8,7 +8,8 @@
  * Jouni Högander
  *
  * Parts of this code are based on code written by
- * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
+ * Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,36 +18,22 @@
 #undef DEBUG
 
 #include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include <plat/cpu.h>
 #include <plat/clock.h>
 
 #include "clock.h"
 #include "clock34xx.h"
-#include "prm.h"
-#include "prm-regbits-34xx.h"
 #include "cm.h"
 #include "cm-regbits-34xx.h"
 
-/*
- * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
- * that are sourced by DPLL5, and both of these require this clock
- * to be at 120 MHz for proper operation.
- */
-#define DPLL5_FREQ_FOR_USBHOST          120000000
-
-/* needed by omap3_core_dpll_m2_set_rate() */
-struct clk *sdrc_ick_p, *arm_fck_p;
-
 /**
  * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
  * @clk: struct clk * being enabled
  * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
  *
  * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
  * from the CM_{I,F}CLKEN bit.  Pass back the correct info via
@@ -54,13 +41,15 @@ struct clk *sdrc_ick_p, *arm_fck_p;
  */
 static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
                                             void __iomem **idlest_reg,
-                                            u8 *idlest_bit)
+                                            u8 *idlest_bit,
+                                            u8 *idlest_val)
 {
         u32 r;
 
         r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
         *idlest_reg = (__force void __iomem *)r;
         *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
+        *idlest_val = OMAP34XX_CM_IDLEST_VAL;
 }
 
 const struct clkops clkops_omap3430es2_ssi_wait = {
@@ -75,6 +64,7 @@ const struct clkops clkops_omap3430es2_ssi_wait = {
  * @clk: struct clk * being enabled
  * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
  *
  * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
  * target IDLEST bits.  For our purposes, we are concerned with the
@@ -85,7 +75,8 @@ const struct clkops clkops_omap3430es2_ssi_wait = {
  */
 static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
                                                     void __iomem **idlest_reg,
-                                                    u8 *idlest_bit)
+                                                    u8 *idlest_bit,
+                                                    u8 *idlest_val)
 {
         u32 r;
 
@@ -93,6 +84,7 @@ static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
         *idlest_reg = (__force void __iomem *)r;
         /* USBHOST_IDLE has same shift */
         *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
+        *idlest_val = OMAP34XX_CM_IDLEST_VAL;
 }
 
 const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
@@ -107,6 +99,7 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
  * @clk: struct clk * being enabled
  * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator
  *
  * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
  * shift from the CM_{I,F}CLKEN bit.  Pass back the correct info via
@@ -114,13 +107,15 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
  */
 static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
                                                  void __iomem **idlest_reg,
-                                                 u8 *idlest_bit)
+                                                 u8 *idlest_bit,
+                                                 u8 *idlest_val)
 {
         u32 r;
 
         r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
         *idlest_reg = (__force void __iomem *)r;
         *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
+        *idlest_val = OMAP34XX_CM_IDLEST_VAL;
 }
 
 const struct clkops clkops_omap3430es2_hsotgusb_wait = {
@@ -129,93 +124,3 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = {
         .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
         .find_companion = omap2_clk_dflt_find_companion,
 };
-
-const struct clkops omap3_clkops_noncore_dpll_ops = {
-        .enable         = omap3_noncore_dpll_enable,
-        .disable        = omap3_noncore_dpll_disable,
-};
-
-int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
-{
-        /*
-         * According to the 12-5 CDP code from TI, "Limitation 2.5"
-         * on 3430ES1 prevents us from changing DPLL multipliers or dividers
-         * on DPLL4.
-         */
-        if (omap_rev() == OMAP3430_REV_ES1_0) {
-                printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
-                       "silicon 'Limitation 2.5' on 3430ES1.\n");
-                return -EINVAL;
-        }
-        return omap3_noncore_dpll_set_rate(clk, rate);
-}
-
-void __init omap3_clk_lock_dpll5(void)
-{
-        struct clk *dpll5_clk;
-        struct clk *dpll5_m2_clk;
-
-        dpll5_clk = clk_get(NULL, "dpll5_ck");
-        clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
-        clk_enable(dpll5_clk);
-
-        /* Enable autoidle to allow it to enter low power bypass */
-        omap3_dpll_allow_idle(dpll5_clk);
-
-        /* Program dpll5_m2_clk divider for no division */
-        dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
-        clk_enable(dpll5_m2_clk);
-        clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
-
-        clk_disable(dpll5_m2_clk);
-        clk_disable(dpll5_clk);
-        return;
-}
-
-/* Common clock code */
-
-/* REVISIT: Move this init stuff out into clock.c */
-
-/*
- * Switch the MPU rate if specified on cmdline.
- * We cannot do this early until cmdline is parsed.
- */
-static int __init omap3xxx_clk_arch_init(void)
-{
-        struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
-        unsigned long osc_sys_rate;
-
-        if (!cpu_is_omap34xx())
-                return 0;
-
-        if (!mpurate)
-                return -EINVAL;
-
-        /* XXX test these for success */
-        dpll1_ck = clk_get(NULL, "dpll1_ck");
-        arm_fck = clk_get(NULL, "arm_fck");
-        core_ck = clk_get(NULL, "core_ck");
-        osc_sys_ck = clk_get(NULL, "osc_sys_ck");
-
-        /* REVISIT: not yet ready for 343x */
-        if (clk_set_rate(dpll1_ck, mpurate))
-                printk(KERN_ERR "*** Unable to set MPU rate\n");
-
-        recalculate_root_clocks();
-
-        osc_sys_rate = clk_get_rate(osc_sys_ck);
-
-        pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
-                "%ld.%01ld/%ld/%ld MHz\n",
-                (osc_sys_rate / 1000000),
-                ((osc_sys_rate / 100000) % 10),
-                (clk_get_rate(core_ck) / 1000000),
-                (clk_get_rate(arm_fck) / 1000000));
-
-        calibrate_delay();
-
-        return 0;
-}
-arch_initcall(omap3xxx_clk_arch_init);
-
-