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Diffstat (limited to 'arch/arm/mach-omap2/clock24xx.h')
-rw-r--r--arch/arm/mach-omap2/clock24xx.h47
1 files changed, 32 insertions, 15 deletions
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 88081ed13f96..be4e25554e05 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -30,12 +30,12 @@ static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30static void omap2_sys_clk_recalc(struct clk *clk); 30static void omap2_sys_clk_recalc(struct clk *clk);
31static void omap2_osc_clk_recalc(struct clk *clk); 31static void omap2_osc_clk_recalc(struct clk *clk);
32static void omap2_sys_clk_recalc(struct clk *clk); 32static void omap2_sys_clk_recalc(struct clk *clk);
33static void omap2_dpll_recalc(struct clk *clk); 33static void omap2_dpllcore_recalc(struct clk *clk);
34static int omap2_clk_fixed_enable(struct clk *clk); 34static int omap2_clk_fixed_enable(struct clk *clk);
35static void omap2_clk_fixed_disable(struct clk *clk); 35static void omap2_clk_fixed_disable(struct clk *clk);
36static int omap2_enable_osc_ck(struct clk *clk); 36static int omap2_enable_osc_ck(struct clk *clk);
37static void omap2_disable_osc_ck(struct clk *clk); 37static void omap2_disable_osc_ck(struct clk *clk);
38static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate); 38static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
39 39
40/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 40/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
41 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP 41 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
@@ -665,20 +665,27 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
665 * deal with this 665 * deal with this
666 */ 666 */
667 667
668static const struct dpll_data dpll_dd = { 668static struct dpll_data dpll_dd = {
669 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 669 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
670 .mult_mask = OMAP24XX_DPLL_MULT_MASK, 670 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
671 .div1_mask = OMAP24XX_DPLL_DIV_MASK, 671 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
672 .max_multiplier = 1024,
673 .max_divider = 16,
674 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
672}; 675};
673 676
677/*
678 * XXX Cannot add round_rate here yet, as this is still a composite clock,
679 * not just a DPLL
680 */
674static struct clk dpll_ck = { 681static struct clk dpll_ck = {
675 .name = "dpll_ck", 682 .name = "dpll_ck",
676 .parent = &sys_ck, /* Can be func_32k also */ 683 .parent = &sys_ck, /* Can be func_32k also */
677 .dpll_data = &dpll_dd, 684 .dpll_data = &dpll_dd,
678 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 685 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
679 RATE_PROPAGATES | ALWAYS_ENABLED, 686 RATE_PROPAGATES | ALWAYS_ENABLED,
680 .recalc = &omap2_dpll_recalc, 687 .recalc = &omap2_dpllcore_recalc,
681 .set_rate = &omap2_reprogram_dpll, 688 .set_rate = &omap2_reprogram_dpllcore,
682}; 689};
683 690
684static struct clk apll96_ck = { 691static struct clk apll96_ck = {
@@ -1747,7 +1754,8 @@ static struct clk gpt12_fck = {
1747}; 1754};
1748 1755
1749static struct clk mcbsp1_ick = { 1756static struct clk mcbsp1_ick = {
1750 .name = "mcbsp1_ick", 1757 .name = "mcbsp_ick",
1758 .id = 1,
1751 .parent = &l4_ck, 1759 .parent = &l4_ck,
1752 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1760 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1753 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1761 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1756,7 +1764,8 @@ static struct clk mcbsp1_ick = {
1756}; 1764};
1757 1765
1758static struct clk mcbsp1_fck = { 1766static struct clk mcbsp1_fck = {
1759 .name = "mcbsp1_fck", 1767 .name = "mcbsp_fck",
1768 .id = 1,
1760 .parent = &func_96m_ck, 1769 .parent = &func_96m_ck,
1761 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1770 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1762 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1765,7 +1774,8 @@ static struct clk mcbsp1_fck = {
1765}; 1774};
1766 1775
1767static struct clk mcbsp2_ick = { 1776static struct clk mcbsp2_ick = {
1768 .name = "mcbsp2_ick", 1777 .name = "mcbsp_ick",
1778 .id = 2,
1769 .parent = &l4_ck, 1779 .parent = &l4_ck,
1770 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1780 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1781 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1774,7 +1784,8 @@ static struct clk mcbsp2_ick = {
1774}; 1784};
1775 1785
1776static struct clk mcbsp2_fck = { 1786static struct clk mcbsp2_fck = {
1777 .name = "mcbsp2_fck", 1787 .name = "mcbsp_fck",
1788 .id = 2,
1778 .parent = &func_96m_ck, 1789 .parent = &func_96m_ck,
1779 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1790 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1791 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1783,7 +1794,8 @@ static struct clk mcbsp2_fck = {
1783}; 1794};
1784 1795
1785static struct clk mcbsp3_ick = { 1796static struct clk mcbsp3_ick = {
1786 .name = "mcbsp3_ick", 1797 .name = "mcbsp_ick",
1798 .id = 3,
1787 .parent = &l4_ck, 1799 .parent = &l4_ck,
1788 .flags = CLOCK_IN_OMAP243X, 1800 .flags = CLOCK_IN_OMAP243X,
1789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1801 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1792,7 +1804,8 @@ static struct clk mcbsp3_ick = {
1792}; 1804};
1793 1805
1794static struct clk mcbsp3_fck = { 1806static struct clk mcbsp3_fck = {
1795 .name = "mcbsp3_fck", 1807 .name = "mcbsp_fck",
1808 .id = 3,
1796 .parent = &func_96m_ck, 1809 .parent = &func_96m_ck,
1797 .flags = CLOCK_IN_OMAP243X, 1810 .flags = CLOCK_IN_OMAP243X,
1798 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1811 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1801,7 +1814,8 @@ static struct clk mcbsp3_fck = {
1801}; 1814};
1802 1815
1803static struct clk mcbsp4_ick = { 1816static struct clk mcbsp4_ick = {
1804 .name = "mcbsp4_ick", 1817 .name = "mcbsp_ick",
1818 .id = 4,
1805 .parent = &l4_ck, 1819 .parent = &l4_ck,
1806 .flags = CLOCK_IN_OMAP243X, 1820 .flags = CLOCK_IN_OMAP243X,
1807 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1821 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1810,7 +1824,8 @@ static struct clk mcbsp4_ick = {
1810}; 1824};
1811 1825
1812static struct clk mcbsp4_fck = { 1826static struct clk mcbsp4_fck = {
1813 .name = "mcbsp4_fck", 1827 .name = "mcbsp_fck",
1828 .id = 4,
1814 .parent = &func_96m_ck, 1829 .parent = &func_96m_ck,
1815 .flags = CLOCK_IN_OMAP243X, 1830 .flags = CLOCK_IN_OMAP243X,
1816 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1819,7 +1834,8 @@ static struct clk mcbsp4_fck = {
1819}; 1834};
1820 1835
1821static struct clk mcbsp5_ick = { 1836static struct clk mcbsp5_ick = {
1822 .name = "mcbsp5_ick", 1837 .name = "mcbsp_ick",
1838 .id = 5,
1823 .parent = &l4_ck, 1839 .parent = &l4_ck,
1824 .flags = CLOCK_IN_OMAP243X, 1840 .flags = CLOCK_IN_OMAP243X,
1825 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1828,7 +1844,8 @@ static struct clk mcbsp5_ick = {
1828}; 1844};
1829 1845
1830static struct clk mcbsp5_fck = { 1846static struct clk mcbsp5_fck = {
1831 .name = "mcbsp5_fck", 1847 .name = "mcbsp_fck",
1848 .id = 5,
1832 .parent = &func_96m_ck, 1849 .parent = &func_96m_ck,
1833 .flags = CLOCK_IN_OMAP243X, 1850 .flags = CLOCK_IN_OMAP243X,
1834 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),