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Diffstat (limited to 'arch/arm/mach-omap2/clock24xx.h')
-rw-r--r--arch/arm/mach-omap2/clock24xx.h17
1 files changed, 12 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 06e1118ddba2..be4e25554e05 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -30,12 +30,12 @@ static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30static void omap2_sys_clk_recalc(struct clk *clk); 30static void omap2_sys_clk_recalc(struct clk *clk);
31static void omap2_osc_clk_recalc(struct clk *clk); 31static void omap2_osc_clk_recalc(struct clk *clk);
32static void omap2_sys_clk_recalc(struct clk *clk); 32static void omap2_sys_clk_recalc(struct clk *clk);
33static void omap2_dpll_recalc(struct clk *clk); 33static void omap2_dpllcore_recalc(struct clk *clk);
34static int omap2_clk_fixed_enable(struct clk *clk); 34static int omap2_clk_fixed_enable(struct clk *clk);
35static void omap2_clk_fixed_disable(struct clk *clk); 35static void omap2_clk_fixed_disable(struct clk *clk);
36static int omap2_enable_osc_ck(struct clk *clk); 36static int omap2_enable_osc_ck(struct clk *clk);
37static void omap2_disable_osc_ck(struct clk *clk); 37static void omap2_disable_osc_ck(struct clk *clk);
38static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate); 38static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
39 39
40/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 40/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
41 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP 41 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
@@ -665,20 +665,27 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
665 * deal with this 665 * deal with this
666 */ 666 */
667 667
668static const struct dpll_data dpll_dd = { 668static struct dpll_data dpll_dd = {
669 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 669 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
670 .mult_mask = OMAP24XX_DPLL_MULT_MASK, 670 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
671 .div1_mask = OMAP24XX_DPLL_DIV_MASK, 671 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
672 .max_multiplier = 1024,
673 .max_divider = 16,
674 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
672}; 675};
673 676
677/*
678 * XXX Cannot add round_rate here yet, as this is still a composite clock,
679 * not just a DPLL
680 */
674static struct clk dpll_ck = { 681static struct clk dpll_ck = {
675 .name = "dpll_ck", 682 .name = "dpll_ck",
676 .parent = &sys_ck, /* Can be func_32k also */ 683 .parent = &sys_ck, /* Can be func_32k also */
677 .dpll_data = &dpll_dd, 684 .dpll_data = &dpll_dd,
678 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 685 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
679 RATE_PROPAGATES | ALWAYS_ENABLED, 686 RATE_PROPAGATES | ALWAYS_ENABLED,
680 .recalc = &omap2_dpll_recalc, 687 .recalc = &omap2_dpllcore_recalc,
681 .set_rate = &omap2_reprogram_dpll, 688 .set_rate = &omap2_reprogram_dpllcore,
682}; 689};
683 690
684static struct clk apll96_ck = { 691static struct clk apll96_ck = {