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-rw-r--r--arch/arm/mach-omap2/clock24xx.h525
1 files changed, 185 insertions, 340 deletions
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index ad6d98d177c5..33c3e5b14323 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -24,17 +24,13 @@
24#include "cm-regbits-24xx.h" 24#include "cm-regbits-24xx.h"
25#include "sdrc.h" 25#include "sdrc.h"
26 26
27static void omap2_table_mpu_recalc(struct clk *clk); 27static unsigned long omap2_table_mpu_recalc(struct clk *clk);
28static int omap2_select_table_rate(struct clk *clk, unsigned long rate); 28static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
29static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); 29static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30static void omap2_sys_clk_recalc(struct clk *clk); 30static unsigned long omap2_sys_clk_recalc(struct clk *clk);
31static void omap2_osc_clk_recalc(struct clk *clk); 31static unsigned long omap2_osc_clk_recalc(struct clk *clk);
32static void omap2_sys_clk_recalc(struct clk *clk); 32static unsigned long omap2_sys_clk_recalc(struct clk *clk);
33static void omap2_dpllcore_recalc(struct clk *clk); 33static unsigned long omap2_dpllcore_recalc(struct clk *clk);
34static int omap2_clk_fixed_enable(struct clk *clk);
35static void omap2_clk_fixed_disable(struct clk *clk);
36static int omap2_enable_osc_ck(struct clk *clk);
37static void omap2_disable_osc_ck(struct clk *clk);
38static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); 34static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
39 35
40/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 36/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
@@ -623,41 +619,35 @@ static struct prcm_config rate_table[] = {
623/* Base external input clocks */ 619/* Base external input clocks */
624static struct clk func_32k_ck = { 620static struct clk func_32k_ck = {
625 .name = "func_32k_ck", 621 .name = "func_32k_ck",
622 .ops = &clkops_null,
626 .rate = 32000, 623 .rate = 32000,
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 624 .flags = RATE_FIXED,
628 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
629 .clkdm_name = "wkup_clkdm", 625 .clkdm_name = "wkup_clkdm",
630 .recalc = &propagate_rate,
631}; 626};
632 627
633/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ 628/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
634static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ 629static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
635 .name = "osc_ck", 630 .name = "osc_ck",
636 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 631 .ops = &clkops_oscck,
637 RATE_PROPAGATES,
638 .clkdm_name = "wkup_clkdm", 632 .clkdm_name = "wkup_clkdm",
639 .enable = &omap2_enable_osc_ck,
640 .disable = &omap2_disable_osc_ck,
641 .recalc = &omap2_osc_clk_recalc, 633 .recalc = &omap2_osc_clk_recalc,
642}; 634};
643 635
644/* Without modem likely 12MHz, with modem likely 13MHz */ 636/* Without modem likely 12MHz, with modem likely 13MHz */
645static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ 637static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
646 .name = "sys_ck", /* ~ ref_clk also */ 638 .name = "sys_ck", /* ~ ref_clk also */
639 .ops = &clkops_null,
647 .parent = &osc_ck, 640 .parent = &osc_ck,
648 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
649 ALWAYS_ENABLED | RATE_PROPAGATES,
650 .clkdm_name = "wkup_clkdm", 641 .clkdm_name = "wkup_clkdm",
651 .recalc = &omap2_sys_clk_recalc, 642 .recalc = &omap2_sys_clk_recalc,
652}; 643};
653 644
654static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ 645static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
655 .name = "alt_ck", 646 .name = "alt_ck",
647 .ops = &clkops_null,
656 .rate = 54000000, 648 .rate = 54000000,
657 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 649 .flags = RATE_FIXED,
658 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
659 .clkdm_name = "wkup_clkdm", 650 .clkdm_name = "wkup_clkdm",
660 .recalc = &propagate_rate,
661}; 651};
662 652
663/* 653/*
@@ -673,7 +663,12 @@ static struct dpll_data dpll_dd = {
673 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 663 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
674 .mult_mask = OMAP24XX_DPLL_MULT_MASK, 664 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
675 .div1_mask = OMAP24XX_DPLL_DIV_MASK, 665 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
666 .clk_bypass = &sys_ck,
667 .clk_ref = &sys_ck,
668 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
669 .enable_mask = OMAP24XX_EN_DPLL_MASK,
676 .max_multiplier = 1024, 670 .max_multiplier = 1024,
671 .min_divider = 1,
677 .max_divider = 16, 672 .max_divider = 16,
678 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 673 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
679}; 674};
@@ -684,10 +679,9 @@ static struct dpll_data dpll_dd = {
684 */ 679 */
685static struct clk dpll_ck = { 680static struct clk dpll_ck = {
686 .name = "dpll_ck", 681 .name = "dpll_ck",
682 .ops = &clkops_null,
687 .parent = &sys_ck, /* Can be func_32k also */ 683 .parent = &sys_ck, /* Can be func_32k also */
688 .dpll_data = &dpll_dd, 684 .dpll_data = &dpll_dd,
689 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
690 RATE_PROPAGATES | ALWAYS_ENABLED,
691 .clkdm_name = "wkup_clkdm", 685 .clkdm_name = "wkup_clkdm",
692 .recalc = &omap2_dpllcore_recalc, 686 .recalc = &omap2_dpllcore_recalc,
693 .set_rate = &omap2_reprogram_dpllcore, 687 .set_rate = &omap2_reprogram_dpllcore,
@@ -695,30 +689,24 @@ static struct clk dpll_ck = {
695 689
696static struct clk apll96_ck = { 690static struct clk apll96_ck = {
697 .name = "apll96_ck", 691 .name = "apll96_ck",
692 .ops = &clkops_fixed,
698 .parent = &sys_ck, 693 .parent = &sys_ck,
699 .rate = 96000000, 694 .rate = 96000000,
700 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 695 .flags = RATE_FIXED | ENABLE_ON_INIT,
701 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
702 .clkdm_name = "wkup_clkdm", 696 .clkdm_name = "wkup_clkdm",
703 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 697 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
704 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, 698 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
705 .enable = &omap2_clk_fixed_enable,
706 .disable = &omap2_clk_fixed_disable,
707 .recalc = &propagate_rate,
708}; 699};
709 700
710static struct clk apll54_ck = { 701static struct clk apll54_ck = {
711 .name = "apll54_ck", 702 .name = "apll54_ck",
703 .ops = &clkops_fixed,
712 .parent = &sys_ck, 704 .parent = &sys_ck,
713 .rate = 54000000, 705 .rate = 54000000,
714 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 706 .flags = RATE_FIXED | ENABLE_ON_INIT,
715 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
716 .clkdm_name = "wkup_clkdm", 707 .clkdm_name = "wkup_clkdm",
717 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 708 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
718 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, 709 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
719 .enable = &omap2_clk_fixed_enable,
720 .disable = &omap2_clk_fixed_disable,
721 .recalc = &propagate_rate,
722}; 710};
723 711
724/* 712/*
@@ -745,9 +733,8 @@ static const struct clksel func_54m_clksel[] = {
745 733
746static struct clk func_54m_ck = { 734static struct clk func_54m_ck = {
747 .name = "func_54m_ck", 735 .name = "func_54m_ck",
736 .ops = &clkops_null,
748 .parent = &apll54_ck, /* can also be alt_clk */ 737 .parent = &apll54_ck, /* can also be alt_clk */
749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
750 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
751 .clkdm_name = "wkup_clkdm", 738 .clkdm_name = "wkup_clkdm",
752 .init = &omap2_init_clksel_parent, 739 .init = &omap2_init_clksel_parent,
753 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 740 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -758,9 +745,8 @@ static struct clk func_54m_ck = {
758 745
759static struct clk core_ck = { 746static struct clk core_ck = {
760 .name = "core_ck", 747 .name = "core_ck",
748 .ops = &clkops_null,
761 .parent = &dpll_ck, /* can also be 32k */ 749 .parent = &dpll_ck, /* can also be 32k */
762 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
763 ALWAYS_ENABLED | RATE_PROPAGATES,
764 .clkdm_name = "wkup_clkdm", 750 .clkdm_name = "wkup_clkdm",
765 .recalc = &followparent_recalc, 751 .recalc = &followparent_recalc,
766}; 752};
@@ -785,9 +771,8 @@ static const struct clksel func_96m_clksel[] = {
785/* The parent of this clock is not selectable on 2420. */ 771/* The parent of this clock is not selectable on 2420. */
786static struct clk func_96m_ck = { 772static struct clk func_96m_ck = {
787 .name = "func_96m_ck", 773 .name = "func_96m_ck",
774 .ops = &clkops_null,
788 .parent = &apll96_ck, 775 .parent = &apll96_ck,
789 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
790 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
791 .clkdm_name = "wkup_clkdm", 776 .clkdm_name = "wkup_clkdm",
792 .init = &omap2_init_clksel_parent, 777 .init = &omap2_init_clksel_parent,
793 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 778 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -818,9 +803,8 @@ static const struct clksel func_48m_clksel[] = {
818 803
819static struct clk func_48m_ck = { 804static struct clk func_48m_ck = {
820 .name = "func_48m_ck", 805 .name = "func_48m_ck",
806 .ops = &clkops_null,
821 .parent = &apll96_ck, /* 96M or Alt */ 807 .parent = &apll96_ck, /* 96M or Alt */
822 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
823 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
824 .clkdm_name = "wkup_clkdm", 808 .clkdm_name = "wkup_clkdm",
825 .init = &omap2_init_clksel_parent, 809 .init = &omap2_init_clksel_parent,
826 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 810 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -833,10 +817,9 @@ static struct clk func_48m_ck = {
833 817
834static struct clk func_12m_ck = { 818static struct clk func_12m_ck = {
835 .name = "func_12m_ck", 819 .name = "func_12m_ck",
820 .ops = &clkops_null,
836 .parent = &func_48m_ck, 821 .parent = &func_48m_ck,
837 .fixed_div = 4, 822 .fixed_div = 4,
838 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
839 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
840 .clkdm_name = "wkup_clkdm", 823 .clkdm_name = "wkup_clkdm",
841 .recalc = &omap2_fixed_divisor_recalc, 824 .recalc = &omap2_fixed_divisor_recalc,
842}; 825};
@@ -844,8 +827,8 @@ static struct clk func_12m_ck = {
844/* Secure timer, only available in secure mode */ 827/* Secure timer, only available in secure mode */
845static struct clk wdt1_osc_ck = { 828static struct clk wdt1_osc_ck = {
846 .name = "ck_wdt1_osc", 829 .name = "ck_wdt1_osc",
830 .ops = &clkops_null, /* RMK: missing? */
847 .parent = &osc_ck, 831 .parent = &osc_ck,
848 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
849 .recalc = &followparent_recalc, 832 .recalc = &followparent_recalc,
850}; 833};
851 834
@@ -887,9 +870,8 @@ static const struct clksel common_clkout_src_clksel[] = {
887 870
888static struct clk sys_clkout_src = { 871static struct clk sys_clkout_src = {
889 .name = "sys_clkout_src", 872 .name = "sys_clkout_src",
873 .ops = &clkops_omap2_dflt,
890 .parent = &func_54m_ck, 874 .parent = &func_54m_ck,
891 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
892 RATE_PROPAGATES,
893 .clkdm_name = "wkup_clkdm", 875 .clkdm_name = "wkup_clkdm",
894 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 876 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
895 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, 877 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
@@ -918,9 +900,8 @@ static const struct clksel sys_clkout_clksel[] = {
918 900
919static struct clk sys_clkout = { 901static struct clk sys_clkout = {
920 .name = "sys_clkout", 902 .name = "sys_clkout",
903 .ops = &clkops_null,
921 .parent = &sys_clkout_src, 904 .parent = &sys_clkout_src,
922 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
923 PARENT_CONTROLS_CLOCK,
924 .clkdm_name = "wkup_clkdm", 905 .clkdm_name = "wkup_clkdm",
925 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 906 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
926 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, 907 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
@@ -933,8 +914,8 @@ static struct clk sys_clkout = {
933/* In 2430, new in 2420 ES2 */ 914/* In 2430, new in 2420 ES2 */
934static struct clk sys_clkout2_src = { 915static struct clk sys_clkout2_src = {
935 .name = "sys_clkout2_src", 916 .name = "sys_clkout2_src",
917 .ops = &clkops_omap2_dflt,
936 .parent = &func_54m_ck, 918 .parent = &func_54m_ck,
937 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
938 .clkdm_name = "wkup_clkdm", 919 .clkdm_name = "wkup_clkdm",
939 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 920 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
940 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, 921 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
@@ -955,8 +936,8 @@ static const struct clksel sys_clkout2_clksel[] = {
955/* In 2430, new in 2420 ES2 */ 936/* In 2430, new in 2420 ES2 */
956static struct clk sys_clkout2 = { 937static struct clk sys_clkout2 = {
957 .name = "sys_clkout2", 938 .name = "sys_clkout2",
939 .ops = &clkops_null,
958 .parent = &sys_clkout2_src, 940 .parent = &sys_clkout2_src,
959 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
960 .clkdm_name = "wkup_clkdm", 941 .clkdm_name = "wkup_clkdm",
961 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 942 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
962 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, 943 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
@@ -968,8 +949,8 @@ static struct clk sys_clkout2 = {
968 949
969static struct clk emul_ck = { 950static struct clk emul_ck = {
970 .name = "emul_ck", 951 .name = "emul_ck",
952 .ops = &clkops_omap2_dflt,
971 .parent = &func_54m_ck, 953 .parent = &func_54m_ck,
972 .flags = CLOCK_IN_OMAP242X,
973 .clkdm_name = "wkup_clkdm", 954 .clkdm_name = "wkup_clkdm",
974 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, 955 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
975 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, 956 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
@@ -1003,10 +984,9 @@ static const struct clksel mpu_clksel[] = {
1003 984
1004static struct clk mpu_ck = { /* Control cpu */ 985static struct clk mpu_ck = { /* Control cpu */
1005 .name = "mpu_ck", 986 .name = "mpu_ck",
987 .ops = &clkops_null,
1006 .parent = &core_ck, 988 .parent = &core_ck,
1007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 989 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1008 ALWAYS_ENABLED | DELAYED_APP |
1009 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1010 .clkdm_name = "mpu_clkdm", 990 .clkdm_name = "mpu_clkdm",
1011 .init = &omap2_init_clksel_parent, 991 .init = &omap2_init_clksel_parent,
1012 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), 992 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
@@ -1046,9 +1026,9 @@ static const struct clksel dsp_fck_clksel[] = {
1046 1026
1047static struct clk dsp_fck = { 1027static struct clk dsp_fck = {
1048 .name = "dsp_fck", 1028 .name = "dsp_fck",
1029 .ops = &clkops_omap2_dflt_wait,
1049 .parent = &core_ck, 1030 .parent = &core_ck,
1050 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | 1031 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1051 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1052 .clkdm_name = "dsp_clkdm", 1032 .clkdm_name = "dsp_clkdm",
1053 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1033 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1054 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 1034 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
@@ -1076,9 +1056,9 @@ static const struct clksel dsp_irate_ick_clksel[] = {
1076/* This clock does not exist as such in the TRM. */ 1056/* This clock does not exist as such in the TRM. */
1077static struct clk dsp_irate_ick = { 1057static struct clk dsp_irate_ick = {
1078 .name = "dsp_irate_ick", 1058 .name = "dsp_irate_ick",
1059 .ops = &clkops_null,
1079 .parent = &dsp_fck, 1060 .parent = &dsp_fck,
1080 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | 1061 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1081 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1082 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), 1062 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1083 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, 1063 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1084 .clksel = dsp_irate_ick_clksel, 1064 .clksel = dsp_irate_ick_clksel,
@@ -1090,8 +1070,9 @@ static struct clk dsp_irate_ick = {
1090/* 2420 only */ 1070/* 2420 only */
1091static struct clk dsp_ick = { 1071static struct clk dsp_ick = {
1092 .name = "dsp_ick", /* apparently ipi and isp */ 1072 .name = "dsp_ick", /* apparently ipi and isp */
1073 .ops = &clkops_omap2_dflt_wait,
1093 .parent = &dsp_irate_ick, 1074 .parent = &dsp_irate_ick,
1094 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT, 1075 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1095 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), 1076 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1096 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ 1077 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1097}; 1078};
@@ -1099,8 +1080,9 @@ static struct clk dsp_ick = {
1099/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ 1080/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1100static struct clk iva2_1_ick = { 1081static struct clk iva2_1_ick = {
1101 .name = "iva2_1_ick", 1082 .name = "iva2_1_ick",
1083 .ops = &clkops_omap2_dflt_wait,
1102 .parent = &dsp_irate_ick, 1084 .parent = &dsp_irate_ick,
1103 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, 1085 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1104 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1086 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1105 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 1087 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1106}; 1088};
@@ -1112,9 +1094,9 @@ static struct clk iva2_1_ick = {
1112 */ 1094 */
1113static struct clk iva1_ifck = { 1095static struct clk iva1_ifck = {
1114 .name = "iva1_ifck", 1096 .name = "iva1_ifck",
1097 .ops = &clkops_omap2_dflt_wait,
1115 .parent = &core_ck, 1098 .parent = &core_ck,
1116 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | 1099 .flags = CONFIG_PARTICIPANT | DELAYED_APP,
1117 RATE_PROPAGATES | DELAYED_APP,
1118 .clkdm_name = "iva1_clkdm", 1100 .clkdm_name = "iva1_clkdm",
1119 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1101 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1120 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, 1102 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
@@ -1129,8 +1111,8 @@ static struct clk iva1_ifck = {
1129/* IVA1 mpu/int/i/f clocks are /2 of parent */ 1111/* IVA1 mpu/int/i/f clocks are /2 of parent */
1130static struct clk iva1_mpu_int_ifck = { 1112static struct clk iva1_mpu_int_ifck = {
1131 .name = "iva1_mpu_int_ifck", 1113 .name = "iva1_mpu_int_ifck",
1114 .ops = &clkops_omap2_dflt_wait,
1132 .parent = &iva1_ifck, 1115 .parent = &iva1_ifck,
1133 .flags = CLOCK_IN_OMAP242X,
1134 .clkdm_name = "iva1_clkdm", 1116 .clkdm_name = "iva1_clkdm",
1135 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1117 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1136 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, 1118 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
@@ -1175,10 +1157,9 @@ static const struct clksel core_l3_clksel[] = {
1175 1157
1176static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ 1158static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1177 .name = "core_l3_ck", 1159 .name = "core_l3_ck",
1160 .ops = &clkops_null,
1178 .parent = &core_ck, 1161 .parent = &core_ck,
1179 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1162 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1180 ALWAYS_ENABLED | DELAYED_APP |
1181 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1182 .clkdm_name = "core_l3_clkdm", 1163 .clkdm_name = "core_l3_clkdm",
1183 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1164 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1184 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, 1165 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
@@ -1204,9 +1185,9 @@ static const struct clksel usb_l4_ick_clksel[] = {
1204/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ 1185/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1205static struct clk usb_l4_ick = { /* FS-USB interface clock */ 1186static struct clk usb_l4_ick = { /* FS-USB interface clock */
1206 .name = "usb_l4_ick", 1187 .name = "usb_l4_ick",
1188 .ops = &clkops_omap2_dflt_wait,
1207 .parent = &core_l3_ck, 1189 .parent = &core_l3_ck,
1208 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1190 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1209 DELAYED_APP | CONFIG_PARTICIPANT,
1210 .clkdm_name = "core_l4_clkdm", 1191 .clkdm_name = "core_l4_clkdm",
1211 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1192 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1212 .enable_bit = OMAP24XX_EN_USB_SHIFT, 1193 .enable_bit = OMAP24XX_EN_USB_SHIFT,
@@ -1238,9 +1219,9 @@ static const struct clksel l4_clksel[] = {
1238 1219
1239static struct clk l4_ck = { /* used both as an ick and fck */ 1220static struct clk l4_ck = { /* used both as an ick and fck */
1240 .name = "l4_ck", 1221 .name = "l4_ck",
1222 .ops = &clkops_null,
1241 .parent = &core_l3_ck, 1223 .parent = &core_l3_ck,
1242 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1224 .flags = DELAYED_APP,
1243 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1244 .clkdm_name = "core_l4_clkdm", 1225 .clkdm_name = "core_l4_clkdm",
1245 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1226 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1246 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, 1227 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
@@ -1276,9 +1257,9 @@ static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1276 1257
1277static struct clk ssi_ssr_sst_fck = { 1258static struct clk ssi_ssr_sst_fck = {
1278 .name = "ssi_fck", 1259 .name = "ssi_fck",
1260 .ops = &clkops_omap2_dflt_wait,
1279 .parent = &core_ck, 1261 .parent = &core_ck,
1280 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1262 .flags = DELAYED_APP,
1281 DELAYED_APP,
1282 .clkdm_name = "core_l3_clkdm", 1263 .clkdm_name = "core_l3_clkdm",
1283 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1264 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1284 .enable_bit = OMAP24XX_EN_SSI_SHIFT, 1265 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
@@ -1290,6 +1271,20 @@ static struct clk ssi_ssr_sst_fck = {
1290 .set_rate = &omap2_clksel_set_rate 1271 .set_rate = &omap2_clksel_set_rate
1291}; 1272};
1292 1273
1274/*
1275 * Presumably this is the same as SSI_ICLK.
1276 * TRM contradicts itself on what clockdomain SSI_ICLK is in
1277 */
1278static struct clk ssi_l4_ick = {
1279 .name = "ssi_l4_ick",
1280 .ops = &clkops_omap2_dflt_wait,
1281 .parent = &l4_ck,
1282 .clkdm_name = "core_l4_clkdm",
1283 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1284 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1285 .recalc = &followparent_recalc,
1286};
1287
1293 1288
1294/* 1289/*
1295 * GFX clock domain 1290 * GFX clock domain
@@ -1312,8 +1307,8 @@ static const struct clksel gfx_fck_clksel[] = {
1312 1307
1313static struct clk gfx_3d_fck = { 1308static struct clk gfx_3d_fck = {
1314 .name = "gfx_3d_fck", 1309 .name = "gfx_3d_fck",
1310 .ops = &clkops_omap2_dflt_wait,
1315 .parent = &core_l3_ck, 1311 .parent = &core_l3_ck,
1316 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1317 .clkdm_name = "gfx_clkdm", 1312 .clkdm_name = "gfx_clkdm",
1318 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1313 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1319 .enable_bit = OMAP24XX_EN_3D_SHIFT, 1314 .enable_bit = OMAP24XX_EN_3D_SHIFT,
@@ -1327,8 +1322,8 @@ static struct clk gfx_3d_fck = {
1327 1322
1328static struct clk gfx_2d_fck = { 1323static struct clk gfx_2d_fck = {
1329 .name = "gfx_2d_fck", 1324 .name = "gfx_2d_fck",
1325 .ops = &clkops_omap2_dflt_wait,
1330 .parent = &core_l3_ck, 1326 .parent = &core_l3_ck,
1331 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1332 .clkdm_name = "gfx_clkdm", 1327 .clkdm_name = "gfx_clkdm",
1333 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1328 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1334 .enable_bit = OMAP24XX_EN_2D_SHIFT, 1329 .enable_bit = OMAP24XX_EN_2D_SHIFT,
@@ -1342,8 +1337,8 @@ static struct clk gfx_2d_fck = {
1342 1337
1343static struct clk gfx_ick = { 1338static struct clk gfx_ick = {
1344 .name = "gfx_ick", /* From l3 */ 1339 .name = "gfx_ick", /* From l3 */
1340 .ops = &clkops_omap2_dflt_wait,
1345 .parent = &core_l3_ck, 1341 .parent = &core_l3_ck,
1346 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1347 .clkdm_name = "gfx_clkdm", 1342 .clkdm_name = "gfx_clkdm",
1348 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1343 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1349 .enable_bit = OMAP_EN_GFX_SHIFT, 1344 .enable_bit = OMAP_EN_GFX_SHIFT,
@@ -1372,8 +1367,9 @@ static const struct clksel mdm_ick_clksel[] = {
1372 1367
1373static struct clk mdm_ick = { /* used both as a ick and fck */ 1368static struct clk mdm_ick = { /* used both as a ick and fck */
1374 .name = "mdm_ick", 1369 .name = "mdm_ick",
1370 .ops = &clkops_omap2_dflt_wait,
1375 .parent = &core_ck, 1371 .parent = &core_ck,
1376 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, 1372 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1377 .clkdm_name = "mdm_clkdm", 1373 .clkdm_name = "mdm_clkdm",
1378 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), 1374 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1379 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, 1375 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
@@ -1387,8 +1383,8 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
1387 1383
1388static struct clk mdm_osc_ck = { 1384static struct clk mdm_osc_ck = {
1389 .name = "mdm_osc_ck", 1385 .name = "mdm_osc_ck",
1386 .ops = &clkops_omap2_dflt_wait,
1390 .parent = &osc_ck, 1387 .parent = &osc_ck,
1391 .flags = CLOCK_IN_OMAP243X,
1392 .clkdm_name = "mdm_clkdm", 1388 .clkdm_name = "mdm_clkdm",
1393 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), 1389 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1394 .enable_bit = OMAP2430_EN_OSC_SHIFT, 1390 .enable_bit = OMAP2430_EN_OSC_SHIFT,
@@ -1432,8 +1428,8 @@ static const struct clksel dss1_fck_clksel[] = {
1432 1428
1433static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ 1429static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1434 .name = "dss_ick", 1430 .name = "dss_ick",
1431 .ops = &clkops_omap2_dflt,
1435 .parent = &l4_ck, /* really both l3 and l4 */ 1432 .parent = &l4_ck, /* really both l3 and l4 */
1436 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1437 .clkdm_name = "dss_clkdm", 1433 .clkdm_name = "dss_clkdm",
1438 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1434 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1439 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 1435 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
@@ -1442,9 +1438,9 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1442 1438
1443static struct clk dss1_fck = { 1439static struct clk dss1_fck = {
1444 .name = "dss1_fck", 1440 .name = "dss1_fck",
1441 .ops = &clkops_omap2_dflt,
1445 .parent = &core_ck, /* Core or sys */ 1442 .parent = &core_ck, /* Core or sys */
1446 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1443 .flags = DELAYED_APP,
1447 DELAYED_APP,
1448 .clkdm_name = "dss_clkdm", 1444 .clkdm_name = "dss_clkdm",
1449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1445 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1450 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 1446 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
@@ -1475,9 +1471,9 @@ static const struct clksel dss2_fck_clksel[] = {
1475 1471
1476static struct clk dss2_fck = { /* Alt clk used in power management */ 1472static struct clk dss2_fck = { /* Alt clk used in power management */
1477 .name = "dss2_fck", 1473 .name = "dss2_fck",
1474 .ops = &clkops_omap2_dflt,
1478 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ 1475 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1479 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1476 .flags = DELAYED_APP,
1480 DELAYED_APP,
1481 .clkdm_name = "dss_clkdm", 1477 .clkdm_name = "dss_clkdm",
1482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1478 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1483 .enable_bit = OMAP24XX_EN_DSS2_SHIFT, 1479 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
@@ -1490,8 +1486,8 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
1490 1486
1491static struct clk dss_54m_fck = { /* Alt clk used in power management */ 1487static struct clk dss_54m_fck = { /* Alt clk used in power management */
1492 .name = "dss_54m_fck", /* 54m tv clk */ 1488 .name = "dss_54m_fck", /* 54m tv clk */
1489 .ops = &clkops_omap2_dflt_wait,
1493 .parent = &func_54m_ck, 1490 .parent = &func_54m_ck,
1494 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1495 .clkdm_name = "dss_clkdm", 1491 .clkdm_name = "dss_clkdm",
1496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1492 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1497 .enable_bit = OMAP24XX_EN_TV_SHIFT, 1493 .enable_bit = OMAP24XX_EN_TV_SHIFT,
@@ -1518,8 +1514,8 @@ static const struct clksel omap24xx_gpt_clksel[] = {
1518 1514
1519static struct clk gpt1_ick = { 1515static struct clk gpt1_ick = {
1520 .name = "gpt1_ick", 1516 .name = "gpt1_ick",
1517 .ops = &clkops_omap2_dflt_wait,
1521 .parent = &l4_ck, 1518 .parent = &l4_ck,
1522 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1523 .clkdm_name = "core_l4_clkdm", 1519 .clkdm_name = "core_l4_clkdm",
1524 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1520 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1525 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 1521 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
@@ -1528,8 +1524,8 @@ static struct clk gpt1_ick = {
1528 1524
1529static struct clk gpt1_fck = { 1525static struct clk gpt1_fck = {
1530 .name = "gpt1_fck", 1526 .name = "gpt1_fck",
1527 .ops = &clkops_omap2_dflt_wait,
1531 .parent = &func_32k_ck, 1528 .parent = &func_32k_ck,
1532 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1533 .clkdm_name = "core_l4_clkdm", 1529 .clkdm_name = "core_l4_clkdm",
1534 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 1530 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1535 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 1531 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
@@ -1544,8 +1540,8 @@ static struct clk gpt1_fck = {
1544 1540
1545static struct clk gpt2_ick = { 1541static struct clk gpt2_ick = {
1546 .name = "gpt2_ick", 1542 .name = "gpt2_ick",
1543 .ops = &clkops_omap2_dflt_wait,
1547 .parent = &l4_ck, 1544 .parent = &l4_ck,
1548 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1549 .clkdm_name = "core_l4_clkdm", 1545 .clkdm_name = "core_l4_clkdm",
1550 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1546 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1551 .enable_bit = OMAP24XX_EN_GPT2_SHIFT, 1547 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
@@ -1554,8 +1550,8 @@ static struct clk gpt2_ick = {
1554 1550
1555static struct clk gpt2_fck = { 1551static struct clk gpt2_fck = {
1556 .name = "gpt2_fck", 1552 .name = "gpt2_fck",
1553 .ops = &clkops_omap2_dflt_wait,
1557 .parent = &func_32k_ck, 1554 .parent = &func_32k_ck,
1558 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1559 .clkdm_name = "core_l4_clkdm", 1555 .clkdm_name = "core_l4_clkdm",
1560 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1556 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1561 .enable_bit = OMAP24XX_EN_GPT2_SHIFT, 1557 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
@@ -1568,8 +1564,8 @@ static struct clk gpt2_fck = {
1568 1564
1569static struct clk gpt3_ick = { 1565static struct clk gpt3_ick = {
1570 .name = "gpt3_ick", 1566 .name = "gpt3_ick",
1567 .ops = &clkops_omap2_dflt_wait,
1571 .parent = &l4_ck, 1568 .parent = &l4_ck,
1572 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1573 .clkdm_name = "core_l4_clkdm", 1569 .clkdm_name = "core_l4_clkdm",
1574 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1570 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1575 .enable_bit = OMAP24XX_EN_GPT3_SHIFT, 1571 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
@@ -1578,8 +1574,8 @@ static struct clk gpt3_ick = {
1578 1574
1579static struct clk gpt3_fck = { 1575static struct clk gpt3_fck = {
1580 .name = "gpt3_fck", 1576 .name = "gpt3_fck",
1577 .ops = &clkops_omap2_dflt_wait,
1581 .parent = &func_32k_ck, 1578 .parent = &func_32k_ck,
1582 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1583 .clkdm_name = "core_l4_clkdm", 1579 .clkdm_name = "core_l4_clkdm",
1584 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1580 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1585 .enable_bit = OMAP24XX_EN_GPT3_SHIFT, 1581 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
@@ -1592,8 +1588,8 @@ static struct clk gpt3_fck = {
1592 1588
1593static struct clk gpt4_ick = { 1589static struct clk gpt4_ick = {
1594 .name = "gpt4_ick", 1590 .name = "gpt4_ick",
1591 .ops = &clkops_omap2_dflt_wait,
1595 .parent = &l4_ck, 1592 .parent = &l4_ck,
1596 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1597 .clkdm_name = "core_l4_clkdm", 1593 .clkdm_name = "core_l4_clkdm",
1598 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1594 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1599 .enable_bit = OMAP24XX_EN_GPT4_SHIFT, 1595 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
@@ -1602,8 +1598,8 @@ static struct clk gpt4_ick = {
1602 1598
1603static struct clk gpt4_fck = { 1599static struct clk gpt4_fck = {
1604 .name = "gpt4_fck", 1600 .name = "gpt4_fck",
1601 .ops = &clkops_omap2_dflt_wait,
1605 .parent = &func_32k_ck, 1602 .parent = &func_32k_ck,
1606 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1607 .clkdm_name = "core_l4_clkdm", 1603 .clkdm_name = "core_l4_clkdm",
1608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1604 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1609 .enable_bit = OMAP24XX_EN_GPT4_SHIFT, 1605 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
@@ -1616,8 +1612,8 @@ static struct clk gpt4_fck = {
1616 1612
1617static struct clk gpt5_ick = { 1613static struct clk gpt5_ick = {
1618 .name = "gpt5_ick", 1614 .name = "gpt5_ick",
1615 .ops = &clkops_omap2_dflt_wait,
1619 .parent = &l4_ck, 1616 .parent = &l4_ck,
1620 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1621 .clkdm_name = "core_l4_clkdm", 1617 .clkdm_name = "core_l4_clkdm",
1622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1618 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1623 .enable_bit = OMAP24XX_EN_GPT5_SHIFT, 1619 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
@@ -1626,8 +1622,8 @@ static struct clk gpt5_ick = {
1626 1622
1627static struct clk gpt5_fck = { 1623static struct clk gpt5_fck = {
1628 .name = "gpt5_fck", 1624 .name = "gpt5_fck",
1625 .ops = &clkops_omap2_dflt_wait,
1629 .parent = &func_32k_ck, 1626 .parent = &func_32k_ck,
1630 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1631 .clkdm_name = "core_l4_clkdm", 1627 .clkdm_name = "core_l4_clkdm",
1632 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1628 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1633 .enable_bit = OMAP24XX_EN_GPT5_SHIFT, 1629 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
@@ -1640,8 +1636,8 @@ static struct clk gpt5_fck = {
1640 1636
1641static struct clk gpt6_ick = { 1637static struct clk gpt6_ick = {
1642 .name = "gpt6_ick", 1638 .name = "gpt6_ick",
1639 .ops = &clkops_omap2_dflt_wait,
1643 .parent = &l4_ck, 1640 .parent = &l4_ck,
1644 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1645 .clkdm_name = "core_l4_clkdm", 1641 .clkdm_name = "core_l4_clkdm",
1646 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1642 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1647 .enable_bit = OMAP24XX_EN_GPT6_SHIFT, 1643 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
@@ -1650,8 +1646,8 @@ static struct clk gpt6_ick = {
1650 1646
1651static struct clk gpt6_fck = { 1647static struct clk gpt6_fck = {
1652 .name = "gpt6_fck", 1648 .name = "gpt6_fck",
1649 .ops = &clkops_omap2_dflt_wait,
1653 .parent = &func_32k_ck, 1650 .parent = &func_32k_ck,
1654 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1655 .clkdm_name = "core_l4_clkdm", 1651 .clkdm_name = "core_l4_clkdm",
1656 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1652 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1657 .enable_bit = OMAP24XX_EN_GPT6_SHIFT, 1653 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
@@ -1664,8 +1660,8 @@ static struct clk gpt6_fck = {
1664 1660
1665static struct clk gpt7_ick = { 1661static struct clk gpt7_ick = {
1666 .name = "gpt7_ick", 1662 .name = "gpt7_ick",
1663 .ops = &clkops_omap2_dflt_wait,
1667 .parent = &l4_ck, 1664 .parent = &l4_ck,
1668 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1669 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1670 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 1666 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1671 .recalc = &followparent_recalc, 1667 .recalc = &followparent_recalc,
@@ -1673,8 +1669,8 @@ static struct clk gpt7_ick = {
1673 1669
1674static struct clk gpt7_fck = { 1670static struct clk gpt7_fck = {
1675 .name = "gpt7_fck", 1671 .name = "gpt7_fck",
1672 .ops = &clkops_omap2_dflt_wait,
1676 .parent = &func_32k_ck, 1673 .parent = &func_32k_ck,
1677 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1678 .clkdm_name = "core_l4_clkdm", 1674 .clkdm_name = "core_l4_clkdm",
1679 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1675 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1680 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 1676 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
@@ -1687,8 +1683,8 @@ static struct clk gpt7_fck = {
1687 1683
1688static struct clk gpt8_ick = { 1684static struct clk gpt8_ick = {
1689 .name = "gpt8_ick", 1685 .name = "gpt8_ick",
1686 .ops = &clkops_omap2_dflt_wait,
1690 .parent = &l4_ck, 1687 .parent = &l4_ck,
1691 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1692 .clkdm_name = "core_l4_clkdm", 1688 .clkdm_name = "core_l4_clkdm",
1693 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1689 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1694 .enable_bit = OMAP24XX_EN_GPT8_SHIFT, 1690 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
@@ -1697,8 +1693,8 @@ static struct clk gpt8_ick = {
1697 1693
1698static struct clk gpt8_fck = { 1694static struct clk gpt8_fck = {
1699 .name = "gpt8_fck", 1695 .name = "gpt8_fck",
1696 .ops = &clkops_omap2_dflt_wait,
1700 .parent = &func_32k_ck, 1697 .parent = &func_32k_ck,
1701 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1702 .clkdm_name = "core_l4_clkdm", 1698 .clkdm_name = "core_l4_clkdm",
1703 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1699 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1704 .enable_bit = OMAP24XX_EN_GPT8_SHIFT, 1700 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
@@ -1711,8 +1707,8 @@ static struct clk gpt8_fck = {
1711 1707
1712static struct clk gpt9_ick = { 1708static struct clk gpt9_ick = {
1713 .name = "gpt9_ick", 1709 .name = "gpt9_ick",
1710 .ops = &clkops_omap2_dflt_wait,
1714 .parent = &l4_ck, 1711 .parent = &l4_ck,
1715 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1716 .clkdm_name = "core_l4_clkdm", 1712 .clkdm_name = "core_l4_clkdm",
1717 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1713 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1718 .enable_bit = OMAP24XX_EN_GPT9_SHIFT, 1714 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
@@ -1721,8 +1717,8 @@ static struct clk gpt9_ick = {
1721 1717
1722static struct clk gpt9_fck = { 1718static struct clk gpt9_fck = {
1723 .name = "gpt9_fck", 1719 .name = "gpt9_fck",
1720 .ops = &clkops_omap2_dflt_wait,
1724 .parent = &func_32k_ck, 1721 .parent = &func_32k_ck,
1725 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1726 .clkdm_name = "core_l4_clkdm", 1722 .clkdm_name = "core_l4_clkdm",
1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1723 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1728 .enable_bit = OMAP24XX_EN_GPT9_SHIFT, 1724 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
@@ -1735,8 +1731,8 @@ static struct clk gpt9_fck = {
1735 1731
1736static struct clk gpt10_ick = { 1732static struct clk gpt10_ick = {
1737 .name = "gpt10_ick", 1733 .name = "gpt10_ick",
1734 .ops = &clkops_omap2_dflt_wait,
1738 .parent = &l4_ck, 1735 .parent = &l4_ck,
1739 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1740 .clkdm_name = "core_l4_clkdm", 1736 .clkdm_name = "core_l4_clkdm",
1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1737 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1742 .enable_bit = OMAP24XX_EN_GPT10_SHIFT, 1738 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
@@ -1745,8 +1741,8 @@ static struct clk gpt10_ick = {
1745 1741
1746static struct clk gpt10_fck = { 1742static struct clk gpt10_fck = {
1747 .name = "gpt10_fck", 1743 .name = "gpt10_fck",
1744 .ops = &clkops_omap2_dflt_wait,
1748 .parent = &func_32k_ck, 1745 .parent = &func_32k_ck,
1749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1750 .clkdm_name = "core_l4_clkdm", 1746 .clkdm_name = "core_l4_clkdm",
1751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1752 .enable_bit = OMAP24XX_EN_GPT10_SHIFT, 1748 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
@@ -1759,8 +1755,8 @@ static struct clk gpt10_fck = {
1759 1755
1760static struct clk gpt11_ick = { 1756static struct clk gpt11_ick = {
1761 .name = "gpt11_ick", 1757 .name = "gpt11_ick",
1758 .ops = &clkops_omap2_dflt_wait,
1762 .parent = &l4_ck, 1759 .parent = &l4_ck,
1763 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1764 .clkdm_name = "core_l4_clkdm", 1760 .clkdm_name = "core_l4_clkdm",
1765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1761 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1766 .enable_bit = OMAP24XX_EN_GPT11_SHIFT, 1762 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
@@ -1769,8 +1765,8 @@ static struct clk gpt11_ick = {
1769 1765
1770static struct clk gpt11_fck = { 1766static struct clk gpt11_fck = {
1771 .name = "gpt11_fck", 1767 .name = "gpt11_fck",
1768 .ops = &clkops_omap2_dflt_wait,
1772 .parent = &func_32k_ck, 1769 .parent = &func_32k_ck,
1773 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1774 .clkdm_name = "core_l4_clkdm", 1770 .clkdm_name = "core_l4_clkdm",
1775 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1776 .enable_bit = OMAP24XX_EN_GPT11_SHIFT, 1772 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
@@ -1783,8 +1779,8 @@ static struct clk gpt11_fck = {
1783 1779
1784static struct clk gpt12_ick = { 1780static struct clk gpt12_ick = {
1785 .name = "gpt12_ick", 1781 .name = "gpt12_ick",
1782 .ops = &clkops_omap2_dflt_wait,
1786 .parent = &l4_ck, 1783 .parent = &l4_ck,
1787 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1788 .clkdm_name = "core_l4_clkdm", 1784 .clkdm_name = "core_l4_clkdm",
1789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1785 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1790 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1786 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
@@ -1793,8 +1789,8 @@ static struct clk gpt12_ick = {
1793 1789
1794static struct clk gpt12_fck = { 1790static struct clk gpt12_fck = {
1795 .name = "gpt12_fck", 1791 .name = "gpt12_fck",
1792 .ops = &clkops_omap2_dflt_wait,
1796 .parent = &func_32k_ck, 1793 .parent = &func_32k_ck,
1797 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1798 .clkdm_name = "core_l4_clkdm", 1794 .clkdm_name = "core_l4_clkdm",
1799 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1795 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1800 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1796 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
@@ -1807,9 +1803,9 @@ static struct clk gpt12_fck = {
1807 1803
1808static struct clk mcbsp1_ick = { 1804static struct clk mcbsp1_ick = {
1809 .name = "mcbsp_ick", 1805 .name = "mcbsp_ick",
1806 .ops = &clkops_omap2_dflt_wait,
1810 .id = 1, 1807 .id = 1,
1811 .parent = &l4_ck, 1808 .parent = &l4_ck,
1812 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1813 .clkdm_name = "core_l4_clkdm", 1809 .clkdm_name = "core_l4_clkdm",
1814 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1815 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1811 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
@@ -1818,9 +1814,9 @@ static struct clk mcbsp1_ick = {
1818 1814
1819static struct clk mcbsp1_fck = { 1815static struct clk mcbsp1_fck = {
1820 .name = "mcbsp_fck", 1816 .name = "mcbsp_fck",
1817 .ops = &clkops_omap2_dflt_wait,
1821 .id = 1, 1818 .id = 1,
1822 .parent = &func_96m_ck, 1819 .parent = &func_96m_ck,
1823 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1824 .clkdm_name = "core_l4_clkdm", 1820 .clkdm_name = "core_l4_clkdm",
1825 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1821 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1826 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1822 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
@@ -1829,9 +1825,9 @@ static struct clk mcbsp1_fck = {
1829 1825
1830static struct clk mcbsp2_ick = { 1826static struct clk mcbsp2_ick = {
1831 .name = "mcbsp_ick", 1827 .name = "mcbsp_ick",
1828 .ops = &clkops_omap2_dflt_wait,
1832 .id = 2, 1829 .id = 2,
1833 .parent = &l4_ck, 1830 .parent = &l4_ck,
1834 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1835 .clkdm_name = "core_l4_clkdm", 1831 .clkdm_name = "core_l4_clkdm",
1836 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1832 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1837 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1833 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
@@ -1840,9 +1836,9 @@ static struct clk mcbsp2_ick = {
1840 1836
1841static struct clk mcbsp2_fck = { 1837static struct clk mcbsp2_fck = {
1842 .name = "mcbsp_fck", 1838 .name = "mcbsp_fck",
1839 .ops = &clkops_omap2_dflt_wait,
1843 .id = 2, 1840 .id = 2,
1844 .parent = &func_96m_ck, 1841 .parent = &func_96m_ck,
1845 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1846 .clkdm_name = "core_l4_clkdm", 1842 .clkdm_name = "core_l4_clkdm",
1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1843 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1848 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1844 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
@@ -1851,9 +1847,9 @@ static struct clk mcbsp2_fck = {
1851 1847
1852static struct clk mcbsp3_ick = { 1848static struct clk mcbsp3_ick = {
1853 .name = "mcbsp_ick", 1849 .name = "mcbsp_ick",
1850 .ops = &clkops_omap2_dflt_wait,
1854 .id = 3, 1851 .id = 3,
1855 .parent = &l4_ck, 1852 .parent = &l4_ck,
1856 .flags = CLOCK_IN_OMAP243X,
1857 .clkdm_name = "core_l4_clkdm", 1853 .clkdm_name = "core_l4_clkdm",
1858 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1854 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1859 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, 1855 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
@@ -1862,9 +1858,9 @@ static struct clk mcbsp3_ick = {
1862 1858
1863static struct clk mcbsp3_fck = { 1859static struct clk mcbsp3_fck = {
1864 .name = "mcbsp_fck", 1860 .name = "mcbsp_fck",
1861 .ops = &clkops_omap2_dflt_wait,
1865 .id = 3, 1862 .id = 3,
1866 .parent = &func_96m_ck, 1863 .parent = &func_96m_ck,
1867 .flags = CLOCK_IN_OMAP243X,
1868 .clkdm_name = "core_l4_clkdm", 1864 .clkdm_name = "core_l4_clkdm",
1869 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1865 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1870 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, 1866 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
@@ -1873,9 +1869,9 @@ static struct clk mcbsp3_fck = {
1873 1869
1874static struct clk mcbsp4_ick = { 1870static struct clk mcbsp4_ick = {
1875 .name = "mcbsp_ick", 1871 .name = "mcbsp_ick",
1872 .ops = &clkops_omap2_dflt_wait,
1876 .id = 4, 1873 .id = 4,
1877 .parent = &l4_ck, 1874 .parent = &l4_ck,
1878 .flags = CLOCK_IN_OMAP243X,
1879 .clkdm_name = "core_l4_clkdm", 1875 .clkdm_name = "core_l4_clkdm",
1880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1876 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1881 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, 1877 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
@@ -1884,9 +1880,9 @@ static struct clk mcbsp4_ick = {
1884 1880
1885static struct clk mcbsp4_fck = { 1881static struct clk mcbsp4_fck = {
1886 .name = "mcbsp_fck", 1882 .name = "mcbsp_fck",
1883 .ops = &clkops_omap2_dflt_wait,
1887 .id = 4, 1884 .id = 4,
1888 .parent = &func_96m_ck, 1885 .parent = &func_96m_ck,
1889 .flags = CLOCK_IN_OMAP243X,
1890 .clkdm_name = "core_l4_clkdm", 1886 .clkdm_name = "core_l4_clkdm",
1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1887 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1892 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, 1888 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
@@ -1895,9 +1891,9 @@ static struct clk mcbsp4_fck = {
1895 1891
1896static struct clk mcbsp5_ick = { 1892static struct clk mcbsp5_ick = {
1897 .name = "mcbsp_ick", 1893 .name = "mcbsp_ick",
1894 .ops = &clkops_omap2_dflt_wait,
1898 .id = 5, 1895 .id = 5,
1899 .parent = &l4_ck, 1896 .parent = &l4_ck,
1900 .flags = CLOCK_IN_OMAP243X,
1901 .clkdm_name = "core_l4_clkdm", 1897 .clkdm_name = "core_l4_clkdm",
1902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1898 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1903 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, 1899 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
@@ -1906,9 +1902,9 @@ static struct clk mcbsp5_ick = {
1906 1902
1907static struct clk mcbsp5_fck = { 1903static struct clk mcbsp5_fck = {
1908 .name = "mcbsp_fck", 1904 .name = "mcbsp_fck",
1905 .ops = &clkops_omap2_dflt_wait,
1909 .id = 5, 1906 .id = 5,
1910 .parent = &func_96m_ck, 1907 .parent = &func_96m_ck,
1911 .flags = CLOCK_IN_OMAP243X,
1912 .clkdm_name = "core_l4_clkdm", 1908 .clkdm_name = "core_l4_clkdm",
1913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1909 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1914 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, 1910 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
@@ -1917,10 +1913,10 @@ static struct clk mcbsp5_fck = {
1917 1913
1918static struct clk mcspi1_ick = { 1914static struct clk mcspi1_ick = {
1919 .name = "mcspi_ick", 1915 .name = "mcspi_ick",
1916 .ops = &clkops_omap2_dflt_wait,
1920 .id = 1, 1917 .id = 1,
1921 .parent = &l4_ck, 1918 .parent = &l4_ck,
1922 .clkdm_name = "core_l4_clkdm", 1919 .clkdm_name = "core_l4_clkdm",
1923 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1924 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1920 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1925 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1921 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1926 .recalc = &followparent_recalc, 1922 .recalc = &followparent_recalc,
@@ -1928,9 +1924,9 @@ static struct clk mcspi1_ick = {
1928 1924
1929static struct clk mcspi1_fck = { 1925static struct clk mcspi1_fck = {
1930 .name = "mcspi_fck", 1926 .name = "mcspi_fck",
1927 .ops = &clkops_omap2_dflt_wait,
1931 .id = 1, 1928 .id = 1,
1932 .parent = &func_48m_ck, 1929 .parent = &func_48m_ck,
1933 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1934 .clkdm_name = "core_l4_clkdm", 1930 .clkdm_name = "core_l4_clkdm",
1935 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1936 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1932 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
@@ -1939,9 +1935,9 @@ static struct clk mcspi1_fck = {
1939 1935
1940static struct clk mcspi2_ick = { 1936static struct clk mcspi2_ick = {
1941 .name = "mcspi_ick", 1937 .name = "mcspi_ick",
1938 .ops = &clkops_omap2_dflt_wait,
1942 .id = 2, 1939 .id = 2,
1943 .parent = &l4_ck, 1940 .parent = &l4_ck,
1944 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1945 .clkdm_name = "core_l4_clkdm", 1941 .clkdm_name = "core_l4_clkdm",
1946 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1942 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1947 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1943 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
@@ -1950,9 +1946,9 @@ static struct clk mcspi2_ick = {
1950 1946
1951static struct clk mcspi2_fck = { 1947static struct clk mcspi2_fck = {
1952 .name = "mcspi_fck", 1948 .name = "mcspi_fck",
1949 .ops = &clkops_omap2_dflt_wait,
1953 .id = 2, 1950 .id = 2,
1954 .parent = &func_48m_ck, 1951 .parent = &func_48m_ck,
1955 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1956 .clkdm_name = "core_l4_clkdm", 1952 .clkdm_name = "core_l4_clkdm",
1957 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1953 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1958 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1954 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
@@ -1961,9 +1957,9 @@ static struct clk mcspi2_fck = {
1961 1957
1962static struct clk mcspi3_ick = { 1958static struct clk mcspi3_ick = {
1963 .name = "mcspi_ick", 1959 .name = "mcspi_ick",
1960 .ops = &clkops_omap2_dflt_wait,
1964 .id = 3, 1961 .id = 3,
1965 .parent = &l4_ck, 1962 .parent = &l4_ck,
1966 .flags = CLOCK_IN_OMAP243X,
1967 .clkdm_name = "core_l4_clkdm", 1963 .clkdm_name = "core_l4_clkdm",
1968 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1964 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1969 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, 1965 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
@@ -1972,9 +1968,9 @@ static struct clk mcspi3_ick = {
1972 1968
1973static struct clk mcspi3_fck = { 1969static struct clk mcspi3_fck = {
1974 .name = "mcspi_fck", 1970 .name = "mcspi_fck",
1971 .ops = &clkops_omap2_dflt_wait,
1975 .id = 3, 1972 .id = 3,
1976 .parent = &func_48m_ck, 1973 .parent = &func_48m_ck,
1977 .flags = CLOCK_IN_OMAP243X,
1978 .clkdm_name = "core_l4_clkdm", 1974 .clkdm_name = "core_l4_clkdm",
1979 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1975 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1980 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, 1976 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
@@ -1983,8 +1979,8 @@ static struct clk mcspi3_fck = {
1983 1979
1984static struct clk uart1_ick = { 1980static struct clk uart1_ick = {
1985 .name = "uart1_ick", 1981 .name = "uart1_ick",
1982 .ops = &clkops_omap2_dflt_wait,
1986 .parent = &l4_ck, 1983 .parent = &l4_ck,
1987 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1988 .clkdm_name = "core_l4_clkdm", 1984 .clkdm_name = "core_l4_clkdm",
1989 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1985 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1990 .enable_bit = OMAP24XX_EN_UART1_SHIFT, 1986 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
@@ -1993,8 +1989,8 @@ static struct clk uart1_ick = {
1993 1989
1994static struct clk uart1_fck = { 1990static struct clk uart1_fck = {
1995 .name = "uart1_fck", 1991 .name = "uart1_fck",
1992 .ops = &clkops_omap2_dflt_wait,
1996 .parent = &func_48m_ck, 1993 .parent = &func_48m_ck,
1997 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1998 .clkdm_name = "core_l4_clkdm", 1994 .clkdm_name = "core_l4_clkdm",
1999 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1995 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2000 .enable_bit = OMAP24XX_EN_UART1_SHIFT, 1996 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
@@ -2003,8 +1999,8 @@ static struct clk uart1_fck = {
2003 1999
2004static struct clk uart2_ick = { 2000static struct clk uart2_ick = {
2005 .name = "uart2_ick", 2001 .name = "uart2_ick",
2002 .ops = &clkops_omap2_dflt_wait,
2006 .parent = &l4_ck, 2003 .parent = &l4_ck,
2007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2008 .clkdm_name = "core_l4_clkdm", 2004 .clkdm_name = "core_l4_clkdm",
2009 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2005 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2010 .enable_bit = OMAP24XX_EN_UART2_SHIFT, 2006 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
@@ -2013,8 +2009,8 @@ static struct clk uart2_ick = {
2013 2009
2014static struct clk uart2_fck = { 2010static struct clk uart2_fck = {
2015 .name = "uart2_fck", 2011 .name = "uart2_fck",
2012 .ops = &clkops_omap2_dflt_wait,
2016 .parent = &func_48m_ck, 2013 .parent = &func_48m_ck,
2017 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2018 .clkdm_name = "core_l4_clkdm", 2014 .clkdm_name = "core_l4_clkdm",
2019 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2015 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2020 .enable_bit = OMAP24XX_EN_UART2_SHIFT, 2016 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
@@ -2023,8 +2019,8 @@ static struct clk uart2_fck = {
2023 2019
2024static struct clk uart3_ick = { 2020static struct clk uart3_ick = {
2025 .name = "uart3_ick", 2021 .name = "uart3_ick",
2022 .ops = &clkops_omap2_dflt_wait,
2026 .parent = &l4_ck, 2023 .parent = &l4_ck,
2027 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2028 .clkdm_name = "core_l4_clkdm", 2024 .clkdm_name = "core_l4_clkdm",
2029 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2025 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2030 .enable_bit = OMAP24XX_EN_UART3_SHIFT, 2026 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
@@ -2033,8 +2029,8 @@ static struct clk uart3_ick = {
2033 2029
2034static struct clk uart3_fck = { 2030static struct clk uart3_fck = {
2035 .name = "uart3_fck", 2031 .name = "uart3_fck",
2032 .ops = &clkops_omap2_dflt_wait,
2036 .parent = &func_48m_ck, 2033 .parent = &func_48m_ck,
2037 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2038 .clkdm_name = "core_l4_clkdm", 2034 .clkdm_name = "core_l4_clkdm",
2039 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2035 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2040 .enable_bit = OMAP24XX_EN_UART3_SHIFT, 2036 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
@@ -2043,8 +2039,8 @@ static struct clk uart3_fck = {
2043 2039
2044static struct clk gpios_ick = { 2040static struct clk gpios_ick = {
2045 .name = "gpios_ick", 2041 .name = "gpios_ick",
2042 .ops = &clkops_omap2_dflt_wait,
2046 .parent = &l4_ck, 2043 .parent = &l4_ck,
2047 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2048 .clkdm_name = "core_l4_clkdm", 2044 .clkdm_name = "core_l4_clkdm",
2049 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2045 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2050 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 2046 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
@@ -2053,8 +2049,8 @@ static struct clk gpios_ick = {
2053 2049
2054static struct clk gpios_fck = { 2050static struct clk gpios_fck = {
2055 .name = "gpios_fck", 2051 .name = "gpios_fck",
2052 .ops = &clkops_omap2_dflt_wait,
2056 .parent = &func_32k_ck, 2053 .parent = &func_32k_ck,
2057 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2058 .clkdm_name = "wkup_clkdm", 2054 .clkdm_name = "wkup_clkdm",
2059 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2055 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2060 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 2056 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
@@ -2063,8 +2059,8 @@ static struct clk gpios_fck = {
2063 2059
2064static struct clk mpu_wdt_ick = { 2060static struct clk mpu_wdt_ick = {
2065 .name = "mpu_wdt_ick", 2061 .name = "mpu_wdt_ick",
2062 .ops = &clkops_omap2_dflt_wait,
2066 .parent = &l4_ck, 2063 .parent = &l4_ck,
2067 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2068 .clkdm_name = "core_l4_clkdm", 2064 .clkdm_name = "core_l4_clkdm",
2069 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2065 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2070 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 2066 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
@@ -2073,8 +2069,8 @@ static struct clk mpu_wdt_ick = {
2073 2069
2074static struct clk mpu_wdt_fck = { 2070static struct clk mpu_wdt_fck = {
2075 .name = "mpu_wdt_fck", 2071 .name = "mpu_wdt_fck",
2072 .ops = &clkops_omap2_dflt_wait,
2076 .parent = &func_32k_ck, 2073 .parent = &func_32k_ck,
2077 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2078 .clkdm_name = "wkup_clkdm", 2074 .clkdm_name = "wkup_clkdm",
2079 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2075 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2080 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 2076 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
@@ -2083,9 +2079,9 @@ static struct clk mpu_wdt_fck = {
2083 2079
2084static struct clk sync_32k_ick = { 2080static struct clk sync_32k_ick = {
2085 .name = "sync_32k_ick", 2081 .name = "sync_32k_ick",
2082 .ops = &clkops_omap2_dflt_wait,
2086 .parent = &l4_ck, 2083 .parent = &l4_ck,
2087 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2084 .flags = ENABLE_ON_INIT,
2088 ENABLE_ON_INIT,
2089 .clkdm_name = "core_l4_clkdm", 2085 .clkdm_name = "core_l4_clkdm",
2090 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2086 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2091 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, 2087 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
@@ -2094,8 +2090,8 @@ static struct clk sync_32k_ick = {
2094 2090
2095static struct clk wdt1_ick = { 2091static struct clk wdt1_ick = {
2096 .name = "wdt1_ick", 2092 .name = "wdt1_ick",
2093 .ops = &clkops_omap2_dflt_wait,
2097 .parent = &l4_ck, 2094 .parent = &l4_ck,
2098 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2099 .clkdm_name = "core_l4_clkdm", 2095 .clkdm_name = "core_l4_clkdm",
2100 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2096 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2101 .enable_bit = OMAP24XX_EN_WDT1_SHIFT, 2097 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
@@ -2104,9 +2100,9 @@ static struct clk wdt1_ick = {
2104 2100
2105static struct clk omapctrl_ick = { 2101static struct clk omapctrl_ick = {
2106 .name = "omapctrl_ick", 2102 .name = "omapctrl_ick",
2103 .ops = &clkops_omap2_dflt_wait,
2107 .parent = &l4_ck, 2104 .parent = &l4_ck,
2108 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2105 .flags = ENABLE_ON_INIT,
2109 ENABLE_ON_INIT,
2110 .clkdm_name = "core_l4_clkdm", 2106 .clkdm_name = "core_l4_clkdm",
2111 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2107 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2112 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, 2108 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
@@ -2115,8 +2111,8 @@ static struct clk omapctrl_ick = {
2115 2111
2116static struct clk icr_ick = { 2112static struct clk icr_ick = {
2117 .name = "icr_ick", 2113 .name = "icr_ick",
2114 .ops = &clkops_omap2_dflt_wait,
2118 .parent = &l4_ck, 2115 .parent = &l4_ck,
2119 .flags = CLOCK_IN_OMAP243X,
2120 .clkdm_name = "core_l4_clkdm", 2116 .clkdm_name = "core_l4_clkdm",
2121 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2117 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2122 .enable_bit = OMAP2430_EN_ICR_SHIFT, 2118 .enable_bit = OMAP2430_EN_ICR_SHIFT,
@@ -2125,8 +2121,8 @@ static struct clk icr_ick = {
2125 2121
2126static struct clk cam_ick = { 2122static struct clk cam_ick = {
2127 .name = "cam_ick", 2123 .name = "cam_ick",
2124 .ops = &clkops_omap2_dflt,
2128 .parent = &l4_ck, 2125 .parent = &l4_ck,
2129 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2130 .clkdm_name = "core_l4_clkdm", 2126 .clkdm_name = "core_l4_clkdm",
2131 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2127 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2132 .enable_bit = OMAP24XX_EN_CAM_SHIFT, 2128 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
@@ -2140,8 +2136,8 @@ static struct clk cam_ick = {
2140 */ 2136 */
2141static struct clk cam_fck = { 2137static struct clk cam_fck = {
2142 .name = "cam_fck", 2138 .name = "cam_fck",
2139 .ops = &clkops_omap2_dflt,
2143 .parent = &func_96m_ck, 2140 .parent = &func_96m_ck,
2144 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2145 .clkdm_name = "core_l3_clkdm", 2141 .clkdm_name = "core_l3_clkdm",
2146 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2142 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2147 .enable_bit = OMAP24XX_EN_CAM_SHIFT, 2143 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
@@ -2150,8 +2146,8 @@ static struct clk cam_fck = {
2150 2146
2151static struct clk mailboxes_ick = { 2147static struct clk mailboxes_ick = {
2152 .name = "mailboxes_ick", 2148 .name = "mailboxes_ick",
2149 .ops = &clkops_omap2_dflt_wait,
2153 .parent = &l4_ck, 2150 .parent = &l4_ck,
2154 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2155 .clkdm_name = "core_l4_clkdm", 2151 .clkdm_name = "core_l4_clkdm",
2156 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2152 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2157 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, 2153 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
@@ -2160,8 +2156,8 @@ static struct clk mailboxes_ick = {
2160 2156
2161static struct clk wdt4_ick = { 2157static struct clk wdt4_ick = {
2162 .name = "wdt4_ick", 2158 .name = "wdt4_ick",
2159 .ops = &clkops_omap2_dflt_wait,
2163 .parent = &l4_ck, 2160 .parent = &l4_ck,
2164 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2165 .clkdm_name = "core_l4_clkdm", 2161 .clkdm_name = "core_l4_clkdm",
2166 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2162 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2167 .enable_bit = OMAP24XX_EN_WDT4_SHIFT, 2163 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
@@ -2170,8 +2166,8 @@ static struct clk wdt4_ick = {
2170 2166
2171static struct clk wdt4_fck = { 2167static struct clk wdt4_fck = {
2172 .name = "wdt4_fck", 2168 .name = "wdt4_fck",
2169 .ops = &clkops_omap2_dflt_wait,
2173 .parent = &func_32k_ck, 2170 .parent = &func_32k_ck,
2174 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2175 .clkdm_name = "core_l4_clkdm", 2171 .clkdm_name = "core_l4_clkdm",
2176 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2172 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2177 .enable_bit = OMAP24XX_EN_WDT4_SHIFT, 2173 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
@@ -2180,8 +2176,8 @@ static struct clk wdt4_fck = {
2180 2176
2181static struct clk wdt3_ick = { 2177static struct clk wdt3_ick = {
2182 .name = "wdt3_ick", 2178 .name = "wdt3_ick",
2179 .ops = &clkops_omap2_dflt_wait,
2183 .parent = &l4_ck, 2180 .parent = &l4_ck,
2184 .flags = CLOCK_IN_OMAP242X,
2185 .clkdm_name = "core_l4_clkdm", 2181 .clkdm_name = "core_l4_clkdm",
2186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2182 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2187 .enable_bit = OMAP2420_EN_WDT3_SHIFT, 2183 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
@@ -2190,8 +2186,8 @@ static struct clk wdt3_ick = {
2190 2186
2191static struct clk wdt3_fck = { 2187static struct clk wdt3_fck = {
2192 .name = "wdt3_fck", 2188 .name = "wdt3_fck",
2189 .ops = &clkops_omap2_dflt_wait,
2193 .parent = &func_32k_ck, 2190 .parent = &func_32k_ck,
2194 .flags = CLOCK_IN_OMAP242X,
2195 .clkdm_name = "core_l4_clkdm", 2191 .clkdm_name = "core_l4_clkdm",
2196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2192 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2197 .enable_bit = OMAP2420_EN_WDT3_SHIFT, 2193 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
@@ -2200,8 +2196,8 @@ static struct clk wdt3_fck = {
2200 2196
2201static struct clk mspro_ick = { 2197static struct clk mspro_ick = {
2202 .name = "mspro_ick", 2198 .name = "mspro_ick",
2199 .ops = &clkops_omap2_dflt_wait,
2203 .parent = &l4_ck, 2200 .parent = &l4_ck,
2204 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2205 .clkdm_name = "core_l4_clkdm", 2201 .clkdm_name = "core_l4_clkdm",
2206 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2202 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2207 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, 2203 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
@@ -2210,8 +2206,8 @@ static struct clk mspro_ick = {
2210 2206
2211static struct clk mspro_fck = { 2207static struct clk mspro_fck = {
2212 .name = "mspro_fck", 2208 .name = "mspro_fck",
2209 .ops = &clkops_omap2_dflt_wait,
2213 .parent = &func_96m_ck, 2210 .parent = &func_96m_ck,
2214 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2215 .clkdm_name = "core_l4_clkdm", 2211 .clkdm_name = "core_l4_clkdm",
2216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2212 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2217 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, 2213 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
@@ -2220,8 +2216,8 @@ static struct clk mspro_fck = {
2220 2216
2221static struct clk mmc_ick = { 2217static struct clk mmc_ick = {
2222 .name = "mmc_ick", 2218 .name = "mmc_ick",
2219 .ops = &clkops_omap2_dflt_wait,
2223 .parent = &l4_ck, 2220 .parent = &l4_ck,
2224 .flags = CLOCK_IN_OMAP242X,
2225 .clkdm_name = "core_l4_clkdm", 2221 .clkdm_name = "core_l4_clkdm",
2226 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2222 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2227 .enable_bit = OMAP2420_EN_MMC_SHIFT, 2223 .enable_bit = OMAP2420_EN_MMC_SHIFT,
@@ -2230,8 +2226,8 @@ static struct clk mmc_ick = {
2230 2226
2231static struct clk mmc_fck = { 2227static struct clk mmc_fck = {
2232 .name = "mmc_fck", 2228 .name = "mmc_fck",
2229 .ops = &clkops_omap2_dflt_wait,
2233 .parent = &func_96m_ck, 2230 .parent = &func_96m_ck,
2234 .flags = CLOCK_IN_OMAP242X,
2235 .clkdm_name = "core_l4_clkdm", 2231 .clkdm_name = "core_l4_clkdm",
2236 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2232 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2237 .enable_bit = OMAP2420_EN_MMC_SHIFT, 2233 .enable_bit = OMAP2420_EN_MMC_SHIFT,
@@ -2240,8 +2236,8 @@ static struct clk mmc_fck = {
2240 2236
2241static struct clk fac_ick = { 2237static struct clk fac_ick = {
2242 .name = "fac_ick", 2238 .name = "fac_ick",
2239 .ops = &clkops_omap2_dflt_wait,
2243 .parent = &l4_ck, 2240 .parent = &l4_ck,
2244 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2245 .clkdm_name = "core_l4_clkdm", 2241 .clkdm_name = "core_l4_clkdm",
2246 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2242 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2247 .enable_bit = OMAP24XX_EN_FAC_SHIFT, 2243 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
@@ -2250,8 +2246,8 @@ static struct clk fac_ick = {
2250 2246
2251static struct clk fac_fck = { 2247static struct clk fac_fck = {
2252 .name = "fac_fck", 2248 .name = "fac_fck",
2249 .ops = &clkops_omap2_dflt_wait,
2253 .parent = &func_12m_ck, 2250 .parent = &func_12m_ck,
2254 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2255 .clkdm_name = "core_l4_clkdm", 2251 .clkdm_name = "core_l4_clkdm",
2256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2252 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2257 .enable_bit = OMAP24XX_EN_FAC_SHIFT, 2253 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
@@ -2260,8 +2256,8 @@ static struct clk fac_fck = {
2260 2256
2261static struct clk eac_ick = { 2257static struct clk eac_ick = {
2262 .name = "eac_ick", 2258 .name = "eac_ick",
2259 .ops = &clkops_omap2_dflt_wait,
2263 .parent = &l4_ck, 2260 .parent = &l4_ck,
2264 .flags = CLOCK_IN_OMAP242X,
2265 .clkdm_name = "core_l4_clkdm", 2261 .clkdm_name = "core_l4_clkdm",
2266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2262 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2267 .enable_bit = OMAP2420_EN_EAC_SHIFT, 2263 .enable_bit = OMAP2420_EN_EAC_SHIFT,
@@ -2270,8 +2266,8 @@ static struct clk eac_ick = {
2270 2266
2271static struct clk eac_fck = { 2267static struct clk eac_fck = {
2272 .name = "eac_fck", 2268 .name = "eac_fck",
2269 .ops = &clkops_omap2_dflt_wait,
2273 .parent = &func_96m_ck, 2270 .parent = &func_96m_ck,
2274 .flags = CLOCK_IN_OMAP242X,
2275 .clkdm_name = "core_l4_clkdm", 2271 .clkdm_name = "core_l4_clkdm",
2276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2272 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2277 .enable_bit = OMAP2420_EN_EAC_SHIFT, 2273 .enable_bit = OMAP2420_EN_EAC_SHIFT,
@@ -2280,8 +2276,8 @@ static struct clk eac_fck = {
2280 2276
2281static struct clk hdq_ick = { 2277static struct clk hdq_ick = {
2282 .name = "hdq_ick", 2278 .name = "hdq_ick",
2279 .ops = &clkops_omap2_dflt_wait,
2283 .parent = &l4_ck, 2280 .parent = &l4_ck,
2284 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2285 .clkdm_name = "core_l4_clkdm", 2281 .clkdm_name = "core_l4_clkdm",
2286 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2282 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2287 .enable_bit = OMAP24XX_EN_HDQ_SHIFT, 2283 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
@@ -2290,8 +2286,8 @@ static struct clk hdq_ick = {
2290 2286
2291static struct clk hdq_fck = { 2287static struct clk hdq_fck = {
2292 .name = "hdq_fck", 2288 .name = "hdq_fck",
2289 .ops = &clkops_omap2_dflt_wait,
2293 .parent = &func_12m_ck, 2290 .parent = &func_12m_ck,
2294 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2295 .clkdm_name = "core_l4_clkdm", 2291 .clkdm_name = "core_l4_clkdm",
2296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2292 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2297 .enable_bit = OMAP24XX_EN_HDQ_SHIFT, 2293 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
@@ -2300,9 +2296,9 @@ static struct clk hdq_fck = {
2300 2296
2301static struct clk i2c2_ick = { 2297static struct clk i2c2_ick = {
2302 .name = "i2c_ick", 2298 .name = "i2c_ick",
2299 .ops = &clkops_omap2_dflt_wait,
2303 .id = 2, 2300 .id = 2,
2304 .parent = &l4_ck, 2301 .parent = &l4_ck,
2305 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2306 .clkdm_name = "core_l4_clkdm", 2302 .clkdm_name = "core_l4_clkdm",
2307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2303 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2308 .enable_bit = OMAP2420_EN_I2C2_SHIFT, 2304 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
@@ -2311,9 +2307,9 @@ static struct clk i2c2_ick = {
2311 2307
2312static struct clk i2c2_fck = { 2308static struct clk i2c2_fck = {
2313 .name = "i2c_fck", 2309 .name = "i2c_fck",
2310 .ops = &clkops_omap2_dflt_wait,
2314 .id = 2, 2311 .id = 2,
2315 .parent = &func_12m_ck, 2312 .parent = &func_12m_ck,
2316 .flags = CLOCK_IN_OMAP242X,
2317 .clkdm_name = "core_l4_clkdm", 2313 .clkdm_name = "core_l4_clkdm",
2318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2314 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2319 .enable_bit = OMAP2420_EN_I2C2_SHIFT, 2315 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
@@ -2322,9 +2318,9 @@ static struct clk i2c2_fck = {
2322 2318
2323static struct clk i2chs2_fck = { 2319static struct clk i2chs2_fck = {
2324 .name = "i2c_fck", 2320 .name = "i2c_fck",
2321 .ops = &clkops_omap2_dflt_wait,
2325 .id = 2, 2322 .id = 2,
2326 .parent = &func_96m_ck, 2323 .parent = &func_96m_ck,
2327 .flags = CLOCK_IN_OMAP243X,
2328 .clkdm_name = "core_l4_clkdm", 2324 .clkdm_name = "core_l4_clkdm",
2329 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2325 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2330 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, 2326 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
@@ -2333,9 +2329,9 @@ static struct clk i2chs2_fck = {
2333 2329
2334static struct clk i2c1_ick = { 2330static struct clk i2c1_ick = {
2335 .name = "i2c_ick", 2331 .name = "i2c_ick",
2332 .ops = &clkops_omap2_dflt_wait,
2336 .id = 1, 2333 .id = 1,
2337 .parent = &l4_ck, 2334 .parent = &l4_ck,
2338 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2339 .clkdm_name = "core_l4_clkdm", 2335 .clkdm_name = "core_l4_clkdm",
2340 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2336 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2341 .enable_bit = OMAP2420_EN_I2C1_SHIFT, 2337 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
@@ -2344,9 +2340,9 @@ static struct clk i2c1_ick = {
2344 2340
2345static struct clk i2c1_fck = { 2341static struct clk i2c1_fck = {
2346 .name = "i2c_fck", 2342 .name = "i2c_fck",
2343 .ops = &clkops_omap2_dflt_wait,
2347 .id = 1, 2344 .id = 1,
2348 .parent = &func_12m_ck, 2345 .parent = &func_12m_ck,
2349 .flags = CLOCK_IN_OMAP242X,
2350 .clkdm_name = "core_l4_clkdm", 2346 .clkdm_name = "core_l4_clkdm",
2351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2347 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2352 .enable_bit = OMAP2420_EN_I2C1_SHIFT, 2348 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
@@ -2355,9 +2351,9 @@ static struct clk i2c1_fck = {
2355 2351
2356static struct clk i2chs1_fck = { 2352static struct clk i2chs1_fck = {
2357 .name = "i2c_fck", 2353 .name = "i2c_fck",
2354 .ops = &clkops_omap2_dflt_wait,
2358 .id = 1, 2355 .id = 1,
2359 .parent = &func_96m_ck, 2356 .parent = &func_96m_ck,
2360 .flags = CLOCK_IN_OMAP243X,
2361 .clkdm_name = "core_l4_clkdm", 2357 .clkdm_name = "core_l4_clkdm",
2362 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2358 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2363 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, 2359 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
@@ -2366,33 +2362,33 @@ static struct clk i2chs1_fck = {
2366 2362
2367static struct clk gpmc_fck = { 2363static struct clk gpmc_fck = {
2368 .name = "gpmc_fck", 2364 .name = "gpmc_fck",
2365 .ops = &clkops_null, /* RMK: missing? */
2369 .parent = &core_l3_ck, 2366 .parent = &core_l3_ck,
2370 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2367 .flags = ENABLE_ON_INIT,
2371 ENABLE_ON_INIT,
2372 .clkdm_name = "core_l3_clkdm", 2368 .clkdm_name = "core_l3_clkdm",
2373 .recalc = &followparent_recalc, 2369 .recalc = &followparent_recalc,
2374}; 2370};
2375 2371
2376static struct clk sdma_fck = { 2372static struct clk sdma_fck = {
2377 .name = "sdma_fck", 2373 .name = "sdma_fck",
2374 .ops = &clkops_null, /* RMK: missing? */
2378 .parent = &core_l3_ck, 2375 .parent = &core_l3_ck,
2379 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2380 .clkdm_name = "core_l3_clkdm", 2376 .clkdm_name = "core_l3_clkdm",
2381 .recalc = &followparent_recalc, 2377 .recalc = &followparent_recalc,
2382}; 2378};
2383 2379
2384static struct clk sdma_ick = { 2380static struct clk sdma_ick = {
2385 .name = "sdma_ick", 2381 .name = "sdma_ick",
2382 .ops = &clkops_null, /* RMK: missing? */
2386 .parent = &l4_ck, 2383 .parent = &l4_ck,
2387 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2388 .clkdm_name = "core_l3_clkdm", 2384 .clkdm_name = "core_l3_clkdm",
2389 .recalc = &followparent_recalc, 2385 .recalc = &followparent_recalc,
2390}; 2386};
2391 2387
2392static struct clk vlynq_ick = { 2388static struct clk vlynq_ick = {
2393 .name = "vlynq_ick", 2389 .name = "vlynq_ick",
2390 .ops = &clkops_omap2_dflt_wait,
2394 .parent = &core_l3_ck, 2391 .parent = &core_l3_ck,
2395 .flags = CLOCK_IN_OMAP242X,
2396 .clkdm_name = "core_l3_clkdm", 2392 .clkdm_name = "core_l3_clkdm",
2397 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2393 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2398 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 2394 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
@@ -2426,8 +2422,9 @@ static const struct clksel vlynq_fck_clksel[] = {
2426 2422
2427static struct clk vlynq_fck = { 2423static struct clk vlynq_fck = {
2428 .name = "vlynq_fck", 2424 .name = "vlynq_fck",
2425 .ops = &clkops_omap2_dflt_wait,
2429 .parent = &func_96m_ck, 2426 .parent = &func_96m_ck,
2430 .flags = CLOCK_IN_OMAP242X | DELAYED_APP, 2427 .flags = DELAYED_APP,
2431 .clkdm_name = "core_l3_clkdm", 2428 .clkdm_name = "core_l3_clkdm",
2432 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2429 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2433 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 2430 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
@@ -2442,8 +2439,9 @@ static struct clk vlynq_fck = {
2442 2439
2443static struct clk sdrc_ick = { 2440static struct clk sdrc_ick = {
2444 .name = "sdrc_ick", 2441 .name = "sdrc_ick",
2442 .ops = &clkops_omap2_dflt_wait,
2445 .parent = &l4_ck, 2443 .parent = &l4_ck,
2446 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, 2444 .flags = ENABLE_ON_INIT,
2447 .clkdm_name = "core_l4_clkdm", 2445 .clkdm_name = "core_l4_clkdm",
2448 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 2446 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2449 .enable_bit = OMAP2430_EN_SDRC_SHIFT, 2447 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
@@ -2452,8 +2450,8 @@ static struct clk sdrc_ick = {
2452 2450
2453static struct clk des_ick = { 2451static struct clk des_ick = {
2454 .name = "des_ick", 2452 .name = "des_ick",
2453 .ops = &clkops_omap2_dflt_wait,
2455 .parent = &l4_ck, 2454 .parent = &l4_ck,
2456 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2457 .clkdm_name = "core_l4_clkdm", 2455 .clkdm_name = "core_l4_clkdm",
2458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2456 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2459 .enable_bit = OMAP24XX_EN_DES_SHIFT, 2457 .enable_bit = OMAP24XX_EN_DES_SHIFT,
@@ -2462,8 +2460,8 @@ static struct clk des_ick = {
2462 2460
2463static struct clk sha_ick = { 2461static struct clk sha_ick = {
2464 .name = "sha_ick", 2462 .name = "sha_ick",
2463 .ops = &clkops_omap2_dflt_wait,
2465 .parent = &l4_ck, 2464 .parent = &l4_ck,
2466 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2467 .clkdm_name = "core_l4_clkdm", 2465 .clkdm_name = "core_l4_clkdm",
2468 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2466 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2469 .enable_bit = OMAP24XX_EN_SHA_SHIFT, 2467 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
@@ -2472,8 +2470,8 @@ static struct clk sha_ick = {
2472 2470
2473static struct clk rng_ick = { 2471static struct clk rng_ick = {
2474 .name = "rng_ick", 2472 .name = "rng_ick",
2473 .ops = &clkops_omap2_dflt_wait,
2475 .parent = &l4_ck, 2474 .parent = &l4_ck,
2476 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2477 .clkdm_name = "core_l4_clkdm", 2475 .clkdm_name = "core_l4_clkdm",
2478 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2476 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2479 .enable_bit = OMAP24XX_EN_RNG_SHIFT, 2477 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
@@ -2482,8 +2480,8 @@ static struct clk rng_ick = {
2482 2480
2483static struct clk aes_ick = { 2481static struct clk aes_ick = {
2484 .name = "aes_ick", 2482 .name = "aes_ick",
2483 .ops = &clkops_omap2_dflt_wait,
2485 .parent = &l4_ck, 2484 .parent = &l4_ck,
2486 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2487 .clkdm_name = "core_l4_clkdm", 2485 .clkdm_name = "core_l4_clkdm",
2488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2486 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2489 .enable_bit = OMAP24XX_EN_AES_SHIFT, 2487 .enable_bit = OMAP24XX_EN_AES_SHIFT,
@@ -2492,8 +2490,8 @@ static struct clk aes_ick = {
2492 2490
2493static struct clk pka_ick = { 2491static struct clk pka_ick = {
2494 .name = "pka_ick", 2492 .name = "pka_ick",
2493 .ops = &clkops_omap2_dflt_wait,
2495 .parent = &l4_ck, 2494 .parent = &l4_ck,
2496 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2497 .clkdm_name = "core_l4_clkdm", 2495 .clkdm_name = "core_l4_clkdm",
2498 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2499 .enable_bit = OMAP24XX_EN_PKA_SHIFT, 2497 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
@@ -2502,8 +2500,8 @@ static struct clk pka_ick = {
2502 2500
2503static struct clk usb_fck = { 2501static struct clk usb_fck = {
2504 .name = "usb_fck", 2502 .name = "usb_fck",
2503 .ops = &clkops_omap2_dflt_wait,
2505 .parent = &func_48m_ck, 2504 .parent = &func_48m_ck,
2506 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2507 .clkdm_name = "core_l3_clkdm", 2505 .clkdm_name = "core_l3_clkdm",
2508 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2506 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2509 .enable_bit = OMAP24XX_EN_USB_SHIFT, 2507 .enable_bit = OMAP24XX_EN_USB_SHIFT,
@@ -2512,8 +2510,8 @@ static struct clk usb_fck = {
2512 2510
2513static struct clk usbhs_ick = { 2511static struct clk usbhs_ick = {
2514 .name = "usbhs_ick", 2512 .name = "usbhs_ick",
2513 .ops = &clkops_omap2_dflt_wait,
2515 .parent = &core_l3_ck, 2514 .parent = &core_l3_ck,
2516 .flags = CLOCK_IN_OMAP243X,
2517 .clkdm_name = "core_l3_clkdm", 2515 .clkdm_name = "core_l3_clkdm",
2518 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2516 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2519 .enable_bit = OMAP2430_EN_USBHS_SHIFT, 2517 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
@@ -2522,8 +2520,8 @@ static struct clk usbhs_ick = {
2522 2520
2523static struct clk mmchs1_ick = { 2521static struct clk mmchs1_ick = {
2524 .name = "mmchs_ick", 2522 .name = "mmchs_ick",
2523 .ops = &clkops_omap2_dflt_wait,
2525 .parent = &l4_ck, 2524 .parent = &l4_ck,
2526 .flags = CLOCK_IN_OMAP243X,
2527 .clkdm_name = "core_l4_clkdm", 2525 .clkdm_name = "core_l4_clkdm",
2528 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2526 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2529 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 2527 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
@@ -2532,8 +2530,8 @@ static struct clk mmchs1_ick = {
2532 2530
2533static struct clk mmchs1_fck = { 2531static struct clk mmchs1_fck = {
2534 .name = "mmchs_fck", 2532 .name = "mmchs_fck",
2533 .ops = &clkops_omap2_dflt_wait,
2535 .parent = &func_96m_ck, 2534 .parent = &func_96m_ck,
2536 .flags = CLOCK_IN_OMAP243X,
2537 .clkdm_name = "core_l3_clkdm", 2535 .clkdm_name = "core_l3_clkdm",
2538 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2536 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2539 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 2537 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
@@ -2542,9 +2540,9 @@ static struct clk mmchs1_fck = {
2542 2540
2543static struct clk mmchs2_ick = { 2541static struct clk mmchs2_ick = {
2544 .name = "mmchs_ick", 2542 .name = "mmchs_ick",
2543 .ops = &clkops_omap2_dflt_wait,
2545 .id = 1, 2544 .id = 1,
2546 .parent = &l4_ck, 2545 .parent = &l4_ck,
2547 .flags = CLOCK_IN_OMAP243X,
2548 .clkdm_name = "core_l4_clkdm", 2546 .clkdm_name = "core_l4_clkdm",
2549 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2547 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2550 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, 2548 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
@@ -2553,9 +2551,9 @@ static struct clk mmchs2_ick = {
2553 2551
2554static struct clk mmchs2_fck = { 2552static struct clk mmchs2_fck = {
2555 .name = "mmchs_fck", 2553 .name = "mmchs_fck",
2554 .ops = &clkops_omap2_dflt_wait,
2556 .id = 1, 2555 .id = 1,
2557 .parent = &func_96m_ck, 2556 .parent = &func_96m_ck,
2558 .flags = CLOCK_IN_OMAP243X,
2559 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2557 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2560 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, 2558 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2561 .recalc = &followparent_recalc, 2559 .recalc = &followparent_recalc,
@@ -2563,8 +2561,8 @@ static struct clk mmchs2_fck = {
2563 2561
2564static struct clk gpio5_ick = { 2562static struct clk gpio5_ick = {
2565 .name = "gpio5_ick", 2563 .name = "gpio5_ick",
2564 .ops = &clkops_omap2_dflt_wait,
2566 .parent = &l4_ck, 2565 .parent = &l4_ck,
2567 .flags = CLOCK_IN_OMAP243X,
2568 .clkdm_name = "core_l4_clkdm", 2566 .clkdm_name = "core_l4_clkdm",
2569 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2567 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2570 .enable_bit = OMAP2430_EN_GPIO5_SHIFT, 2568 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
@@ -2573,8 +2571,8 @@ static struct clk gpio5_ick = {
2573 2571
2574static struct clk gpio5_fck = { 2572static struct clk gpio5_fck = {
2575 .name = "gpio5_fck", 2573 .name = "gpio5_fck",
2574 .ops = &clkops_omap2_dflt_wait,
2576 .parent = &func_32k_ck, 2575 .parent = &func_32k_ck,
2577 .flags = CLOCK_IN_OMAP243X,
2578 .clkdm_name = "core_l4_clkdm", 2576 .clkdm_name = "core_l4_clkdm",
2579 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2577 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2580 .enable_bit = OMAP2430_EN_GPIO5_SHIFT, 2578 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
@@ -2583,8 +2581,8 @@ static struct clk gpio5_fck = {
2583 2581
2584static struct clk mdm_intc_ick = { 2582static struct clk mdm_intc_ick = {
2585 .name = "mdm_intc_ick", 2583 .name = "mdm_intc_ick",
2584 .ops = &clkops_omap2_dflt_wait,
2586 .parent = &l4_ck, 2585 .parent = &l4_ck,
2587 .flags = CLOCK_IN_OMAP243X,
2588 .clkdm_name = "core_l4_clkdm", 2586 .clkdm_name = "core_l4_clkdm",
2589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2587 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2590 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, 2588 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
@@ -2593,8 +2591,8 @@ static struct clk mdm_intc_ick = {
2593 2591
2594static struct clk mmchsdb1_fck = { 2592static struct clk mmchsdb1_fck = {
2595 .name = "mmchsdb_fck", 2593 .name = "mmchsdb_fck",
2594 .ops = &clkops_omap2_dflt_wait,
2596 .parent = &func_32k_ck, 2595 .parent = &func_32k_ck,
2597 .flags = CLOCK_IN_OMAP243X,
2598 .clkdm_name = "core_l4_clkdm", 2596 .clkdm_name = "core_l4_clkdm",
2599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2597 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2600 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, 2598 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
@@ -2603,9 +2601,9 @@ static struct clk mmchsdb1_fck = {
2603 2601
2604static struct clk mmchsdb2_fck = { 2602static struct clk mmchsdb2_fck = {
2605 .name = "mmchsdb_fck", 2603 .name = "mmchsdb_fck",
2604 .ops = &clkops_omap2_dflt_wait,
2606 .id = 1, 2605 .id = 1,
2607 .parent = &func_32k_ck, 2606 .parent = &func_32k_ck,
2608 .flags = CLOCK_IN_OMAP243X,
2609 .clkdm_name = "core_l4_clkdm", 2607 .clkdm_name = "core_l4_clkdm",
2610 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2611 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, 2609 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
@@ -2628,166 +2626,13 @@ static struct clk mmchsdb2_fck = {
2628 */ 2626 */
2629static struct clk virt_prcm_set = { 2627static struct clk virt_prcm_set = {
2630 .name = "virt_prcm_set", 2628 .name = "virt_prcm_set",
2631 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2629 .ops = &clkops_null,
2632 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP, 2630 .flags = DELAYED_APP,
2633 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ 2631 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2634 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ 2632 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2635 .set_rate = &omap2_select_table_rate, 2633 .set_rate = &omap2_select_table_rate,
2636 .round_rate = &omap2_round_to_table_rate, 2634 .round_rate = &omap2_round_to_table_rate,
2637}; 2635};
2638 2636
2639static struct clk *onchip_24xx_clks[] __initdata = {
2640 /* external root sources */
2641 &func_32k_ck,
2642 &osc_ck,
2643 &sys_ck,
2644 &alt_ck,
2645 /* internal analog sources */
2646 &dpll_ck,
2647 &apll96_ck,
2648 &apll54_ck,
2649 /* internal prcm root sources */
2650 &func_54m_ck,
2651 &core_ck,
2652 &func_96m_ck,
2653 &func_48m_ck,
2654 &func_12m_ck,
2655 &wdt1_osc_ck,
2656 &sys_clkout_src,
2657 &sys_clkout,
2658 &sys_clkout2_src,
2659 &sys_clkout2,
2660 &emul_ck,
2661 /* mpu domain clocks */
2662 &mpu_ck,
2663 /* dsp domain clocks */
2664 &dsp_fck,
2665 &dsp_irate_ick,
2666 &dsp_ick, /* 242x */
2667 &iva2_1_ick, /* 243x */
2668 &iva1_ifck, /* 242x */
2669 &iva1_mpu_int_ifck, /* 242x */
2670 /* GFX domain clocks */
2671 &gfx_3d_fck,
2672 &gfx_2d_fck,
2673 &gfx_ick,
2674 /* Modem domain clocks */
2675 &mdm_ick,
2676 &mdm_osc_ck,
2677 /* DSS domain clocks */
2678 &dss_ick,
2679 &dss1_fck,
2680 &dss2_fck,
2681 &dss_54m_fck,
2682 /* L3 domain clocks */
2683 &core_l3_ck,
2684 &ssi_ssr_sst_fck,
2685 &usb_l4_ick,
2686 /* L4 domain clocks */
2687 &l4_ck, /* used as both core_l4 and wu_l4 */
2688 /* virtual meta-group clock */
2689 &virt_prcm_set,
2690 /* general l4 interface ck, multi-parent functional clk */
2691 &gpt1_ick,
2692 &gpt1_fck,
2693 &gpt2_ick,
2694 &gpt2_fck,
2695 &gpt3_ick,
2696 &gpt3_fck,
2697 &gpt4_ick,
2698 &gpt4_fck,
2699 &gpt5_ick,
2700 &gpt5_fck,
2701 &gpt6_ick,
2702 &gpt6_fck,
2703 &gpt7_ick,
2704 &gpt7_fck,
2705 &gpt8_ick,
2706 &gpt8_fck,
2707 &gpt9_ick,
2708 &gpt9_fck,
2709 &gpt10_ick,
2710 &gpt10_fck,
2711 &gpt11_ick,
2712 &gpt11_fck,
2713 &gpt12_ick,
2714 &gpt12_fck,
2715 &mcbsp1_ick,
2716 &mcbsp1_fck,
2717 &mcbsp2_ick,
2718 &mcbsp2_fck,
2719 &mcbsp3_ick,
2720 &mcbsp3_fck,
2721 &mcbsp4_ick,
2722 &mcbsp4_fck,
2723 &mcbsp5_ick,
2724 &mcbsp5_fck,
2725 &mcspi1_ick,
2726 &mcspi1_fck,
2727 &mcspi2_ick,
2728 &mcspi2_fck,
2729 &mcspi3_ick,
2730 &mcspi3_fck,
2731 &uart1_ick,
2732 &uart1_fck,
2733 &uart2_ick,
2734 &uart2_fck,
2735 &uart3_ick,
2736 &uart3_fck,
2737 &gpios_ick,
2738 &gpios_fck,
2739 &mpu_wdt_ick,
2740 &mpu_wdt_fck,
2741 &sync_32k_ick,
2742 &wdt1_ick,
2743 &omapctrl_ick,
2744 &icr_ick,
2745 &cam_fck,
2746 &cam_ick,
2747 &mailboxes_ick,
2748 &wdt4_ick,
2749 &wdt4_fck,
2750 &wdt3_ick,
2751 &wdt3_fck,
2752 &mspro_ick,
2753 &mspro_fck,
2754 &mmc_ick,
2755 &mmc_fck,
2756 &fac_ick,
2757 &fac_fck,
2758 &eac_ick,
2759 &eac_fck,
2760 &hdq_ick,
2761 &hdq_fck,
2762 &i2c1_ick,
2763 &i2c1_fck,
2764 &i2chs1_fck,
2765 &i2c2_ick,
2766 &i2c2_fck,
2767 &i2chs2_fck,
2768 &gpmc_fck,
2769 &sdma_fck,
2770 &sdma_ick,
2771 &vlynq_ick,
2772 &vlynq_fck,
2773 &sdrc_ick,
2774 &des_ick,
2775 &sha_ick,
2776 &rng_ick,
2777 &aes_ick,
2778 &pka_ick,
2779 &usb_fck,
2780 &usbhs_ick,
2781 &mmchs1_ick,
2782 &mmchs1_fck,
2783 &mmchs2_ick,
2784 &mmchs2_fck,
2785 &gpio5_ick,
2786 &gpio5_fck,
2787 &mdm_intc_ick,
2788 &mmchsdb1_fck,
2789 &mmchsdb2_fck,
2790};
2791
2792#endif 2637#endif
2793 2638
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 15:59:45 -0500