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path: root/arch/arm/mach-omap2/clock24xx.c
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Diffstat (limited to 'arch/arm/mach-omap2/clock24xx.c')
-rw-r--r--arch/arm/mach-omap2/clock24xx.c23
1 files changed, 12 insertions, 11 deletions
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 83911ad48733..a11e7c71177c 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -389,9 +389,9 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
389 mult &= OMAP24XX_CORE_CLK_SRC_MASK; 389 mult &= OMAP24XX_CORE_CLK_SRC_MASK;
390 390
391 if ((rate == (cur_rate / 2)) && (mult == 2)) { 391 if ((rate == (cur_rate / 2)) && (mult == 2)) {
392 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); 392 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
393 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { 393 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
394 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); 394 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
395 } else if (rate != cur_rate) { 395 } else if (rate != cur_rate) {
396 valid_rate = omap2_dpllcore_round_rate(rate); 396 valid_rate = omap2_dpllcore_round_rate(rate);
397 if (valid_rate != rate) 397 if (valid_rate != rate)
@@ -430,15 +430,16 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
430 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ 430 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
431 bypass = 1; 431 bypass = 1;
432 432
433 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */ 433 /* For omap2xxx_sdrc_init_params() */
434 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
434 435
435 /* Force dll lock mode */ 436 /* Force dll lock mode */
436 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, 437 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
437 bypass); 438 bypass);
438 439
439 /* Errata: ret dll entry state */ 440 /* Errata: ret dll entry state */
440 omap2_init_memory_params(omap2_dll_force_needed()); 441 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
441 omap2_reprogram_sdrc(done_rate, 0); 442 omap2xxx_sdrc_reprogram(done_rate, 0);
442 } 443 }
443 omap2_dpllcore_recalc(&dpll_ck); 444 omap2_dpllcore_recalc(&dpll_ck);
444 ret = 0; 445 ret = 0;
@@ -525,9 +526,9 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
525 cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); 526 cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
526 527
527 if (prcm->dpll_speed == cur_rate / 2) { 528 if (prcm->dpll_speed == cur_rate / 2) {
528 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); 529 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
529 } else if (prcm->dpll_speed == cur_rate * 2) { 530 } else if (prcm->dpll_speed == cur_rate * 2) {
530 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); 531 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
531 } else if (prcm->dpll_speed != cur_rate) { 532 } else if (prcm->dpll_speed != cur_rate) {
532 local_irq_save(flags); 533 local_irq_save(flags);
533 534
@@ -558,14 +559,14 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
558 cm_write_mod_reg(prcm->cm_clksel_mdm, 559 cm_write_mod_reg(prcm->cm_clksel_mdm,
559 OMAP2430_MDM_MOD, CM_CLKSEL); 560 OMAP2430_MDM_MOD, CM_CLKSEL);
560 561
561 /* x2 to enter init_mem */ 562 /* x2 to enter omap2xxx_sdrc_init_params() */
562 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); 563 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
563 564
564 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, 565 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
565 bypass); 566 bypass);
566 567
567 omap2_init_memory_params(omap2_dll_force_needed()); 568 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
568 omap2_reprogram_sdrc(done_rate, 0); 569 omap2xxx_sdrc_reprogram(done_rate, 0);
569 570
570 local_irq_restore(flags); 571 local_irq_restore(flags);
571 } 572 }