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-rw-r--r--arch/arm/mach-omap2/clock2430_data.c2071
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diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
deleted file mode 100644
index b179b6ef4329..000000000000
--- a/arch/arm/mach-omap2/clock2430_data.c
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@@ -1,2071 +0,0 @@
1/*
2 * OMAP2430 clock data
3 *
4 * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/list.h>
19
20#include "soc.h"
21#include "iomap.h"
22#include "clock.h"
23#include "clock2xxx.h"
24#include "opp2xxx.h"
25#include "cm2xxx.h"
26#include "prm2xxx_3xxx.h"
27#include "prm-regbits-24xx.h"
28#include "cm-regbits-24xx.h"
29#include "sdrc.h"
30#include "control.h"
31
32#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
33
34/*
35 * 2430 clock tree.
36 *
37 * NOTE:In many cases here we are assigning a 'default' parent. In
38 * many cases the parent is selectable. The set parent calls will
39 * also switch sources.
40 *
41 * Several sources are given initial rates which may be wrong, this will
42 * be fixed up in the init func.
43 *
44 * Things are broadly separated below by clock domains. It is
45 * noteworthy that most peripherals have dependencies on multiple clock
46 * domains. Many get their interface clocks from the L4 domain, but get
47 * functional clocks from fixed sources or other core domain derived
48 * clocks.
49 */
50
51/* Base external input clocks */
52static struct clk func_32k_ck = {
53 .name = "func_32k_ck",
54 .ops = &clkops_null,
55 .rate = 32768,
56 .clkdm_name = "wkup_clkdm",
57};
58
59static struct clk secure_32k_ck = {
60 .name = "secure_32k_ck",
61 .ops = &clkops_null,
62 .rate = 32768,
63 .clkdm_name = "wkup_clkdm",
64};
65
66/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
67static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
68 .name = "osc_ck",
69 .ops = &clkops_oscck,
70 .clkdm_name = "wkup_clkdm",
71 .recalc = &omap2_osc_clk_recalc,
72};
73
74/* Without modem likely 12MHz, with modem likely 13MHz */
75static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
76 .name = "sys_ck", /* ~ ref_clk also */
77 .ops = &clkops_null,
78 .parent = &osc_ck,
79 .clkdm_name = "wkup_clkdm",
80 .recalc = &omap2xxx_sys_clk_recalc,
81};
82
83static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
84 .name = "alt_ck",
85 .ops = &clkops_null,
86 .rate = 54000000,
87 .clkdm_name = "wkup_clkdm",
88};
89
90/* Optional external clock input for McBSP CLKS */
91static struct clk mcbsp_clks = {
92 .name = "mcbsp_clks",
93 .ops = &clkops_null,
94};
95
96/*
97 * Analog domain root source clocks
98 */
99
100/* dpll_ck, is broken out in to special cases through clksel */
101/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
102 * deal with this
103 */
104
105static struct dpll_data dpll_dd = {
106 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
107 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
108 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
109 .clk_bypass = &sys_ck,
110 .clk_ref = &sys_ck,
111 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
112 .enable_mask = OMAP24XX_EN_DPLL_MASK,
113 .max_multiplier = 1023,
114 .min_divider = 1,
115 .max_divider = 16,
116};
117
118/*
119 * XXX Cannot add round_rate here yet, as this is still a composite clock,
120 * not just a DPLL
121 */
122static struct clk dpll_ck = {
123 .name = "dpll_ck",
124 .ops = &clkops_omap2xxx_dpll_ops,
125 .parent = &sys_ck, /* Can be func_32k also */
126 .init = &omap2xxx_clkt_dpllcore_init,
127 .dpll_data = &dpll_dd,
128 .clkdm_name = "wkup_clkdm",
129 .recalc = &omap2_dpllcore_recalc,
130 .set_rate = &omap2_reprogram_dpllcore,
131};
132
133static struct clk apll96_ck = {
134 .name = "apll96_ck",
135 .ops = &clkops_apll96,
136 .parent = &sys_ck,
137 .rate = 96000000,
138 .flags = ENABLE_ON_INIT,
139 .clkdm_name = "wkup_clkdm",
140 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
141 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
142};
143
144static struct clk apll54_ck = {
145 .name = "apll54_ck",
146 .ops = &clkops_apll54,
147 .parent = &sys_ck,
148 .rate = 54000000,
149 .flags = ENABLE_ON_INIT,
150 .clkdm_name = "wkup_clkdm",
151 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
152 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
153};
154
155/*
156 * PRCM digital base sources
157 */
158
159/* func_54m_ck */
160
161static const struct clksel_rate func_54m_apll54_rates[] = {
162 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
163 { .div = 0 },
164};
165
166static const struct clksel_rate func_54m_alt_rates[] = {
167 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
168 { .div = 0 },
169};
170
171static const struct clksel func_54m_clksel[] = {
172 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
173 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
174 { .parent = NULL },
175};
176
177static struct clk func_54m_ck = {
178 .name = "func_54m_ck",
179 .ops = &clkops_null,
180 .parent = &apll54_ck, /* can also be alt_clk */
181 .clkdm_name = "wkup_clkdm",
182 .init = &omap2_init_clksel_parent,
183 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
184 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
185 .clksel = func_54m_clksel,
186 .recalc = &omap2_clksel_recalc,
187};
188
189static struct clk core_ck = {
190 .name = "core_ck",
191 .ops = &clkops_null,
192 .parent = &dpll_ck, /* can also be 32k */
193 .clkdm_name = "wkup_clkdm",
194 .recalc = &followparent_recalc,
195};
196
197/* func_96m_ck */
198static const struct clksel_rate func_96m_apll96_rates[] = {
199 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
200 { .div = 0 },
201};
202
203static const struct clksel_rate func_96m_alt_rates[] = {
204 { .div = 1, .val = 1, .flags = RATE_IN_243X },
205 { .div = 0 },
206};
207
208static const struct clksel func_96m_clksel[] = {
209 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
210 { .parent = &alt_ck, .rates = func_96m_alt_rates },
211 { .parent = NULL }
212};
213
214static struct clk func_96m_ck = {
215 .name = "func_96m_ck",
216 .ops = &clkops_null,
217 .parent = &apll96_ck,
218 .clkdm_name = "wkup_clkdm",
219 .init = &omap2_init_clksel_parent,
220 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
221 .clksel_mask = OMAP2430_96M_SOURCE_MASK,
222 .clksel = func_96m_clksel,
223 .recalc = &omap2_clksel_recalc,
224};
225
226/* func_48m_ck */
227
228static const struct clksel_rate func_48m_apll96_rates[] = {
229 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
230 { .div = 0 },
231};
232
233static const struct clksel_rate func_48m_alt_rates[] = {
234 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
235 { .div = 0 },
236};
237
238static const struct clksel func_48m_clksel[] = {
239 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
240 { .parent = &alt_ck, .rates = func_48m_alt_rates },
241 { .parent = NULL }
242};
243
244static struct clk func_48m_ck = {
245 .name = "func_48m_ck",
246 .ops = &clkops_null,
247 .parent = &apll96_ck, /* 96M or Alt */
248 .clkdm_name = "wkup_clkdm",
249 .init = &omap2_init_clksel_parent,
250 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
251 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
252 .clksel = func_48m_clksel,
253 .recalc = &omap2_clksel_recalc,
254 .round_rate = &omap2_clksel_round_rate,
255 .set_rate = &omap2_clksel_set_rate
256};
257
258static struct clk func_12m_ck = {
259 .name = "func_12m_ck",
260 .ops = &clkops_null,
261 .parent = &func_48m_ck,
262 .fixed_div = 4,
263 .clkdm_name = "wkup_clkdm",
264 .recalc = &omap_fixed_divisor_recalc,
265};
266
267/* Secure timer, only available in secure mode */
268static struct clk wdt1_osc_ck = {
269 .name = "ck_wdt1_osc",
270 .ops = &clkops_null, /* RMK: missing? */
271 .parent = &osc_ck,
272 .recalc = &followparent_recalc,
273};
274
275/*
276 * The common_clkout* clksel_rate structs are common to
277 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
278 * sys_clkout2_* are 2420-only, so the
279 * clksel_rate flags fields are inaccurate for those clocks. This is
280 * harmless since access to those clocks are gated by the struct clk
281 * flags fields, which mark them as 2420-only.
282 */
283static const struct clksel_rate common_clkout_src_core_rates[] = {
284 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
285 { .div = 0 }
286};
287
288static const struct clksel_rate common_clkout_src_sys_rates[] = {
289 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
290 { .div = 0 }
291};
292
293static const struct clksel_rate common_clkout_src_96m_rates[] = {
294 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
295 { .div = 0 }
296};
297
298static const struct clksel_rate common_clkout_src_54m_rates[] = {
299 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
300 { .div = 0 }
301};
302
303static const struct clksel common_clkout_src_clksel[] = {
304 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
305 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
306 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
307 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
308 { .parent = NULL }
309};
310
311static struct clk sys_clkout_src = {
312 .name = "sys_clkout_src",
313 .ops = &clkops_omap2_dflt,
314 .parent = &func_54m_ck,
315 .clkdm_name = "wkup_clkdm",
316 .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL,
317 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
318 .init = &omap2_init_clksel_parent,
319 .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
320 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
321 .clksel = common_clkout_src_clksel,
322 .recalc = &omap2_clksel_recalc,
323 .round_rate = &omap2_clksel_round_rate,
324 .set_rate = &omap2_clksel_set_rate
325};
326
327static const struct clksel_rate common_clkout_rates[] = {
328 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
329 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
330 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
331 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
332 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
333 { .div = 0 },
334};
335
336static const struct clksel sys_clkout_clksel[] = {
337 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
338 { .parent = NULL }
339};
340
341static struct clk sys_clkout = {
342 .name = "sys_clkout",
343 .ops = &clkops_null,
344 .parent = &sys_clkout_src,
345 .clkdm_name = "wkup_clkdm",
346 .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
347 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
348 .clksel = sys_clkout_clksel,
349 .recalc = &omap2_clksel_recalc,
350 .round_rate = &omap2_clksel_round_rate,
351 .set_rate = &omap2_clksel_set_rate
352};
353
354static struct clk emul_ck = {
355 .name = "emul_ck",
356 .ops = &clkops_omap2_dflt,
357 .parent = &func_54m_ck,
358 .clkdm_name = "wkup_clkdm",
359 .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
360 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
361 .recalc = &followparent_recalc,
362
363};
364
365/*
366 * MPU clock domain
367 * Clocks:
368 * MPU_FCLK, MPU_ICLK
369 * INT_M_FCLK, INT_M_I_CLK
370 *
371 * - Individual clocks are hardware managed.
372 * - Base divider comes from: CM_CLKSEL_MPU
373 *
374 */
375static const struct clksel_rate mpu_core_rates[] = {
376 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
377 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
378 { .div = 0 },
379};
380
381static const struct clksel mpu_clksel[] = {
382 { .parent = &core_ck, .rates = mpu_core_rates },
383 { .parent = NULL }
384};
385
386static struct clk mpu_ck = { /* Control cpu */
387 .name = "mpu_ck",
388 .ops = &clkops_null,
389 .parent = &core_ck,
390 .clkdm_name = "mpu_clkdm",
391 .init = &omap2_init_clksel_parent,
392 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
393 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
394 .clksel = mpu_clksel,
395 .recalc = &omap2_clksel_recalc,
396};
397
398/*
399 * DSP (2430-IVA2.1) clock domain
400 * Clocks:
401 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
402 *
403 * Won't be too specific here. The core clock comes into this block
404 * it is divided then tee'ed. One branch goes directly to xyz enable
405 * controls. The other branch gets further divided by 2 then possibly
406 * routed into a synchronizer and out of clocks abc.
407 */
408static const struct clksel_rate dsp_fck_core_rates[] = {
409 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
410 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
411 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
412 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
413 { .div = 0 },
414};
415
416static const struct clksel dsp_fck_clksel[] = {
417 { .parent = &core_ck, .rates = dsp_fck_core_rates },
418 { .parent = NULL }
419};
420
421static struct clk dsp_fck = {
422 .name = "dsp_fck",
423 .ops = &clkops_omap2_dflt_wait,
424 .parent = &core_ck,
425 .clkdm_name = "dsp_clkdm",
426 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
427 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
428 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
429 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
430 .clksel = dsp_fck_clksel,
431 .recalc = &omap2_clksel_recalc,
432};
433
434static const struct clksel dsp_ick_clksel[] = {
435 { .parent = &dsp_fck, .rates = dsp_ick_rates },
436 { .parent = NULL }
437};
438
439/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
440static struct clk iva2_1_ick = {
441 .name = "iva2_1_ick",
442 .ops = &clkops_omap2_dflt_wait,
443 .parent = &dsp_fck,
444 .clkdm_name = "dsp_clkdm",
445 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
446 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
447 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
448 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
449 .clksel = dsp_ick_clksel,
450 .recalc = &omap2_clksel_recalc,
451};
452
453/*
454 * L3 clock domain
455 * L3 clocks are used for both interface and functional clocks to
456 * multiple entities. Some of these clocks are completely managed
457 * by hardware, and some others allow software control. Hardware
458 * managed ones general are based on directly CLK_REQ signals and
459 * various auto idle settings. The functional spec sets many of these
460 * as 'tie-high' for their enables.
461 *
462 * I-CLOCKS:
463 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
464 * CAM, HS-USB.
465 * F-CLOCK
466 * SSI.
467 *
468 * GPMC memories and SDRC have timing and clock sensitive registers which
469 * may very well need notification when the clock changes. Currently for low
470 * operating points, these are taken care of in sleep.S.
471 */
472static const struct clksel_rate core_l3_core_rates[] = {
473 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
474 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
475 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
476 { .div = 0 }
477};
478
479static const struct clksel core_l3_clksel[] = {
480 { .parent = &core_ck, .rates = core_l3_core_rates },
481 { .parent = NULL }
482};
483
484static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
485 .name = "core_l3_ck",
486 .ops = &clkops_null,
487 .parent = &core_ck,
488 .clkdm_name = "core_l3_clkdm",
489 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
490 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
491 .clksel = core_l3_clksel,
492 .recalc = &omap2_clksel_recalc,
493};
494
495/* usb_l4_ick */
496static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
497 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
498 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
499 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
500 { .div = 0 }
501};
502
503static const struct clksel usb_l4_ick_clksel[] = {
504 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
505 { .parent = NULL },
506};
507
508/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
509static struct clk usb_l4_ick = { /* FS-USB interface clock */
510 .name = "usb_l4_ick",
511 .ops = &clkops_omap2_iclk_dflt_wait,
512 .parent = &core_l3_ck,
513 .clkdm_name = "core_l4_clkdm",
514 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
515 .enable_bit = OMAP24XX_EN_USB_SHIFT,
516 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
517 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
518 .clksel = usb_l4_ick_clksel,
519 .recalc = &omap2_clksel_recalc,
520};
521
522/*
523 * L4 clock management domain
524 *
525 * This domain contains lots of interface clocks from the L4 interface, some
526 * functional clocks. Fixed APLL functional source clocks are managed in
527 * this domain.
528 */
529static const struct clksel_rate l4_core_l3_rates[] = {
530 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
531 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
532 { .div = 0 }
533};
534
535static const struct clksel l4_clksel[] = {
536 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
537 { .parent = NULL }
538};
539
540static struct clk l4_ck = { /* used both as an ick and fck */
541 .name = "l4_ck",
542 .ops = &clkops_null,
543 .parent = &core_l3_ck,
544 .clkdm_name = "core_l4_clkdm",
545 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
546 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
547 .clksel = l4_clksel,
548 .recalc = &omap2_clksel_recalc,
549};
550
551/*
552 * SSI is in L3 management domain, its direct parent is core not l3,
553 * many core power domain entities are grouped into the L3 clock
554 * domain.
555 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
556 *
557 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
558 */
559static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
560 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
561 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
562 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
563 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
564 { .div = 5, .val = 5, .flags = RATE_IN_243X },
565 { .div = 0 }
566};
567
568static const struct clksel ssi_ssr_sst_fck_clksel[] = {
569 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
570 { .parent = NULL }
571};
572
573static struct clk ssi_ssr_sst_fck = {
574 .name = "ssi_fck",
575 .ops = &clkops_omap2_dflt_wait,
576 .parent = &core_ck,
577 .clkdm_name = "core_l3_clkdm",
578 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
579 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
580 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
581 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
582 .clksel = ssi_ssr_sst_fck_clksel,
583 .recalc = &omap2_clksel_recalc,
584};
585
586/*
587 * Presumably this is the same as SSI_ICLK.
588 * TRM contradicts itself on what clockdomain SSI_ICLK is in
589 */
590static struct clk ssi_l4_ick = {
591 .name = "ssi_l4_ick",
592 .ops = &clkops_omap2_iclk_dflt_wait,
593 .parent = &l4_ck,
594 .clkdm_name = "core_l4_clkdm",
595 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
596 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
597 .recalc = &followparent_recalc,
598};
599
600
601/*
602 * GFX clock domain
603 * Clocks:
604 * GFX_FCLK, GFX_ICLK
605 * GFX_CG1(2d), GFX_CG2(3d)
606 *
607 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
608 * The 2d and 3d clocks run at a hardware determined
609 * divided value of fclk.
610 *
611 */
612
613/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
614static const struct clksel gfx_fck_clksel[] = {
615 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
616 { .parent = NULL },
617};
618
619static struct clk gfx_3d_fck = {
620 .name = "gfx_3d_fck",
621 .ops = &clkops_omap2_dflt_wait,
622 .parent = &core_l3_ck,
623 .clkdm_name = "gfx_clkdm",
624 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
625 .enable_bit = OMAP24XX_EN_3D_SHIFT,
626 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
627 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
628 .clksel = gfx_fck_clksel,
629 .recalc = &omap2_clksel_recalc,
630 .round_rate = &omap2_clksel_round_rate,
631 .set_rate = &omap2_clksel_set_rate
632};
633
634static struct clk gfx_2d_fck = {
635 .name = "gfx_2d_fck",
636 .ops = &clkops_omap2_dflt_wait,
637 .parent = &core_l3_ck,
638 .clkdm_name = "gfx_clkdm",
639 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
640 .enable_bit = OMAP24XX_EN_2D_SHIFT,
641 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
642 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
643 .clksel = gfx_fck_clksel,
644 .recalc = &omap2_clksel_recalc,
645};
646
647/* This interface clock does not have a CM_AUTOIDLE bit */
648static struct clk gfx_ick = {
649 .name = "gfx_ick", /* From l3 */
650 .ops = &clkops_omap2_dflt_wait,
651 .parent = &core_l3_ck,
652 .clkdm_name = "gfx_clkdm",
653 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
654 .enable_bit = OMAP_EN_GFX_SHIFT,
655 .recalc = &followparent_recalc,
656};
657
658/*
659 * Modem clock domain (2430)
660 * CLOCKS:
661 * MDM_OSC_CLK
662 * MDM_ICLK
663 * These clocks are usable in chassis mode only.
664 */
665static const struct clksel_rate mdm_ick_core_rates[] = {
666 { .div = 1, .val = 1, .flags = RATE_IN_243X },
667 { .div = 4, .val = 4, .flags = RATE_IN_243X },
668 { .div = 6, .val = 6, .flags = RATE_IN_243X },
669 { .div = 9, .val = 9, .flags = RATE_IN_243X },
670 { .div = 0 }
671};
672
673static const struct clksel mdm_ick_clksel[] = {
674 { .parent = &core_ck, .rates = mdm_ick_core_rates },
675 { .parent = NULL }
676};
677
678static struct clk mdm_ick = { /* used both as a ick and fck */
679 .name = "mdm_ick",
680 .ops = &clkops_omap2_iclk_dflt_wait,
681 .parent = &core_ck,
682 .clkdm_name = "mdm_clkdm",
683 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
684 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
685 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
686 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
687 .clksel = mdm_ick_clksel,
688 .recalc = &omap2_clksel_recalc,
689};
690
691static struct clk mdm_osc_ck = {
692 .name = "mdm_osc_ck",
693 .ops = &clkops_omap2_mdmclk_dflt_wait,
694 .parent = &osc_ck,
695 .clkdm_name = "mdm_clkdm",
696 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
697 .enable_bit = OMAP2430_EN_OSC_SHIFT,
698 .recalc = &followparent_recalc,
699};
700
701/*
702 * DSS clock domain
703 * CLOCKs:
704 * DSS_L4_ICLK, DSS_L3_ICLK,
705 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
706 *
707 * DSS is both initiator and target.
708 */
709/* XXX Add RATE_NOT_VALIDATED */
710
711static const struct clksel_rate dss1_fck_sys_rates[] = {
712 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
713 { .div = 0 }
714};
715
716static const struct clksel_rate dss1_fck_core_rates[] = {
717 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
718 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
719 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
720 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
721 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
722 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
723 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
724 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
725 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
726 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
727 { .div = 0 }
728};
729
730static const struct clksel dss1_fck_clksel[] = {
731 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
732 { .parent = &core_ck, .rates = dss1_fck_core_rates },
733 { .parent = NULL },
734};
735
736static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
737 .name = "dss_ick",
738 .ops = &clkops_omap2_iclk_dflt,
739 .parent = &l4_ck, /* really both l3 and l4 */
740 .clkdm_name = "dss_clkdm",
741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
742 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
743 .recalc = &followparent_recalc,
744};
745
746static struct clk dss1_fck = {
747 .name = "dss1_fck",
748 .ops = &clkops_omap2_dflt,
749 .parent = &core_ck, /* Core or sys */
750 .clkdm_name = "dss_clkdm",
751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
752 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
753 .init = &omap2_init_clksel_parent,
754 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
755 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
756 .clksel = dss1_fck_clksel,
757 .recalc = &omap2_clksel_recalc,
758};
759
760static const struct clksel_rate dss2_fck_sys_rates[] = {
761 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
762 { .div = 0 }
763};
764
765static const struct clksel_rate dss2_fck_48m_rates[] = {
766 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
767 { .div = 0 }
768};
769
770static const struct clksel dss2_fck_clksel[] = {
771 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
772 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
773 { .parent = NULL }
774};
775
776static struct clk dss2_fck = { /* Alt clk used in power management */
777 .name = "dss2_fck",
778 .ops = &clkops_omap2_dflt,
779 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
780 .clkdm_name = "dss_clkdm",
781 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
782 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
783 .init = &omap2_init_clksel_parent,
784 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
785 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
786 .clksel = dss2_fck_clksel,
787 .recalc = &omap2_clksel_recalc,
788};
789
790static struct clk dss_54m_fck = { /* Alt clk used in power management */
791 .name = "dss_54m_fck", /* 54m tv clk */
792 .ops = &clkops_omap2_dflt_wait,
793 .parent = &func_54m_ck,
794 .clkdm_name = "dss_clkdm",
795 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
796 .enable_bit = OMAP24XX_EN_TV_SHIFT,
797 .recalc = &followparent_recalc,
798};
799
800static struct clk wu_l4_ick = {
801 .name = "wu_l4_ick",
802 .ops = &clkops_null,
803 .parent = &sys_ck,
804 .clkdm_name = "wkup_clkdm",
805 .recalc = &followparent_recalc,
806};
807
808/*
809 * CORE power domain ICLK & FCLK defines.
810 * Many of the these can have more than one possible parent. Entries
811 * here will likely have an L4 interface parent, and may have multiple
812 * functional clock parents.
813 */
814static const struct clksel_rate gpt_alt_rates[] = {
815 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
816 { .div = 0 }
817};
818
819static const struct clksel omap24xx_gpt_clksel[] = {
820 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
821 { .parent = &sys_ck, .rates = gpt_sys_rates },
822 { .parent = &alt_ck, .rates = gpt_alt_rates },
823 { .parent = NULL },
824};
825
826static struct clk gpt1_ick = {
827 .name = "gpt1_ick",
828 .ops = &clkops_omap2_iclk_dflt_wait,
829 .parent = &wu_l4_ick,
830 .clkdm_name = "wkup_clkdm",
831 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
832 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
833 .recalc = &followparent_recalc,
834};
835
836static struct clk gpt1_fck = {
837 .name = "gpt1_fck",
838 .ops = &clkops_omap2_dflt_wait,
839 .parent = &func_32k_ck,
840 .clkdm_name = "core_l4_clkdm",
841 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
842 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
843 .init = &omap2_init_clksel_parent,
844 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
845 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
846 .clksel = omap24xx_gpt_clksel,
847 .recalc = &omap2_clksel_recalc,
848 .round_rate = &omap2_clksel_round_rate,
849 .set_rate = &omap2_clksel_set_rate
850};
851
852static struct clk gpt2_ick = {
853 .name = "gpt2_ick",
854 .ops = &clkops_omap2_iclk_dflt_wait,
855 .parent = &l4_ck,
856 .clkdm_name = "core_l4_clkdm",
857 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
858 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
859 .recalc = &followparent_recalc,
860};
861
862static struct clk gpt2_fck = {
863 .name = "gpt2_fck",
864 .ops = &clkops_omap2_dflt_wait,
865 .parent = &func_32k_ck,
866 .clkdm_name = "core_l4_clkdm",
867 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
868 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
869 .init = &omap2_init_clksel_parent,
870 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
871 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
872 .clksel = omap24xx_gpt_clksel,
873 .recalc = &omap2_clksel_recalc,
874};
875
876static struct clk gpt3_ick = {
877 .name = "gpt3_ick",
878 .ops = &clkops_omap2_iclk_dflt_wait,
879 .parent = &l4_ck,
880 .clkdm_name = "core_l4_clkdm",
881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
882 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
883 .recalc = &followparent_recalc,
884};
885
886static struct clk gpt3_fck = {
887 .name = "gpt3_fck",
888 .ops = &clkops_omap2_dflt_wait,
889 .parent = &func_32k_ck,
890 .clkdm_name = "core_l4_clkdm",
891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
892 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
893 .init = &omap2_init_clksel_parent,
894 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
895 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
896 .clksel = omap24xx_gpt_clksel,
897 .recalc = &omap2_clksel_recalc,
898};
899
900static struct clk gpt4_ick = {
901 .name = "gpt4_ick",
902 .ops = &clkops_omap2_iclk_dflt_wait,
903 .parent = &l4_ck,
904 .clkdm_name = "core_l4_clkdm",
905 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
906 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
907 .recalc = &followparent_recalc,
908};
909
910static struct clk gpt4_fck = {
911 .name = "gpt4_fck",
912 .ops = &clkops_omap2_dflt_wait,
913 .parent = &func_32k_ck,
914 .clkdm_name = "core_l4_clkdm",
915 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
916 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
917 .init = &omap2_init_clksel_parent,
918 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
919 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
920 .clksel = omap24xx_gpt_clksel,
921 .recalc = &omap2_clksel_recalc,
922};
923
924static struct clk gpt5_ick = {
925 .name = "gpt5_ick",
926 .ops = &clkops_omap2_iclk_dflt_wait,
927 .parent = &l4_ck,
928 .clkdm_name = "core_l4_clkdm",
929 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
930 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
931 .recalc = &followparent_recalc,
932};
933
934static struct clk gpt5_fck = {
935 .name = "gpt5_fck",
936 .ops = &clkops_omap2_dflt_wait,
937 .parent = &func_32k_ck,
938 .clkdm_name = "core_l4_clkdm",
939 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
940 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
941 .init = &omap2_init_clksel_parent,
942 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
943 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
944 .clksel = omap24xx_gpt_clksel,
945 .recalc = &omap2_clksel_recalc,
946};
947
948static struct clk gpt6_ick = {
949 .name = "gpt6_ick",
950 .ops = &clkops_omap2_iclk_dflt_wait,
951 .parent = &l4_ck,
952 .clkdm_name = "core_l4_clkdm",
953 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
954 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
955 .recalc = &followparent_recalc,
956};
957
958static struct clk gpt6_fck = {
959 .name = "gpt6_fck",
960 .ops = &clkops_omap2_dflt_wait,
961 .parent = &func_32k_ck,
962 .clkdm_name = "core_l4_clkdm",
963 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
964 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
965 .init = &omap2_init_clksel_parent,
966 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
967 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
968 .clksel = omap24xx_gpt_clksel,
969 .recalc = &omap2_clksel_recalc,
970};
971
972static struct clk gpt7_ick = {
973 .name = "gpt7_ick",
974 .ops = &clkops_omap2_iclk_dflt_wait,
975 .parent = &l4_ck,
976 .clkdm_name = "core_l4_clkdm",
977 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
978 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
979 .recalc = &followparent_recalc,
980};
981
982static struct clk gpt7_fck = {
983 .name = "gpt7_fck",
984 .ops = &clkops_omap2_dflt_wait,
985 .parent = &func_32k_ck,
986 .clkdm_name = "core_l4_clkdm",
987 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
988 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
989 .init = &omap2_init_clksel_parent,
990 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
991 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
992 .clksel = omap24xx_gpt_clksel,
993 .recalc = &omap2_clksel_recalc,
994};
995
996static struct clk gpt8_ick = {
997 .name = "gpt8_ick",
998 .ops = &clkops_omap2_iclk_dflt_wait,
999 .parent = &l4_ck,
1000 .clkdm_name = "core_l4_clkdm",
1001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1002 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1003 .recalc = &followparent_recalc,
1004};
1005
1006static struct clk gpt8_fck = {
1007 .name = "gpt8_fck",
1008 .ops = &clkops_omap2_dflt_wait,
1009 .parent = &func_32k_ck,
1010 .clkdm_name = "core_l4_clkdm",
1011 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1012 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1013 .init = &omap2_init_clksel_parent,
1014 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1015 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1016 .clksel = omap24xx_gpt_clksel,
1017 .recalc = &omap2_clksel_recalc,
1018};
1019
1020static struct clk gpt9_ick = {
1021 .name = "gpt9_ick",
1022 .ops = &clkops_omap2_iclk_dflt_wait,
1023 .parent = &l4_ck,
1024 .clkdm_name = "core_l4_clkdm",
1025 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1026 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1027 .recalc = &followparent_recalc,
1028};
1029
1030static struct clk gpt9_fck = {
1031 .name = "gpt9_fck",
1032 .ops = &clkops_omap2_dflt_wait,
1033 .parent = &func_32k_ck,
1034 .clkdm_name = "core_l4_clkdm",
1035 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1036 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1037 .init = &omap2_init_clksel_parent,
1038 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1039 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1040 .clksel = omap24xx_gpt_clksel,
1041 .recalc = &omap2_clksel_recalc,
1042};
1043
1044static struct clk gpt10_ick = {
1045 .name = "gpt10_ick",
1046 .ops = &clkops_omap2_iclk_dflt_wait,
1047 .parent = &l4_ck,
1048 .clkdm_name = "core_l4_clkdm",
1049 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1050 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1051 .recalc = &followparent_recalc,
1052};
1053
1054static struct clk gpt10_fck = {
1055 .name = "gpt10_fck",
1056 .ops = &clkops_omap2_dflt_wait,
1057 .parent = &func_32k_ck,
1058 .clkdm_name = "core_l4_clkdm",
1059 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1060 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1061 .init = &omap2_init_clksel_parent,
1062 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1063 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1064 .clksel = omap24xx_gpt_clksel,
1065 .recalc = &omap2_clksel_recalc,
1066};
1067
1068static struct clk gpt11_ick = {
1069 .name = "gpt11_ick",
1070 .ops = &clkops_omap2_iclk_dflt_wait,
1071 .parent = &l4_ck,
1072 .clkdm_name = "core_l4_clkdm",
1073 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1074 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1075 .recalc = &followparent_recalc,
1076};
1077
1078static struct clk gpt11_fck = {
1079 .name = "gpt11_fck",
1080 .ops = &clkops_omap2_dflt_wait,
1081 .parent = &func_32k_ck,
1082 .clkdm_name = "core_l4_clkdm",
1083 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1084 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1085 .init = &omap2_init_clksel_parent,
1086 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1087 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1088 .clksel = omap24xx_gpt_clksel,
1089 .recalc = &omap2_clksel_recalc,
1090};
1091
1092static struct clk gpt12_ick = {
1093 .name = "gpt12_ick",
1094 .ops = &clkops_omap2_iclk_dflt_wait,
1095 .parent = &l4_ck,
1096 .clkdm_name = "core_l4_clkdm",
1097 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1098 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1099 .recalc = &followparent_recalc,
1100};
1101
1102static struct clk gpt12_fck = {
1103 .name = "gpt12_fck",
1104 .ops = &clkops_omap2_dflt_wait,
1105 .parent = &secure_32k_ck,
1106 .clkdm_name = "core_l4_clkdm",
1107 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1108 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1109 .init = &omap2_init_clksel_parent,
1110 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1111 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1112 .clksel = omap24xx_gpt_clksel,
1113 .recalc = &omap2_clksel_recalc,
1114};
1115
1116static struct clk mcbsp1_ick = {
1117 .name = "mcbsp1_ick",
1118 .ops = &clkops_omap2_iclk_dflt_wait,
1119 .parent = &l4_ck,
1120 .clkdm_name = "core_l4_clkdm",
1121 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1122 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1123 .recalc = &followparent_recalc,
1124};
1125
1126static const struct clksel_rate common_mcbsp_96m_rates[] = {
1127 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1128 { .div = 0 }
1129};
1130
1131static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1132 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1133 { .div = 0 }
1134};
1135
1136static const struct clksel mcbsp_fck_clksel[] = {
1137 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1138 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1139 { .parent = NULL }
1140};
1141
1142static struct clk mcbsp1_fck = {
1143 .name = "mcbsp1_fck",
1144 .ops = &clkops_omap2_dflt_wait,
1145 .parent = &func_96m_ck,
1146 .init = &omap2_init_clksel_parent,
1147 .clkdm_name = "core_l4_clkdm",
1148 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1149 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1150 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1151 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1152 .clksel = mcbsp_fck_clksel,
1153 .recalc = &omap2_clksel_recalc,
1154};
1155
1156static struct clk mcbsp2_ick = {
1157 .name = "mcbsp2_ick",
1158 .ops = &clkops_omap2_iclk_dflt_wait,
1159 .parent = &l4_ck,
1160 .clkdm_name = "core_l4_clkdm",
1161 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1162 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1163 .recalc = &followparent_recalc,
1164};
1165
1166static struct clk mcbsp2_fck = {
1167 .name = "mcbsp2_fck",
1168 .ops = &clkops_omap2_dflt_wait,
1169 .parent = &func_96m_ck,
1170 .init = &omap2_init_clksel_parent,
1171 .clkdm_name = "core_l4_clkdm",
1172 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1173 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1174 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1175 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
1176 .clksel = mcbsp_fck_clksel,
1177 .recalc = &omap2_clksel_recalc,
1178};
1179
1180static struct clk mcbsp3_ick = {
1181 .name = "mcbsp3_ick",
1182 .ops = &clkops_omap2_iclk_dflt_wait,
1183 .parent = &l4_ck,
1184 .clkdm_name = "core_l4_clkdm",
1185 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1186 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1187 .recalc = &followparent_recalc,
1188};
1189
1190static struct clk mcbsp3_fck = {
1191 .name = "mcbsp3_fck",
1192 .ops = &clkops_omap2_dflt_wait,
1193 .parent = &func_96m_ck,
1194 .init = &omap2_init_clksel_parent,
1195 .clkdm_name = "core_l4_clkdm",
1196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1197 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1198 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1199 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
1200 .clksel = mcbsp_fck_clksel,
1201 .recalc = &omap2_clksel_recalc,
1202};
1203
1204static struct clk mcbsp4_ick = {
1205 .name = "mcbsp4_ick",
1206 .ops = &clkops_omap2_iclk_dflt_wait,
1207 .parent = &l4_ck,
1208 .clkdm_name = "core_l4_clkdm",
1209 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1210 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1211 .recalc = &followparent_recalc,
1212};
1213
1214static struct clk mcbsp4_fck = {
1215 .name = "mcbsp4_fck",
1216 .ops = &clkops_omap2_dflt_wait,
1217 .parent = &func_96m_ck,
1218 .init = &omap2_init_clksel_parent,
1219 .clkdm_name = "core_l4_clkdm",
1220 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1221 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1222 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1223 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
1224 .clksel = mcbsp_fck_clksel,
1225 .recalc = &omap2_clksel_recalc,
1226};
1227
1228static struct clk mcbsp5_ick = {
1229 .name = "mcbsp5_ick",
1230 .ops = &clkops_omap2_iclk_dflt_wait,
1231 .parent = &l4_ck,
1232 .clkdm_name = "core_l4_clkdm",
1233 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1234 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1235 .recalc = &followparent_recalc,
1236};
1237
1238static struct clk mcbsp5_fck = {
1239 .name = "mcbsp5_fck",
1240 .ops = &clkops_omap2_dflt_wait,
1241 .parent = &func_96m_ck,
1242 .init = &omap2_init_clksel_parent,
1243 .clkdm_name = "core_l4_clkdm",
1244 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1245 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1246 .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1247 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1248 .clksel = mcbsp_fck_clksel,
1249 .recalc = &omap2_clksel_recalc,
1250};
1251
1252static struct clk mcspi1_ick = {
1253 .name = "mcspi1_ick",
1254 .ops = &clkops_omap2_iclk_dflt_wait,
1255 .parent = &l4_ck,
1256 .clkdm_name = "core_l4_clkdm",
1257 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1258 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1259 .recalc = &followparent_recalc,
1260};
1261
1262static struct clk mcspi1_fck = {
1263 .name = "mcspi1_fck",
1264 .ops = &clkops_omap2_dflt_wait,
1265 .parent = &func_48m_ck,
1266 .clkdm_name = "core_l4_clkdm",
1267 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1268 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1269 .recalc = &followparent_recalc,
1270};
1271
1272static struct clk mcspi2_ick = {
1273 .name = "mcspi2_ick",
1274 .ops = &clkops_omap2_iclk_dflt_wait,
1275 .parent = &l4_ck,
1276 .clkdm_name = "core_l4_clkdm",
1277 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1278 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1279 .recalc = &followparent_recalc,
1280};
1281
1282static struct clk mcspi2_fck = {
1283 .name = "mcspi2_fck",
1284 .ops = &clkops_omap2_dflt_wait,
1285 .parent = &func_48m_ck,
1286 .clkdm_name = "core_l4_clkdm",
1287 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1288 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1289 .recalc = &followparent_recalc,
1290};
1291
1292static struct clk mcspi3_ick = {
1293 .name = "mcspi3_ick",
1294 .ops = &clkops_omap2_iclk_dflt_wait,
1295 .parent = &l4_ck,
1296 .clkdm_name = "core_l4_clkdm",
1297 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1298 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1299 .recalc = &followparent_recalc,
1300};
1301
1302static struct clk mcspi3_fck = {
1303 .name = "mcspi3_fck",
1304 .ops = &clkops_omap2_dflt_wait,
1305 .parent = &func_48m_ck,
1306 .clkdm_name = "core_l4_clkdm",
1307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1308 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1309 .recalc = &followparent_recalc,
1310};
1311
1312static struct clk uart1_ick = {
1313 .name = "uart1_ick",
1314 .ops = &clkops_omap2_iclk_dflt_wait,
1315 .parent = &l4_ck,
1316 .clkdm_name = "core_l4_clkdm",
1317 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1318 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1319 .recalc = &followparent_recalc,
1320};
1321
1322static struct clk uart1_fck = {
1323 .name = "uart1_fck",
1324 .ops = &clkops_omap2_dflt_wait,
1325 .parent = &func_48m_ck,
1326 .clkdm_name = "core_l4_clkdm",
1327 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1328 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1329 .recalc = &followparent_recalc,
1330};
1331
1332static struct clk uart2_ick = {
1333 .name = "uart2_ick",
1334 .ops = &clkops_omap2_iclk_dflt_wait,
1335 .parent = &l4_ck,
1336 .clkdm_name = "core_l4_clkdm",
1337 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1338 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1339 .recalc = &followparent_recalc,
1340};
1341
1342static struct clk uart2_fck = {
1343 .name = "uart2_fck",
1344 .ops = &clkops_omap2_dflt_wait,
1345 .parent = &func_48m_ck,
1346 .clkdm_name = "core_l4_clkdm",
1347 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1348 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1349 .recalc = &followparent_recalc,
1350};
1351
1352static struct clk uart3_ick = {
1353 .name = "uart3_ick",
1354 .ops = &clkops_omap2_iclk_dflt_wait,
1355 .parent = &l4_ck,
1356 .clkdm_name = "core_l4_clkdm",
1357 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1358 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1359 .recalc = &followparent_recalc,
1360};
1361
1362static struct clk uart3_fck = {
1363 .name = "uart3_fck",
1364 .ops = &clkops_omap2_dflt_wait,
1365 .parent = &func_48m_ck,
1366 .clkdm_name = "core_l4_clkdm",
1367 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1368 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1369 .recalc = &followparent_recalc,
1370};
1371
1372static struct clk gpios_ick = {
1373 .name = "gpios_ick",
1374 .ops = &clkops_omap2_iclk_dflt_wait,
1375 .parent = &wu_l4_ick,
1376 .clkdm_name = "wkup_clkdm",
1377 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1378 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1379 .recalc = &followparent_recalc,
1380};
1381
1382static struct clk gpios_fck = {
1383 .name = "gpios_fck",
1384 .ops = &clkops_omap2_dflt_wait,
1385 .parent = &func_32k_ck,
1386 .clkdm_name = "wkup_clkdm",
1387 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1388 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1389 .recalc = &followparent_recalc,
1390};
1391
1392static struct clk mpu_wdt_ick = {
1393 .name = "mpu_wdt_ick",
1394 .ops = &clkops_omap2_iclk_dflt_wait,
1395 .parent = &wu_l4_ick,
1396 .clkdm_name = "wkup_clkdm",
1397 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1398 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1399 .recalc = &followparent_recalc,
1400};
1401
1402static struct clk mpu_wdt_fck = {
1403 .name = "mpu_wdt_fck",
1404 .ops = &clkops_omap2_dflt_wait,
1405 .parent = &func_32k_ck,
1406 .clkdm_name = "wkup_clkdm",
1407 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1408 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1409 .recalc = &followparent_recalc,
1410};
1411
1412static struct clk sync_32k_ick = {
1413 .name = "sync_32k_ick",
1414 .ops = &clkops_omap2_iclk_dflt_wait,
1415 .flags = ENABLE_ON_INIT,
1416 .parent = &wu_l4_ick,
1417 .clkdm_name = "wkup_clkdm",
1418 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1419 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1420 .recalc = &followparent_recalc,
1421};
1422
1423static struct clk wdt1_ick = {
1424 .name = "wdt1_ick",
1425 .ops = &clkops_omap2_iclk_dflt_wait,
1426 .parent = &wu_l4_ick,
1427 .clkdm_name = "wkup_clkdm",
1428 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1429 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1430 .recalc = &followparent_recalc,
1431};
1432
1433static struct clk omapctrl_ick = {
1434 .name = "omapctrl_ick",
1435 .ops = &clkops_omap2_iclk_dflt_wait,
1436 .flags = ENABLE_ON_INIT,
1437 .parent = &wu_l4_ick,
1438 .clkdm_name = "wkup_clkdm",
1439 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1440 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1441 .recalc = &followparent_recalc,
1442};
1443
1444static struct clk icr_ick = {
1445 .name = "icr_ick",
1446 .ops = &clkops_omap2_iclk_dflt_wait,
1447 .parent = &wu_l4_ick,
1448 .clkdm_name = "wkup_clkdm",
1449 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1450 .enable_bit = OMAP2430_EN_ICR_SHIFT,
1451 .recalc = &followparent_recalc,
1452};
1453
1454static struct clk cam_ick = {
1455 .name = "cam_ick",
1456 .ops = &clkops_omap2_iclk_dflt,
1457 .parent = &l4_ck,
1458 .clkdm_name = "core_l4_clkdm",
1459 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1460 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1461 .recalc = &followparent_recalc,
1462};
1463
1464/*
1465 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1466 * split into two separate clocks, since the parent clocks are different
1467 * and the clockdomains are also different.
1468 */
1469static struct clk cam_fck = {
1470 .name = "cam_fck",
1471 .ops = &clkops_omap2_dflt,
1472 .parent = &func_96m_ck,
1473 .clkdm_name = "core_l3_clkdm",
1474 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1475 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1476 .recalc = &followparent_recalc,
1477};
1478
1479static struct clk mailboxes_ick = {
1480 .name = "mailboxes_ick",
1481 .ops = &clkops_omap2_iclk_dflt_wait,
1482 .parent = &l4_ck,
1483 .clkdm_name = "core_l4_clkdm",
1484 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1485 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1486 .recalc = &followparent_recalc,
1487};
1488
1489static struct clk wdt4_ick = {
1490 .name = "wdt4_ick",
1491 .ops = &clkops_omap2_iclk_dflt_wait,
1492 .parent = &l4_ck,
1493 .clkdm_name = "core_l4_clkdm",
1494 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1495 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1496 .recalc = &followparent_recalc,
1497};
1498
1499static struct clk wdt4_fck = {
1500 .name = "wdt4_fck",
1501 .ops = &clkops_omap2_dflt_wait,
1502 .parent = &func_32k_ck,
1503 .clkdm_name = "core_l4_clkdm",
1504 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1505 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1506 .recalc = &followparent_recalc,
1507};
1508
1509static struct clk mspro_ick = {
1510 .name = "mspro_ick",
1511 .ops = &clkops_omap2_iclk_dflt_wait,
1512 .parent = &l4_ck,
1513 .clkdm_name = "core_l4_clkdm",
1514 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1515 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1516 .recalc = &followparent_recalc,
1517};
1518
1519static struct clk mspro_fck = {
1520 .name = "mspro_fck",
1521 .ops = &clkops_omap2_dflt_wait,
1522 .parent = &func_96m_ck,
1523 .clkdm_name = "core_l4_clkdm",
1524 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1525 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1526 .recalc = &followparent_recalc,
1527};
1528
1529static struct clk fac_ick = {
1530 .name = "fac_ick",
1531 .ops = &clkops_omap2_iclk_dflt_wait,
1532 .parent = &l4_ck,
1533 .clkdm_name = "core_l4_clkdm",
1534 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1535 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1536 .recalc = &followparent_recalc,
1537};
1538
1539static struct clk fac_fck = {
1540 .name = "fac_fck",
1541 .ops = &clkops_omap2_dflt_wait,
1542 .parent = &func_12m_ck,
1543 .clkdm_name = "core_l4_clkdm",
1544 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1545 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1546 .recalc = &followparent_recalc,
1547};
1548
1549static struct clk hdq_ick = {
1550 .name = "hdq_ick",
1551 .ops = &clkops_omap2_iclk_dflt_wait,
1552 .parent = &l4_ck,
1553 .clkdm_name = "core_l4_clkdm",
1554 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1555 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1556 .recalc = &followparent_recalc,
1557};
1558
1559static struct clk hdq_fck = {
1560 .name = "hdq_fck",
1561 .ops = &clkops_omap2_dflt_wait,
1562 .parent = &func_12m_ck,
1563 .clkdm_name = "core_l4_clkdm",
1564 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1565 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1566 .recalc = &followparent_recalc,
1567};
1568
1569/*
1570 * XXX This is marked as a 2420-only define, but it claims to be present
1571 * on 2430 also. Double-check.
1572 */
1573static struct clk i2c2_ick = {
1574 .name = "i2c2_ick",
1575 .ops = &clkops_omap2_iclk_dflt_wait,
1576 .parent = &l4_ck,
1577 .clkdm_name = "core_l4_clkdm",
1578 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1579 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1580 .recalc = &followparent_recalc,
1581};
1582
1583static struct clk i2chs2_fck = {
1584 .name = "i2chs2_fck",
1585 .ops = &clkops_omap2430_i2chs_wait,
1586 .parent = &func_96m_ck,
1587 .clkdm_name = "core_l4_clkdm",
1588 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1589 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
1590 .recalc = &followparent_recalc,
1591};
1592
1593/*
1594 * XXX This is marked as a 2420-only define, but it claims to be present
1595 * on 2430 also. Double-check.
1596 */
1597static struct clk i2c1_ick = {
1598 .name = "i2c1_ick",
1599 .ops = &clkops_omap2_iclk_dflt_wait,
1600 .parent = &l4_ck,
1601 .clkdm_name = "core_l4_clkdm",
1602 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1603 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1604 .recalc = &followparent_recalc,
1605};
1606
1607static struct clk i2chs1_fck = {
1608 .name = "i2chs1_fck",
1609 .ops = &clkops_omap2430_i2chs_wait,
1610 .parent = &func_96m_ck,
1611 .clkdm_name = "core_l4_clkdm",
1612 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1613 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
1614 .recalc = &followparent_recalc,
1615};
1616
1617/*
1618 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1619 * accesses derived from this data.
1620 */
1621static struct clk gpmc_fck = {
1622 .name = "gpmc_fck",
1623 .ops = &clkops_omap2_iclk_idle_only,
1624 .parent = &core_l3_ck,
1625 .flags = ENABLE_ON_INIT,
1626 .clkdm_name = "core_l3_clkdm",
1627 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1628 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
1629 .recalc = &followparent_recalc,
1630};
1631
1632static struct clk sdma_fck = {
1633 .name = "sdma_fck",
1634 .ops = &clkops_null, /* RMK: missing? */
1635 .parent = &core_l3_ck,
1636 .clkdm_name = "core_l3_clkdm",
1637 .recalc = &followparent_recalc,
1638};
1639
1640/*
1641 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1642 * accesses derived from this data.
1643 */
1644static struct clk sdma_ick = {
1645 .name = "sdma_ick",
1646 .ops = &clkops_omap2_iclk_idle_only,
1647 .parent = &core_l3_ck,
1648 .clkdm_name = "core_l3_clkdm",
1649 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1650 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1651 .recalc = &followparent_recalc,
1652};
1653
1654static struct clk sdrc_ick = {
1655 .name = "sdrc_ick",
1656 .ops = &clkops_omap2_iclk_idle_only,
1657 .parent = &core_l3_ck,
1658 .flags = ENABLE_ON_INIT,
1659 .clkdm_name = "core_l3_clkdm",
1660 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1661 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
1662 .recalc = &followparent_recalc,
1663};
1664
1665static struct clk des_ick = {
1666 .name = "des_ick",
1667 .ops = &clkops_omap2_iclk_dflt_wait,
1668 .parent = &l4_ck,
1669 .clkdm_name = "core_l4_clkdm",
1670 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1671 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1672 .recalc = &followparent_recalc,
1673};
1674
1675static struct clk sha_ick = {
1676 .name = "sha_ick",
1677 .ops = &clkops_omap2_iclk_dflt_wait,
1678 .parent = &l4_ck,
1679 .clkdm_name = "core_l4_clkdm",
1680 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1681 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1682 .recalc = &followparent_recalc,
1683};
1684
1685static struct clk rng_ick = {
1686 .name = "rng_ick",
1687 .ops = &clkops_omap2_iclk_dflt_wait,
1688 .parent = &l4_ck,
1689 .clkdm_name = "core_l4_clkdm",
1690 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1691 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1692 .recalc = &followparent_recalc,
1693};
1694
1695static struct clk aes_ick = {
1696 .name = "aes_ick",
1697 .ops = &clkops_omap2_iclk_dflt_wait,
1698 .parent = &l4_ck,
1699 .clkdm_name = "core_l4_clkdm",
1700 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1701 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1702 .recalc = &followparent_recalc,
1703};
1704
1705static struct clk pka_ick = {
1706 .name = "pka_ick",
1707 .ops = &clkops_omap2_iclk_dflt_wait,
1708 .parent = &l4_ck,
1709 .clkdm_name = "core_l4_clkdm",
1710 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1711 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1712 .recalc = &followparent_recalc,
1713};
1714
1715static struct clk usb_fck = {
1716 .name = "usb_fck",
1717 .ops = &clkops_omap2_dflt_wait,
1718 .parent = &func_48m_ck,
1719 .clkdm_name = "core_l3_clkdm",
1720 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1721 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1722 .recalc = &followparent_recalc,
1723};
1724
1725static struct clk usbhs_ick = {
1726 .name = "usbhs_ick",
1727 .ops = &clkops_omap2_iclk_dflt_wait,
1728 .parent = &core_l3_ck,
1729 .clkdm_name = "core_l3_clkdm",
1730 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1731 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
1732 .recalc = &followparent_recalc,
1733};
1734
1735static struct clk mmchs1_ick = {
1736 .name = "mmchs1_ick",
1737 .ops = &clkops_omap2_iclk_dflt_wait,
1738 .parent = &l4_ck,
1739 .clkdm_name = "core_l4_clkdm",
1740 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1741 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1742 .recalc = &followparent_recalc,
1743};
1744
1745static struct clk mmchs1_fck = {
1746 .name = "mmchs1_fck",
1747 .ops = &clkops_omap2_dflt_wait,
1748 .parent = &func_96m_ck,
1749 .clkdm_name = "core_l4_clkdm",
1750 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1751 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1752 .recalc = &followparent_recalc,
1753};
1754
1755static struct clk mmchs2_ick = {
1756 .name = "mmchs2_ick",
1757 .ops = &clkops_omap2_iclk_dflt_wait,
1758 .parent = &l4_ck,
1759 .clkdm_name = "core_l4_clkdm",
1760 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1761 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1762 .recalc = &followparent_recalc,
1763};
1764
1765static struct clk mmchs2_fck = {
1766 .name = "mmchs2_fck",
1767 .ops = &clkops_omap2_dflt_wait,
1768 .parent = &func_96m_ck,
1769 .clkdm_name = "core_l4_clkdm",
1770 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1771 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1772 .recalc = &followparent_recalc,
1773};
1774
1775static struct clk gpio5_ick = {
1776 .name = "gpio5_ick",
1777 .ops = &clkops_omap2_iclk_dflt_wait,
1778 .parent = &l4_ck,
1779 .clkdm_name = "core_l4_clkdm",
1780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1781 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1782 .recalc = &followparent_recalc,
1783};
1784
1785static struct clk gpio5_fck = {
1786 .name = "gpio5_fck",
1787 .ops = &clkops_omap2_dflt_wait,
1788 .parent = &func_32k_ck,
1789 .clkdm_name = "core_l4_clkdm",
1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1791 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1792 .recalc = &followparent_recalc,
1793};
1794
1795static struct clk mdm_intc_ick = {
1796 .name = "mdm_intc_ick",
1797 .ops = &clkops_omap2_iclk_dflt_wait,
1798 .parent = &l4_ck,
1799 .clkdm_name = "core_l4_clkdm",
1800 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1801 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
1802 .recalc = &followparent_recalc,
1803};
1804
1805static struct clk mmchsdb1_fck = {
1806 .name = "mmchsdb1_fck",
1807 .ops = &clkops_omap2_dflt_wait,
1808 .parent = &func_32k_ck,
1809 .clkdm_name = "core_l4_clkdm",
1810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1811 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
1812 .recalc = &followparent_recalc,
1813};
1814
1815static struct clk mmchsdb2_fck = {
1816 .name = "mmchsdb2_fck",
1817 .ops = &clkops_omap2_dflt_wait,
1818 .parent = &func_32k_ck,
1819 .clkdm_name = "core_l4_clkdm",
1820 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1821 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
1822 .recalc = &followparent_recalc,
1823};
1824
1825/*
1826 * This clock is a composite clock which does entire set changes then
1827 * forces a rebalance. It keys on the MPU speed, but it really could
1828 * be any key speed part of a set in the rate table.
1829 *
1830 * to really change a set, you need memory table sets which get changed
1831 * in sram, pre-notifiers & post notifiers, changing the top set, without
1832 * having low level display recalc's won't work... this is why dpm notifiers
1833 * work, isr's off, walk a list of clocks already _off_ and not messing with
1834 * the bus.
1835 *
1836 * This clock should have no parent. It embodies the entire upper level
1837 * active set. A parent will mess up some of the init also.
1838 */
1839static struct clk virt_prcm_set = {
1840 .name = "virt_prcm_set",
1841 .ops = &clkops_null,
1842 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1843 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
1844 .set_rate = &omap2_select_table_rate,
1845 .round_rate = &omap2_round_to_table_rate,
1846};
1847
1848
1849/*
1850 * clkdev integration
1851 */
1852
1853static struct omap_clk omap2430_clks[] = {
1854 /* external root sources */
1855 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
1856 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
1857 CLK(NULL, "osc_ck", &osc_ck, CK_243X),
1858 CLK("twl", "fck", &osc_ck, CK_243X),
1859 CLK(NULL, "sys_ck", &sys_ck, CK_243X),
1860 CLK(NULL, "alt_ck", &alt_ck, CK_243X),
1861 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
1862 /* internal analog sources */
1863 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
1864 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
1865 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
1866 /* internal prcm root sources */
1867 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
1868 CLK(NULL, "core_ck", &core_ck, CK_243X),
1869 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
1870 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
1871 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
1872 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
1873 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
1874 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
1875 CLK(NULL, "emul_ck", &emul_ck, CK_243X),
1876 /* mpu domain clocks */
1877 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
1878 /* dsp domain clocks */
1879 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
1880 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
1881 /* GFX domain clocks */
1882 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
1883 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
1884 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
1885 /* Modem domain clocks */
1886 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
1887 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
1888 /* DSS domain clocks */
1889 CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
1890 CLK(NULL, "dss_ick", &dss_ick, CK_243X),
1891 CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
1892 CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
1893 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
1894 /* L3 domain clocks */
1895 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
1896 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
1897 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
1898 /* L4 domain clocks */
1899 CLK(NULL, "l4_ck", &l4_ck, CK_243X),
1900 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
1901 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
1902 /* virtual meta-group clock */
1903 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
1904 /* general l4 interface ck, multi-parent functional clk */
1905 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
1906 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
1907 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
1908 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
1909 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
1910 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
1911 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
1912 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
1913 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
1914 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
1915 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
1916 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
1917 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
1918 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
1919 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
1920 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
1921 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
1922 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
1923 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
1924 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
1925 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
1926 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
1927 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
1928 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
1929 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
1930 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X),
1931 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
1932 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
1933 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X),
1934 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
1935 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
1936 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X),
1937 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
1938 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
1939 CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X),
1940 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
1941 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
1942 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X),
1943 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
1944 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
1945 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X),
1946 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
1947 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
1948 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X),
1949 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
1950 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
1951 CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X),
1952 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
1953 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
1954 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
1955 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
1956 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
1957 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
1958 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
1959 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
1960 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
1961 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
1962 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X),
1963 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
1964 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
1965 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
1966 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
1967 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
1968 CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
1969 CLK(NULL, "cam_fck", &cam_fck, CK_243X),
1970 CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
1971 CLK(NULL, "cam_ick", &cam_ick, CK_243X),
1972 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
1973 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
1974 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
1975 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
1976 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
1977 CLK(NULL, "fac_ick", &fac_ick, CK_243X),
1978 CLK(NULL, "fac_fck", &fac_fck, CK_243X),
1979 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
1980 CLK(NULL, "hdq_ick", &hdq_ick, CK_243X),
1981 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
1982 CLK(NULL, "hdq_fck", &hdq_fck, CK_243X),
1983 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
1984 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X),
1985 CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
1986 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
1987 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X),
1988 CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
1989 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
1990 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
1991 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
1992 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
1993 CLK(NULL, "des_ick", &des_ick, CK_243X),
1994 CLK("omap-sham", "ick", &sha_ick, CK_243X),
1995 CLK("omap_rng", "ick", &rng_ick, CK_243X),
1996 CLK(NULL, "rng_ick", &rng_ick, CK_243X),
1997 CLK("omap-aes", "ick", &aes_ick, CK_243X),
1998 CLK(NULL, "pka_ick", &pka_ick, CK_243X),
1999 CLK(NULL, "usb_fck", &usb_fck, CK_243X),
2000 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
2001 CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
2002 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
2003 CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X),
2004 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
2005 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
2006 CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X),
2007 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
2008 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
2009 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
2010 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
2011 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
2012 CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X),
2013 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
2014 CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X),
2015 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
2016 CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
2017 CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
2018 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X),
2019};
2020
2021/*
2022 * init code
2023 */
2024
2025int __init omap2430_clk_init(void)
2026{
2027 struct omap_clk *c;
2028
2029 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
2030 cpu_mask = RATE_IN_243X;
2031 rate_table = omap2430_rate_table;
2032
2033 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2034 c++)
2035 clk_preinit(c->lk.clk);
2036
2037 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
2038 propagate_rate(&osc_ck);
2039 sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
2040 propagate_rate(&sys_ck);
2041
2042 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2043 c++) {
2044 clkdev_add(&c->lk);
2045 clk_register(c->lk.clk);
2046 omap2_init_clk_clkdm(c->lk.clk);
2047 }
2048
2049 omap2xxx_clkt_vps_late_init();
2050
2051 /* Disable autoidle on all clocks; let the PM code enable it later */
2052 omap_clk_disable_autoidle_all();
2053
2054 /* XXX Can this be done from the virt_prcm_set clk init function? */
2055 omap2xxx_clkt_vps_check_bootloader_rates();
2056
2057 recalculate_root_clocks();
2058
2059 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
2060 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
2061 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
2062
2063 /*
2064 * Only enable those clocks we will need, let the drivers
2065 * enable other clocks as necessary
2066 */
2067 clk_enable_init_clocks();
2068
2069 return 0;
2070}
2071
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 16:16:13 -0500