aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/clock2420_data.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-omap2/clock2420_data.c')
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c1933
1 files changed, 1933 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
new file mode 100644
index 000000000000..49adb0eec428
--- /dev/null
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -0,0 +1,1933 @@
1/*
2 * linux/arch/arm/mach-omap2/clock2420_data.c
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/list.h>
19
20#include <plat/clkdev_omap.h>
21
22#include "clock.h"
23#include "clock2xxx.h"
24#include "opp2xxx.h"
25#include "prm.h"
26#include "cm.h"
27#include "prm-regbits-24xx.h"
28#include "cm-regbits-24xx.h"
29#include "sdrc.h"
30
31#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
32
33/*
34 * 2420 clock tree.
35 *
36 * NOTE:In many cases here we are assigning a 'default' parent. In many
37 * cases the parent is selectable. The get/set parent calls will also
38 * switch sources.
39 *
40 * Many some clocks say always_enabled, but they can be auto idled for
41 * power savings. They will always be available upon clock request.
42 *
43 * Several sources are given initial rates which may be wrong, this will
44 * be fixed up in the init func.
45 *
46 * Things are broadly separated below by clock domains. It is
47 * noteworthy that most periferals have dependencies on multiple clock
48 * domains. Many get their interface clocks from the L4 domain, but get
49 * functional clocks from fixed sources or other core domain derived
50 * clocks.
51 */
52
53/* Base external input clocks */
54static struct clk func_32k_ck = {
55 .name = "func_32k_ck",
56 .ops = &clkops_null,
57 .rate = 32000,
58 .flags = RATE_FIXED,
59 .clkdm_name = "wkup_clkdm",
60};
61
62static struct clk secure_32k_ck = {
63 .name = "secure_32k_ck",
64 .ops = &clkops_null,
65 .rate = 32768,
66 .flags = RATE_FIXED,
67 .clkdm_name = "wkup_clkdm",
68};
69
70/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
71static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
72 .name = "osc_ck",
73 .ops = &clkops_oscck,
74 .clkdm_name = "wkup_clkdm",
75 .recalc = &omap2_osc_clk_recalc,
76};
77
78/* Without modem likely 12MHz, with modem likely 13MHz */
79static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
80 .name = "sys_ck", /* ~ ref_clk also */
81 .ops = &clkops_null,
82 .parent = &osc_ck,
83 .clkdm_name = "wkup_clkdm",
84 .recalc = &omap2xxx_sys_clk_recalc,
85};
86
87static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
88 .name = "alt_ck",
89 .ops = &clkops_null,
90 .rate = 54000000,
91 .flags = RATE_FIXED,
92 .clkdm_name = "wkup_clkdm",
93};
94
95/*
96 * Analog domain root source clocks
97 */
98
99/* dpll_ck, is broken out in to special cases through clksel */
100/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
101 * deal with this
102 */
103
104static struct dpll_data dpll_dd = {
105 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
106 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
107 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
108 .clk_bypass = &sys_ck,
109 .clk_ref = &sys_ck,
110 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
111 .enable_mask = OMAP24XX_EN_DPLL_MASK,
112 .max_multiplier = 1023,
113 .min_divider = 1,
114 .max_divider = 16,
115 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
116};
117
118/*
119 * XXX Cannot add round_rate here yet, as this is still a composite clock,
120 * not just a DPLL
121 */
122static struct clk dpll_ck = {
123 .name = "dpll_ck",
124 .ops = &clkops_null,
125 .parent = &sys_ck, /* Can be func_32k also */
126 .dpll_data = &dpll_dd,
127 .clkdm_name = "wkup_clkdm",
128 .recalc = &omap2_dpllcore_recalc,
129 .set_rate = &omap2_reprogram_dpllcore,
130};
131
132static struct clk apll96_ck = {
133 .name = "apll96_ck",
134 .ops = &clkops_apll96,
135 .parent = &sys_ck,
136 .rate = 96000000,
137 .flags = RATE_FIXED | ENABLE_ON_INIT,
138 .clkdm_name = "wkup_clkdm",
139 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
140 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
141};
142
143static struct clk apll54_ck = {
144 .name = "apll54_ck",
145 .ops = &clkops_apll54,
146 .parent = &sys_ck,
147 .rate = 54000000,
148 .flags = RATE_FIXED | ENABLE_ON_INIT,
149 .clkdm_name = "wkup_clkdm",
150 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
151 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
152};
153
154/*
155 * PRCM digital base sources
156 */
157
158/* func_54m_ck */
159
160static const struct clksel_rate func_54m_apll54_rates[] = {
161 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
162 { .div = 0 },
163};
164
165static const struct clksel_rate func_54m_alt_rates[] = {
166 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
167 { .div = 0 },
168};
169
170static const struct clksel func_54m_clksel[] = {
171 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
172 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
173 { .parent = NULL },
174};
175
176static struct clk func_54m_ck = {
177 .name = "func_54m_ck",
178 .ops = &clkops_null,
179 .parent = &apll54_ck, /* can also be alt_clk */
180 .clkdm_name = "wkup_clkdm",
181 .init = &omap2_init_clksel_parent,
182 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
183 .clksel_mask = OMAP24XX_54M_SOURCE,
184 .clksel = func_54m_clksel,
185 .recalc = &omap2_clksel_recalc,
186};
187
188static struct clk core_ck = {
189 .name = "core_ck",
190 .ops = &clkops_null,
191 .parent = &dpll_ck, /* can also be 32k */
192 .clkdm_name = "wkup_clkdm",
193 .recalc = &followparent_recalc,
194};
195
196static struct clk func_96m_ck = {
197 .name = "func_96m_ck",
198 .ops = &clkops_null,
199 .parent = &apll96_ck,
200 .clkdm_name = "wkup_clkdm",
201 .recalc = &followparent_recalc,
202};
203
204/* func_48m_ck */
205
206static const struct clksel_rate func_48m_apll96_rates[] = {
207 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
208 { .div = 0 },
209};
210
211static const struct clksel_rate func_48m_alt_rates[] = {
212 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
213 { .div = 0 },
214};
215
216static const struct clksel func_48m_clksel[] = {
217 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
218 { .parent = &alt_ck, .rates = func_48m_alt_rates },
219 { .parent = NULL }
220};
221
222static struct clk func_48m_ck = {
223 .name = "func_48m_ck",
224 .ops = &clkops_null,
225 .parent = &apll96_ck, /* 96M or Alt */
226 .clkdm_name = "wkup_clkdm",
227 .init = &omap2_init_clksel_parent,
228 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
229 .clksel_mask = OMAP24XX_48M_SOURCE,
230 .clksel = func_48m_clksel,
231 .recalc = &omap2_clksel_recalc,
232 .round_rate = &omap2_clksel_round_rate,
233 .set_rate = &omap2_clksel_set_rate
234};
235
236static struct clk func_12m_ck = {
237 .name = "func_12m_ck",
238 .ops = &clkops_null,
239 .parent = &func_48m_ck,
240 .fixed_div = 4,
241 .clkdm_name = "wkup_clkdm",
242 .recalc = &omap_fixed_divisor_recalc,
243};
244
245/* Secure timer, only available in secure mode */
246static struct clk wdt1_osc_ck = {
247 .name = "ck_wdt1_osc",
248 .ops = &clkops_null, /* RMK: missing? */
249 .parent = &osc_ck,
250 .recalc = &followparent_recalc,
251};
252
253/*
254 * The common_clkout* clksel_rate structs are common to
255 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
256 * sys_clkout2_* are 2420-only, so the
257 * clksel_rate flags fields are inaccurate for those clocks. This is
258 * harmless since access to those clocks are gated by the struct clk
259 * flags fields, which mark them as 2420-only.
260 */
261static const struct clksel_rate common_clkout_src_core_rates[] = {
262 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
263 { .div = 0 }
264};
265
266static const struct clksel_rate common_clkout_src_sys_rates[] = {
267 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
268 { .div = 0 }
269};
270
271static const struct clksel_rate common_clkout_src_96m_rates[] = {
272 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
273 { .div = 0 }
274};
275
276static const struct clksel_rate common_clkout_src_54m_rates[] = {
277 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
278 { .div = 0 }
279};
280
281static const struct clksel common_clkout_src_clksel[] = {
282 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
283 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
284 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
285 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
286 { .parent = NULL }
287};
288
289static struct clk sys_clkout_src = {
290 .name = "sys_clkout_src",
291 .ops = &clkops_omap2_dflt,
292 .parent = &func_54m_ck,
293 .clkdm_name = "wkup_clkdm",
294 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
295 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
296 .init = &omap2_init_clksel_parent,
297 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
298 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
299 .clksel = common_clkout_src_clksel,
300 .recalc = &omap2_clksel_recalc,
301 .round_rate = &omap2_clksel_round_rate,
302 .set_rate = &omap2_clksel_set_rate
303};
304
305static const struct clksel_rate common_clkout_rates[] = {
306 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
307 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
308 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
309 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
310 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
311 { .div = 0 },
312};
313
314static const struct clksel sys_clkout_clksel[] = {
315 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
316 { .parent = NULL }
317};
318
319static struct clk sys_clkout = {
320 .name = "sys_clkout",
321 .ops = &clkops_null,
322 .parent = &sys_clkout_src,
323 .clkdm_name = "wkup_clkdm",
324 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
325 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
326 .clksel = sys_clkout_clksel,
327 .recalc = &omap2_clksel_recalc,
328 .round_rate = &omap2_clksel_round_rate,
329 .set_rate = &omap2_clksel_set_rate
330};
331
332/* In 2430, new in 2420 ES2 */
333static struct clk sys_clkout2_src = {
334 .name = "sys_clkout2_src",
335 .ops = &clkops_omap2_dflt,
336 .parent = &func_54m_ck,
337 .clkdm_name = "wkup_clkdm",
338 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
339 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
340 .init = &omap2_init_clksel_parent,
341 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
342 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
343 .clksel = common_clkout_src_clksel,
344 .recalc = &omap2_clksel_recalc,
345 .round_rate = &omap2_clksel_round_rate,
346 .set_rate = &omap2_clksel_set_rate
347};
348
349static const struct clksel sys_clkout2_clksel[] = {
350 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
351 { .parent = NULL }
352};
353
354/* In 2430, new in 2420 ES2 */
355static struct clk sys_clkout2 = {
356 .name = "sys_clkout2",
357 .ops = &clkops_null,
358 .parent = &sys_clkout2_src,
359 .clkdm_name = "wkup_clkdm",
360 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
361 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
362 .clksel = sys_clkout2_clksel,
363 .recalc = &omap2_clksel_recalc,
364 .round_rate = &omap2_clksel_round_rate,
365 .set_rate = &omap2_clksel_set_rate
366};
367
368static struct clk emul_ck = {
369 .name = "emul_ck",
370 .ops = &clkops_omap2_dflt,
371 .parent = &func_54m_ck,
372 .clkdm_name = "wkup_clkdm",
373 .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
374 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
375 .recalc = &followparent_recalc,
376
377};
378
379/*
380 * MPU clock domain
381 * Clocks:
382 * MPU_FCLK, MPU_ICLK
383 * INT_M_FCLK, INT_M_I_CLK
384 *
385 * - Individual clocks are hardware managed.
386 * - Base divider comes from: CM_CLKSEL_MPU
387 *
388 */
389static const struct clksel_rate mpu_core_rates[] = {
390 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
391 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
392 { .div = 4, .val = 4, .flags = RATE_IN_242X },
393 { .div = 6, .val = 6, .flags = RATE_IN_242X },
394 { .div = 8, .val = 8, .flags = RATE_IN_242X },
395 { .div = 0 },
396};
397
398static const struct clksel mpu_clksel[] = {
399 { .parent = &core_ck, .rates = mpu_core_rates },
400 { .parent = NULL }
401};
402
403static struct clk mpu_ck = { /* Control cpu */
404 .name = "mpu_ck",
405 .ops = &clkops_null,
406 .parent = &core_ck,
407 .flags = DELAYED_APP,
408 .clkdm_name = "mpu_clkdm",
409 .init = &omap2_init_clksel_parent,
410 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
411 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
412 .clksel = mpu_clksel,
413 .recalc = &omap2_clksel_recalc,
414};
415
416/*
417 * DSP (2420-UMA+IVA1) clock domain
418 * Clocks:
419 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
420 *
421 * Won't be too specific here. The core clock comes into this block
422 * it is divided then tee'ed. One branch goes directly to xyz enable
423 * controls. The other branch gets further divided by 2 then possibly
424 * routed into a synchronizer and out of clocks abc.
425 */
426static const struct clksel_rate dsp_fck_core_rates[] = {
427 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
428 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
429 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
430 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
431 { .div = 6, .val = 6, .flags = RATE_IN_242X },
432 { .div = 8, .val = 8, .flags = RATE_IN_242X },
433 { .div = 12, .val = 12, .flags = RATE_IN_242X },
434 { .div = 0 },
435};
436
437static const struct clksel dsp_fck_clksel[] = {
438 { .parent = &core_ck, .rates = dsp_fck_core_rates },
439 { .parent = NULL }
440};
441
442static struct clk dsp_fck = {
443 .name = "dsp_fck",
444 .ops = &clkops_omap2_dflt_wait,
445 .parent = &core_ck,
446 .flags = DELAYED_APP,
447 .clkdm_name = "dsp_clkdm",
448 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
449 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
450 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
451 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
452 .clksel = dsp_fck_clksel,
453 .recalc = &omap2_clksel_recalc,
454};
455
456/* DSP interface clock */
457static const struct clksel_rate dsp_irate_ick_rates[] = {
458 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
459 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
460 { .div = 0 },
461};
462
463static const struct clksel dsp_irate_ick_clksel[] = {
464 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
465 { .parent = NULL }
466};
467
468/* This clock does not exist as such in the TRM. */
469static struct clk dsp_irate_ick = {
470 .name = "dsp_irate_ick",
471 .ops = &clkops_null,
472 .parent = &dsp_fck,
473 .flags = DELAYED_APP,
474 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
475 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
476 .clksel = dsp_irate_ick_clksel,
477 .recalc = &omap2_clksel_recalc,
478};
479
480/* 2420 only */
481static struct clk dsp_ick = {
482 .name = "dsp_ick", /* apparently ipi and isp */
483 .ops = &clkops_omap2_dflt_wait,
484 .parent = &dsp_irate_ick,
485 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
486 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
487};
488
489/*
490 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
491 * the C54x, but which is contained in the DSP powerdomain. Does not
492 * exist on later OMAPs.
493 */
494static struct clk iva1_ifck = {
495 .name = "iva1_ifck",
496 .ops = &clkops_omap2_dflt_wait,
497 .parent = &core_ck,
498 .flags = DELAYED_APP,
499 .clkdm_name = "iva1_clkdm",
500 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
501 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
502 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
503 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
504 .clksel = dsp_fck_clksel,
505 .recalc = &omap2_clksel_recalc,
506};
507
508/* IVA1 mpu/int/i/f clocks are /2 of parent */
509static struct clk iva1_mpu_int_ifck = {
510 .name = "iva1_mpu_int_ifck",
511 .ops = &clkops_omap2_dflt_wait,
512 .parent = &iva1_ifck,
513 .clkdm_name = "iva1_clkdm",
514 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
515 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
516 .fixed_div = 2,
517 .recalc = &omap_fixed_divisor_recalc,
518};
519
520/*
521 * L3 clock domain
522 * L3 clocks are used for both interface and functional clocks to
523 * multiple entities. Some of these clocks are completely managed
524 * by hardware, and some others allow software control. Hardware
525 * managed ones general are based on directly CLK_REQ signals and
526 * various auto idle settings. The functional spec sets many of these
527 * as 'tie-high' for their enables.
528 *
529 * I-CLOCKS:
530 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
531 * CAM, HS-USB.
532 * F-CLOCK
533 * SSI.
534 *
535 * GPMC memories and SDRC have timing and clock sensitive registers which
536 * may very well need notification when the clock changes. Currently for low
537 * operating points, these are taken care of in sleep.S.
538 */
539static const struct clksel_rate core_l3_core_rates[] = {
540 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
541 { .div = 2, .val = 2, .flags = RATE_IN_242X },
542 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
543 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
544 { .div = 8, .val = 8, .flags = RATE_IN_242X },
545 { .div = 12, .val = 12, .flags = RATE_IN_242X },
546 { .div = 16, .val = 16, .flags = RATE_IN_242X },
547 { .div = 0 }
548};
549
550static const struct clksel core_l3_clksel[] = {
551 { .parent = &core_ck, .rates = core_l3_core_rates },
552 { .parent = NULL }
553};
554
555static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
556 .name = "core_l3_ck",
557 .ops = &clkops_null,
558 .parent = &core_ck,
559 .flags = DELAYED_APP,
560 .clkdm_name = "core_l3_clkdm",
561 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
562 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
563 .clksel = core_l3_clksel,
564 .recalc = &omap2_clksel_recalc,
565};
566
567/* usb_l4_ick */
568static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
569 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
570 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
571 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
572 { .div = 0 }
573};
574
575static const struct clksel usb_l4_ick_clksel[] = {
576 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
577 { .parent = NULL },
578};
579
580/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
581static struct clk usb_l4_ick = { /* FS-USB interface clock */
582 .name = "usb_l4_ick",
583 .ops = &clkops_omap2_dflt_wait,
584 .parent = &core_l3_ck,
585 .flags = DELAYED_APP,
586 .clkdm_name = "core_l4_clkdm",
587 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
588 .enable_bit = OMAP24XX_EN_USB_SHIFT,
589 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
590 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
591 .clksel = usb_l4_ick_clksel,
592 .recalc = &omap2_clksel_recalc,
593};
594
595/*
596 * L4 clock management domain
597 *
598 * This domain contains lots of interface clocks from the L4 interface, some
599 * functional clocks. Fixed APLL functional source clocks are managed in
600 * this domain.
601 */
602static const struct clksel_rate l4_core_l3_rates[] = {
603 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
604 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
605 { .div = 0 }
606};
607
608static const struct clksel l4_clksel[] = {
609 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
610 { .parent = NULL }
611};
612
613static struct clk l4_ck = { /* used both as an ick and fck */
614 .name = "l4_ck",
615 .ops = &clkops_null,
616 .parent = &core_l3_ck,
617 .flags = DELAYED_APP,
618 .clkdm_name = "core_l4_clkdm",
619 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
620 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
621 .clksel = l4_clksel,
622 .recalc = &omap2_clksel_recalc,
623 .round_rate = &omap2_clksel_round_rate,
624 .set_rate = &omap2_clksel_set_rate
625};
626
627/*
628 * SSI is in L3 management domain, its direct parent is core not l3,
629 * many core power domain entities are grouped into the L3 clock
630 * domain.
631 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
632 *
633 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
634 */
635static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
636 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
637 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
638 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
639 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
640 { .div = 6, .val = 6, .flags = RATE_IN_242X },
641 { .div = 8, .val = 8, .flags = RATE_IN_242X },
642 { .div = 0 }
643};
644
645static const struct clksel ssi_ssr_sst_fck_clksel[] = {
646 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
647 { .parent = NULL }
648};
649
650static struct clk ssi_ssr_sst_fck = {
651 .name = "ssi_fck",
652 .ops = &clkops_omap2_dflt_wait,
653 .parent = &core_ck,
654 .flags = DELAYED_APP,
655 .clkdm_name = "core_l3_clkdm",
656 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
657 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
658 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
659 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
660 .clksel = ssi_ssr_sst_fck_clksel,
661 .recalc = &omap2_clksel_recalc,
662 .round_rate = &omap2_clksel_round_rate,
663 .set_rate = &omap2_clksel_set_rate
664};
665
666/*
667 * Presumably this is the same as SSI_ICLK.
668 * TRM contradicts itself on what clockdomain SSI_ICLK is in
669 */
670static struct clk ssi_l4_ick = {
671 .name = "ssi_l4_ick",
672 .ops = &clkops_omap2_dflt_wait,
673 .parent = &l4_ck,
674 .clkdm_name = "core_l4_clkdm",
675 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
676 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
677 .recalc = &followparent_recalc,
678};
679
680
681/*
682 * GFX clock domain
683 * Clocks:
684 * GFX_FCLK, GFX_ICLK
685 * GFX_CG1(2d), GFX_CG2(3d)
686 *
687 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
688 * The 2d and 3d clocks run at a hardware determined
689 * divided value of fclk.
690 *
691 */
692
693/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
694static const struct clksel gfx_fck_clksel[] = {
695 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
696 { .parent = NULL },
697};
698
699static struct clk gfx_3d_fck = {
700 .name = "gfx_3d_fck",
701 .ops = &clkops_omap2_dflt_wait,
702 .parent = &core_l3_ck,
703 .clkdm_name = "gfx_clkdm",
704 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
705 .enable_bit = OMAP24XX_EN_3D_SHIFT,
706 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
707 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
708 .clksel = gfx_fck_clksel,
709 .recalc = &omap2_clksel_recalc,
710 .round_rate = &omap2_clksel_round_rate,
711 .set_rate = &omap2_clksel_set_rate
712};
713
714static struct clk gfx_2d_fck = {
715 .name = "gfx_2d_fck",
716 .ops = &clkops_omap2_dflt_wait,
717 .parent = &core_l3_ck,
718 .flags = DELAYED_APP,
719 .clkdm_name = "gfx_clkdm",
720 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
721 .enable_bit = OMAP24XX_EN_2D_SHIFT,
722 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
723 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
724 .clksel = gfx_fck_clksel,
725 .recalc = &omap2_clksel_recalc,
726};
727
728static struct clk gfx_ick = {
729 .name = "gfx_ick", /* From l3 */
730 .ops = &clkops_omap2_dflt_wait,
731 .parent = &core_l3_ck,
732 .clkdm_name = "gfx_clkdm",
733 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
734 .enable_bit = OMAP_EN_GFX_SHIFT,
735 .recalc = &followparent_recalc,
736};
737
738/*
739 * DSS clock domain
740 * CLOCKs:
741 * DSS_L4_ICLK, DSS_L3_ICLK,
742 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
743 *
744 * DSS is both initiator and target.
745 */
746/* XXX Add RATE_NOT_VALIDATED */
747
748static const struct clksel_rate dss1_fck_sys_rates[] = {
749 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
750 { .div = 0 }
751};
752
753static const struct clksel_rate dss1_fck_core_rates[] = {
754 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
755 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
756 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
757 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
758 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
759 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
760 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
761 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
762 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
763 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
764 { .div = 0 }
765};
766
767static const struct clksel dss1_fck_clksel[] = {
768 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
769 { .parent = &core_ck, .rates = dss1_fck_core_rates },
770 { .parent = NULL },
771};
772
773static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
774 .name = "dss_ick",
775 .ops = &clkops_omap2_dflt,
776 .parent = &l4_ck, /* really both l3 and l4 */
777 .clkdm_name = "dss_clkdm",
778 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
779 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
780 .recalc = &followparent_recalc,
781};
782
783static struct clk dss1_fck = {
784 .name = "dss1_fck",
785 .ops = &clkops_omap2_dflt,
786 .parent = &core_ck, /* Core or sys */
787 .flags = DELAYED_APP,
788 .clkdm_name = "dss_clkdm",
789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
790 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
791 .init = &omap2_init_clksel_parent,
792 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
793 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
794 .clksel = dss1_fck_clksel,
795 .recalc = &omap2_clksel_recalc,
796 .round_rate = &omap2_clksel_round_rate,
797 .set_rate = &omap2_clksel_set_rate
798};
799
800static const struct clksel_rate dss2_fck_sys_rates[] = {
801 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
802 { .div = 0 }
803};
804
805static const struct clksel_rate dss2_fck_48m_rates[] = {
806 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
807 { .div = 0 }
808};
809
810static const struct clksel dss2_fck_clksel[] = {
811 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
812 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
813 { .parent = NULL }
814};
815
816static struct clk dss2_fck = { /* Alt clk used in power management */
817 .name = "dss2_fck",
818 .ops = &clkops_omap2_dflt,
819 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
820 .flags = DELAYED_APP,
821 .clkdm_name = "dss_clkdm",
822 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
823 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
824 .init = &omap2_init_clksel_parent,
825 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
826 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
827 .clksel = dss2_fck_clksel,
828 .recalc = &followparent_recalc,
829};
830
831static struct clk dss_54m_fck = { /* Alt clk used in power management */
832 .name = "dss_54m_fck", /* 54m tv clk */
833 .ops = &clkops_omap2_dflt_wait,
834 .parent = &func_54m_ck,
835 .clkdm_name = "dss_clkdm",
836 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
837 .enable_bit = OMAP24XX_EN_TV_SHIFT,
838 .recalc = &followparent_recalc,
839};
840
841/*
842 * CORE power domain ICLK & FCLK defines.
843 * Many of the these can have more than one possible parent. Entries
844 * here will likely have an L4 interface parent, and may have multiple
845 * functional clock parents.
846 */
847static const struct clksel_rate gpt_alt_rates[] = {
848 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
849 { .div = 0 }
850};
851
852static const struct clksel omap24xx_gpt_clksel[] = {
853 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
854 { .parent = &sys_ck, .rates = gpt_sys_rates },
855 { .parent = &alt_ck, .rates = gpt_alt_rates },
856 { .parent = NULL },
857};
858
859static struct clk gpt1_ick = {
860 .name = "gpt1_ick",
861 .ops = &clkops_omap2_dflt_wait,
862 .parent = &l4_ck,
863 .clkdm_name = "core_l4_clkdm",
864 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
865 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
866 .recalc = &followparent_recalc,
867};
868
869static struct clk gpt1_fck = {
870 .name = "gpt1_fck",
871 .ops = &clkops_omap2_dflt_wait,
872 .parent = &func_32k_ck,
873 .clkdm_name = "core_l4_clkdm",
874 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
875 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
876 .init = &omap2_init_clksel_parent,
877 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
878 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
879 .clksel = omap24xx_gpt_clksel,
880 .recalc = &omap2_clksel_recalc,
881 .round_rate = &omap2_clksel_round_rate,
882 .set_rate = &omap2_clksel_set_rate
883};
884
885static struct clk gpt2_ick = {
886 .name = "gpt2_ick",
887 .ops = &clkops_omap2_dflt_wait,
888 .parent = &l4_ck,
889 .clkdm_name = "core_l4_clkdm",
890 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
891 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
892 .recalc = &followparent_recalc,
893};
894
895static struct clk gpt2_fck = {
896 .name = "gpt2_fck",
897 .ops = &clkops_omap2_dflt_wait,
898 .parent = &func_32k_ck,
899 .clkdm_name = "core_l4_clkdm",
900 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
901 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
902 .init = &omap2_init_clksel_parent,
903 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
904 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
905 .clksel = omap24xx_gpt_clksel,
906 .recalc = &omap2_clksel_recalc,
907};
908
909static struct clk gpt3_ick = {
910 .name = "gpt3_ick",
911 .ops = &clkops_omap2_dflt_wait,
912 .parent = &l4_ck,
913 .clkdm_name = "core_l4_clkdm",
914 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
915 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
916 .recalc = &followparent_recalc,
917};
918
919static struct clk gpt3_fck = {
920 .name = "gpt3_fck",
921 .ops = &clkops_omap2_dflt_wait,
922 .parent = &func_32k_ck,
923 .clkdm_name = "core_l4_clkdm",
924 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
925 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
926 .init = &omap2_init_clksel_parent,
927 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
928 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
929 .clksel = omap24xx_gpt_clksel,
930 .recalc = &omap2_clksel_recalc,
931};
932
933static struct clk gpt4_ick = {
934 .name = "gpt4_ick",
935 .ops = &clkops_omap2_dflt_wait,
936 .parent = &l4_ck,
937 .clkdm_name = "core_l4_clkdm",
938 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
939 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
940 .recalc = &followparent_recalc,
941};
942
943static struct clk gpt4_fck = {
944 .name = "gpt4_fck",
945 .ops = &clkops_omap2_dflt_wait,
946 .parent = &func_32k_ck,
947 .clkdm_name = "core_l4_clkdm",
948 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
949 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
950 .init = &omap2_init_clksel_parent,
951 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
952 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
953 .clksel = omap24xx_gpt_clksel,
954 .recalc = &omap2_clksel_recalc,
955};
956
957static struct clk gpt5_ick = {
958 .name = "gpt5_ick",
959 .ops = &clkops_omap2_dflt_wait,
960 .parent = &l4_ck,
961 .clkdm_name = "core_l4_clkdm",
962 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
963 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
964 .recalc = &followparent_recalc,
965};
966
967static struct clk gpt5_fck = {
968 .name = "gpt5_fck",
969 .ops = &clkops_omap2_dflt_wait,
970 .parent = &func_32k_ck,
971 .clkdm_name = "core_l4_clkdm",
972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
973 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
974 .init = &omap2_init_clksel_parent,
975 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
976 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
977 .clksel = omap24xx_gpt_clksel,
978 .recalc = &omap2_clksel_recalc,
979};
980
981static struct clk gpt6_ick = {
982 .name = "gpt6_ick",
983 .ops = &clkops_omap2_dflt_wait,
984 .parent = &l4_ck,
985 .clkdm_name = "core_l4_clkdm",
986 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
987 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
988 .recalc = &followparent_recalc,
989};
990
991static struct clk gpt6_fck = {
992 .name = "gpt6_fck",
993 .ops = &clkops_omap2_dflt_wait,
994 .parent = &func_32k_ck,
995 .clkdm_name = "core_l4_clkdm",
996 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
997 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
998 .init = &omap2_init_clksel_parent,
999 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1000 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
1001 .clksel = omap24xx_gpt_clksel,
1002 .recalc = &omap2_clksel_recalc,
1003};
1004
1005static struct clk gpt7_ick = {
1006 .name = "gpt7_ick",
1007 .ops = &clkops_omap2_dflt_wait,
1008 .parent = &l4_ck,
1009 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1010 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1011 .recalc = &followparent_recalc,
1012};
1013
1014static struct clk gpt7_fck = {
1015 .name = "gpt7_fck",
1016 .ops = &clkops_omap2_dflt_wait,
1017 .parent = &func_32k_ck,
1018 .clkdm_name = "core_l4_clkdm",
1019 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1020 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1021 .init = &omap2_init_clksel_parent,
1022 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1023 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1024 .clksel = omap24xx_gpt_clksel,
1025 .recalc = &omap2_clksel_recalc,
1026};
1027
1028static struct clk gpt8_ick = {
1029 .name = "gpt8_ick",
1030 .ops = &clkops_omap2_dflt_wait,
1031 .parent = &l4_ck,
1032 .clkdm_name = "core_l4_clkdm",
1033 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1034 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1035 .recalc = &followparent_recalc,
1036};
1037
1038static struct clk gpt8_fck = {
1039 .name = "gpt8_fck",
1040 .ops = &clkops_omap2_dflt_wait,
1041 .parent = &func_32k_ck,
1042 .clkdm_name = "core_l4_clkdm",
1043 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1044 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1045 .init = &omap2_init_clksel_parent,
1046 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1047 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1048 .clksel = omap24xx_gpt_clksel,
1049 .recalc = &omap2_clksel_recalc,
1050};
1051
1052static struct clk gpt9_ick = {
1053 .name = "gpt9_ick",
1054 .ops = &clkops_omap2_dflt_wait,
1055 .parent = &l4_ck,
1056 .clkdm_name = "core_l4_clkdm",
1057 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1058 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1059 .recalc = &followparent_recalc,
1060};
1061
1062static struct clk gpt9_fck = {
1063 .name = "gpt9_fck",
1064 .ops = &clkops_omap2_dflt_wait,
1065 .parent = &func_32k_ck,
1066 .clkdm_name = "core_l4_clkdm",
1067 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1068 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1069 .init = &omap2_init_clksel_parent,
1070 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1071 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1072 .clksel = omap24xx_gpt_clksel,
1073 .recalc = &omap2_clksel_recalc,
1074};
1075
1076static struct clk gpt10_ick = {
1077 .name = "gpt10_ick",
1078 .ops = &clkops_omap2_dflt_wait,
1079 .parent = &l4_ck,
1080 .clkdm_name = "core_l4_clkdm",
1081 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1082 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1083 .recalc = &followparent_recalc,
1084};
1085
1086static struct clk gpt10_fck = {
1087 .name = "gpt10_fck",
1088 .ops = &clkops_omap2_dflt_wait,
1089 .parent = &func_32k_ck,
1090 .clkdm_name = "core_l4_clkdm",
1091 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1092 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1093 .init = &omap2_init_clksel_parent,
1094 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1095 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1096 .clksel = omap24xx_gpt_clksel,
1097 .recalc = &omap2_clksel_recalc,
1098};
1099
1100static struct clk gpt11_ick = {
1101 .name = "gpt11_ick",
1102 .ops = &clkops_omap2_dflt_wait,
1103 .parent = &l4_ck,
1104 .clkdm_name = "core_l4_clkdm",
1105 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1106 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1107 .recalc = &followparent_recalc,
1108};
1109
1110static struct clk gpt11_fck = {
1111 .name = "gpt11_fck",
1112 .ops = &clkops_omap2_dflt_wait,
1113 .parent = &func_32k_ck,
1114 .clkdm_name = "core_l4_clkdm",
1115 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1116 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1117 .init = &omap2_init_clksel_parent,
1118 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1119 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1120 .clksel = omap24xx_gpt_clksel,
1121 .recalc = &omap2_clksel_recalc,
1122};
1123
1124static struct clk gpt12_ick = {
1125 .name = "gpt12_ick",
1126 .ops = &clkops_omap2_dflt_wait,
1127 .parent = &l4_ck,
1128 .clkdm_name = "core_l4_clkdm",
1129 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1130 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1131 .recalc = &followparent_recalc,
1132};
1133
1134static struct clk gpt12_fck = {
1135 .name = "gpt12_fck",
1136 .ops = &clkops_omap2_dflt_wait,
1137 .parent = &secure_32k_ck,
1138 .clkdm_name = "core_l4_clkdm",
1139 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1140 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1141 .init = &omap2_init_clksel_parent,
1142 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1143 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1144 .clksel = omap24xx_gpt_clksel,
1145 .recalc = &omap2_clksel_recalc,
1146};
1147
1148static struct clk mcbsp1_ick = {
1149 .name = "mcbsp1_ick",
1150 .ops = &clkops_omap2_dflt_wait,
1151 .parent = &l4_ck,
1152 .clkdm_name = "core_l4_clkdm",
1153 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1154 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1155 .recalc = &followparent_recalc,
1156};
1157
1158static struct clk mcbsp1_fck = {
1159 .name = "mcbsp1_fck",
1160 .ops = &clkops_omap2_dflt_wait,
1161 .parent = &func_96m_ck,
1162 .clkdm_name = "core_l4_clkdm",
1163 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1164 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1165 .recalc = &followparent_recalc,
1166};
1167
1168static struct clk mcbsp2_ick = {
1169 .name = "mcbsp2_ick",
1170 .ops = &clkops_omap2_dflt_wait,
1171 .parent = &l4_ck,
1172 .clkdm_name = "core_l4_clkdm",
1173 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1174 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1175 .recalc = &followparent_recalc,
1176};
1177
1178static struct clk mcbsp2_fck = {
1179 .name = "mcbsp2_fck",
1180 .ops = &clkops_omap2_dflt_wait,
1181 .parent = &func_96m_ck,
1182 .clkdm_name = "core_l4_clkdm",
1183 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1184 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1185 .recalc = &followparent_recalc,
1186};
1187
1188static struct clk mcspi1_ick = {
1189 .name = "mcspi1_ick",
1190 .ops = &clkops_omap2_dflt_wait,
1191 .parent = &l4_ck,
1192 .clkdm_name = "core_l4_clkdm",
1193 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1194 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1195 .recalc = &followparent_recalc,
1196};
1197
1198static struct clk mcspi1_fck = {
1199 .name = "mcspi1_fck",
1200 .ops = &clkops_omap2_dflt_wait,
1201 .parent = &func_48m_ck,
1202 .clkdm_name = "core_l4_clkdm",
1203 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1204 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1205 .recalc = &followparent_recalc,
1206};
1207
1208static struct clk mcspi2_ick = {
1209 .name = "mcspi2_ick",
1210 .ops = &clkops_omap2_dflt_wait,
1211 .parent = &l4_ck,
1212 .clkdm_name = "core_l4_clkdm",
1213 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1214 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1215 .recalc = &followparent_recalc,
1216};
1217
1218static struct clk mcspi2_fck = {
1219 .name = "mcspi2_fck",
1220 .ops = &clkops_omap2_dflt_wait,
1221 .parent = &func_48m_ck,
1222 .clkdm_name = "core_l4_clkdm",
1223 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1224 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1225 .recalc = &followparent_recalc,
1226};
1227
1228static struct clk uart1_ick = {
1229 .name = "uart1_ick",
1230 .ops = &clkops_omap2_dflt_wait,
1231 .parent = &l4_ck,
1232 .clkdm_name = "core_l4_clkdm",
1233 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1234 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1235 .recalc = &followparent_recalc,
1236};
1237
1238static struct clk uart1_fck = {
1239 .name = "uart1_fck",
1240 .ops = &clkops_omap2_dflt_wait,
1241 .parent = &func_48m_ck,
1242 .clkdm_name = "core_l4_clkdm",
1243 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1244 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1245 .recalc = &followparent_recalc,
1246};
1247
1248static struct clk uart2_ick = {
1249 .name = "uart2_ick",
1250 .ops = &clkops_omap2_dflt_wait,
1251 .parent = &l4_ck,
1252 .clkdm_name = "core_l4_clkdm",
1253 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1254 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1255 .recalc = &followparent_recalc,
1256};
1257
1258static struct clk uart2_fck = {
1259 .name = "uart2_fck",
1260 .ops = &clkops_omap2_dflt_wait,
1261 .parent = &func_48m_ck,
1262 .clkdm_name = "core_l4_clkdm",
1263 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1264 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1265 .recalc = &followparent_recalc,
1266};
1267
1268static struct clk uart3_ick = {
1269 .name = "uart3_ick",
1270 .ops = &clkops_omap2_dflt_wait,
1271 .parent = &l4_ck,
1272 .clkdm_name = "core_l4_clkdm",
1273 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1274 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1275 .recalc = &followparent_recalc,
1276};
1277
1278static struct clk uart3_fck = {
1279 .name = "uart3_fck",
1280 .ops = &clkops_omap2_dflt_wait,
1281 .parent = &func_48m_ck,
1282 .clkdm_name = "core_l4_clkdm",
1283 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1284 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1285 .recalc = &followparent_recalc,
1286};
1287
1288static struct clk gpios_ick = {
1289 .name = "gpios_ick",
1290 .ops = &clkops_omap2_dflt_wait,
1291 .parent = &l4_ck,
1292 .clkdm_name = "core_l4_clkdm",
1293 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1294 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1295 .recalc = &followparent_recalc,
1296};
1297
1298static struct clk gpios_fck = {
1299 .name = "gpios_fck",
1300 .ops = &clkops_omap2_dflt_wait,
1301 .parent = &func_32k_ck,
1302 .clkdm_name = "wkup_clkdm",
1303 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1304 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1305 .recalc = &followparent_recalc,
1306};
1307
1308static struct clk mpu_wdt_ick = {
1309 .name = "mpu_wdt_ick",
1310 .ops = &clkops_omap2_dflt_wait,
1311 .parent = &l4_ck,
1312 .clkdm_name = "core_l4_clkdm",
1313 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1314 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1315 .recalc = &followparent_recalc,
1316};
1317
1318static struct clk mpu_wdt_fck = {
1319 .name = "mpu_wdt_fck",
1320 .ops = &clkops_omap2_dflt_wait,
1321 .parent = &func_32k_ck,
1322 .clkdm_name = "wkup_clkdm",
1323 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1324 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1325 .recalc = &followparent_recalc,
1326};
1327
1328static struct clk sync_32k_ick = {
1329 .name = "sync_32k_ick",
1330 .ops = &clkops_omap2_dflt_wait,
1331 .parent = &l4_ck,
1332 .flags = ENABLE_ON_INIT,
1333 .clkdm_name = "core_l4_clkdm",
1334 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1335 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1336 .recalc = &followparent_recalc,
1337};
1338
1339static struct clk wdt1_ick = {
1340 .name = "wdt1_ick",
1341 .ops = &clkops_omap2_dflt_wait,
1342 .parent = &l4_ck,
1343 .clkdm_name = "core_l4_clkdm",
1344 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1345 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1346 .recalc = &followparent_recalc,
1347};
1348
1349static struct clk omapctrl_ick = {
1350 .name = "omapctrl_ick",
1351 .ops = &clkops_omap2_dflt_wait,
1352 .parent = &l4_ck,
1353 .flags = ENABLE_ON_INIT,
1354 .clkdm_name = "core_l4_clkdm",
1355 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1356 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1357 .recalc = &followparent_recalc,
1358};
1359
1360static struct clk cam_ick = {
1361 .name = "cam_ick",
1362 .ops = &clkops_omap2_dflt,
1363 .parent = &l4_ck,
1364 .clkdm_name = "core_l4_clkdm",
1365 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1366 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1367 .recalc = &followparent_recalc,
1368};
1369
1370/*
1371 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1372 * split into two separate clocks, since the parent clocks are different
1373 * and the clockdomains are also different.
1374 */
1375static struct clk cam_fck = {
1376 .name = "cam_fck",
1377 .ops = &clkops_omap2_dflt,
1378 .parent = &func_96m_ck,
1379 .clkdm_name = "core_l3_clkdm",
1380 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1381 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1382 .recalc = &followparent_recalc,
1383};
1384
1385static struct clk mailboxes_ick = {
1386 .name = "mailboxes_ick",
1387 .ops = &clkops_omap2_dflt_wait,
1388 .parent = &l4_ck,
1389 .clkdm_name = "core_l4_clkdm",
1390 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1391 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1392 .recalc = &followparent_recalc,
1393};
1394
1395static struct clk wdt4_ick = {
1396 .name = "wdt4_ick",
1397 .ops = &clkops_omap2_dflt_wait,
1398 .parent = &l4_ck,
1399 .clkdm_name = "core_l4_clkdm",
1400 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1401 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1402 .recalc = &followparent_recalc,
1403};
1404
1405static struct clk wdt4_fck = {
1406 .name = "wdt4_fck",
1407 .ops = &clkops_omap2_dflt_wait,
1408 .parent = &func_32k_ck,
1409 .clkdm_name = "core_l4_clkdm",
1410 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1411 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1412 .recalc = &followparent_recalc,
1413};
1414
1415static struct clk wdt3_ick = {
1416 .name = "wdt3_ick",
1417 .ops = &clkops_omap2_dflt_wait,
1418 .parent = &l4_ck,
1419 .clkdm_name = "core_l4_clkdm",
1420 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1421 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1422 .recalc = &followparent_recalc,
1423};
1424
1425static struct clk wdt3_fck = {
1426 .name = "wdt3_fck",
1427 .ops = &clkops_omap2_dflt_wait,
1428 .parent = &func_32k_ck,
1429 .clkdm_name = "core_l4_clkdm",
1430 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1431 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1432 .recalc = &followparent_recalc,
1433};
1434
1435static struct clk mspro_ick = {
1436 .name = "mspro_ick",
1437 .ops = &clkops_omap2_dflt_wait,
1438 .parent = &l4_ck,
1439 .clkdm_name = "core_l4_clkdm",
1440 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1441 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1442 .recalc = &followparent_recalc,
1443};
1444
1445static struct clk mspro_fck = {
1446 .name = "mspro_fck",
1447 .ops = &clkops_omap2_dflt_wait,
1448 .parent = &func_96m_ck,
1449 .clkdm_name = "core_l4_clkdm",
1450 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1451 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1452 .recalc = &followparent_recalc,
1453};
1454
1455static struct clk mmc_ick = {
1456 .name = "mmc_ick",
1457 .ops = &clkops_omap2_dflt_wait,
1458 .parent = &l4_ck,
1459 .clkdm_name = "core_l4_clkdm",
1460 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1461 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1462 .recalc = &followparent_recalc,
1463};
1464
1465static struct clk mmc_fck = {
1466 .name = "mmc_fck",
1467 .ops = &clkops_omap2_dflt_wait,
1468 .parent = &func_96m_ck,
1469 .clkdm_name = "core_l4_clkdm",
1470 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1471 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1472 .recalc = &followparent_recalc,
1473};
1474
1475static struct clk fac_ick = {
1476 .name = "fac_ick",
1477 .ops = &clkops_omap2_dflt_wait,
1478 .parent = &l4_ck,
1479 .clkdm_name = "core_l4_clkdm",
1480 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1481 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1482 .recalc = &followparent_recalc,
1483};
1484
1485static struct clk fac_fck = {
1486 .name = "fac_fck",
1487 .ops = &clkops_omap2_dflt_wait,
1488 .parent = &func_12m_ck,
1489 .clkdm_name = "core_l4_clkdm",
1490 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1491 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1492 .recalc = &followparent_recalc,
1493};
1494
1495static struct clk eac_ick = {
1496 .name = "eac_ick",
1497 .ops = &clkops_omap2_dflt_wait,
1498 .parent = &l4_ck,
1499 .clkdm_name = "core_l4_clkdm",
1500 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1501 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1502 .recalc = &followparent_recalc,
1503};
1504
1505static struct clk eac_fck = {
1506 .name = "eac_fck",
1507 .ops = &clkops_omap2_dflt_wait,
1508 .parent = &func_96m_ck,
1509 .clkdm_name = "core_l4_clkdm",
1510 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1511 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1512 .recalc = &followparent_recalc,
1513};
1514
1515static struct clk hdq_ick = {
1516 .name = "hdq_ick",
1517 .ops = &clkops_omap2_dflt_wait,
1518 .parent = &l4_ck,
1519 .clkdm_name = "core_l4_clkdm",
1520 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1521 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1522 .recalc = &followparent_recalc,
1523};
1524
1525static struct clk hdq_fck = {
1526 .name = "hdq_fck",
1527 .ops = &clkops_omap2_dflt_wait,
1528 .parent = &func_12m_ck,
1529 .clkdm_name = "core_l4_clkdm",
1530 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1531 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1532 .recalc = &followparent_recalc,
1533};
1534
1535static struct clk i2c2_ick = {
1536 .name = "i2c2_ick",
1537 .ops = &clkops_omap2_dflt_wait,
1538 .parent = &l4_ck,
1539 .clkdm_name = "core_l4_clkdm",
1540 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1541 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1542 .recalc = &followparent_recalc,
1543};
1544
1545static struct clk i2c2_fck = {
1546 .name = "i2c2_fck",
1547 .ops = &clkops_omap2_dflt_wait,
1548 .parent = &func_12m_ck,
1549 .clkdm_name = "core_l4_clkdm",
1550 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1551 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1552 .recalc = &followparent_recalc,
1553};
1554
1555static struct clk i2c1_ick = {
1556 .name = "i2c1_ick",
1557 .ops = &clkops_omap2_dflt_wait,
1558 .parent = &l4_ck,
1559 .clkdm_name = "core_l4_clkdm",
1560 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1561 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1562 .recalc = &followparent_recalc,
1563};
1564
1565static struct clk i2c1_fck = {
1566 .name = "i2c1_fck",
1567 .ops = &clkops_omap2_dflt_wait,
1568 .parent = &func_12m_ck,
1569 .clkdm_name = "core_l4_clkdm",
1570 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1571 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1572 .recalc = &followparent_recalc,
1573};
1574
1575static struct clk gpmc_fck = {
1576 .name = "gpmc_fck",
1577 .ops = &clkops_null, /* RMK: missing? */
1578 .parent = &core_l3_ck,
1579 .flags = ENABLE_ON_INIT,
1580 .clkdm_name = "core_l3_clkdm",
1581 .recalc = &followparent_recalc,
1582};
1583
1584static struct clk sdma_fck = {
1585 .name = "sdma_fck",
1586 .ops = &clkops_null, /* RMK: missing? */
1587 .parent = &core_l3_ck,
1588 .clkdm_name = "core_l3_clkdm",
1589 .recalc = &followparent_recalc,
1590};
1591
1592static struct clk sdma_ick = {
1593 .name = "sdma_ick",
1594 .ops = &clkops_null, /* RMK: missing? */
1595 .parent = &l4_ck,
1596 .clkdm_name = "core_l3_clkdm",
1597 .recalc = &followparent_recalc,
1598};
1599
1600static struct clk vlynq_ick = {
1601 .name = "vlynq_ick",
1602 .ops = &clkops_omap2_dflt_wait,
1603 .parent = &core_l3_ck,
1604 .clkdm_name = "core_l3_clkdm",
1605 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1606 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1607 .recalc = &followparent_recalc,
1608};
1609
1610static const struct clksel_rate vlynq_fck_96m_rates[] = {
1611 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
1612 { .div = 0 }
1613};
1614
1615static const struct clksel_rate vlynq_fck_core_rates[] = {
1616 { .div = 1, .val = 1, .flags = RATE_IN_242X },
1617 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1618 { .div = 3, .val = 3, .flags = RATE_IN_242X },
1619 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1620 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1621 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1622 { .div = 9, .val = 9, .flags = RATE_IN_242X },
1623 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1624 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
1625 { .div = 18, .val = 18, .flags = RATE_IN_242X },
1626 { .div = 0 }
1627};
1628
1629static const struct clksel vlynq_fck_clksel[] = {
1630 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1631 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
1632 { .parent = NULL }
1633};
1634
1635static struct clk vlynq_fck = {
1636 .name = "vlynq_fck",
1637 .ops = &clkops_omap2_dflt_wait,
1638 .parent = &func_96m_ck,
1639 .flags = DELAYED_APP,
1640 .clkdm_name = "core_l3_clkdm",
1641 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1642 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1643 .init = &omap2_init_clksel_parent,
1644 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1645 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
1646 .clksel = vlynq_fck_clksel,
1647 .recalc = &omap2_clksel_recalc,
1648 .round_rate = &omap2_clksel_round_rate,
1649 .set_rate = &omap2_clksel_set_rate
1650};
1651
1652static struct clk des_ick = {
1653 .name = "des_ick",
1654 .ops = &clkops_omap2_dflt_wait,
1655 .parent = &l4_ck,
1656 .clkdm_name = "core_l4_clkdm",
1657 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1658 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1659 .recalc = &followparent_recalc,
1660};
1661
1662static struct clk sha_ick = {
1663 .name = "sha_ick",
1664 .ops = &clkops_omap2_dflt_wait,
1665 .parent = &l4_ck,
1666 .clkdm_name = "core_l4_clkdm",
1667 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1668 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1669 .recalc = &followparent_recalc,
1670};
1671
1672static struct clk rng_ick = {
1673 .name = "rng_ick",
1674 .ops = &clkops_omap2_dflt_wait,
1675 .parent = &l4_ck,
1676 .clkdm_name = "core_l4_clkdm",
1677 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1678 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1679 .recalc = &followparent_recalc,
1680};
1681
1682static struct clk aes_ick = {
1683 .name = "aes_ick",
1684 .ops = &clkops_omap2_dflt_wait,
1685 .parent = &l4_ck,
1686 .clkdm_name = "core_l4_clkdm",
1687 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1688 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1689 .recalc = &followparent_recalc,
1690};
1691
1692static struct clk pka_ick = {
1693 .name = "pka_ick",
1694 .ops = &clkops_omap2_dflt_wait,
1695 .parent = &l4_ck,
1696 .clkdm_name = "core_l4_clkdm",
1697 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1698 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1699 .recalc = &followparent_recalc,
1700};
1701
1702static struct clk usb_fck = {
1703 .name = "usb_fck",
1704 .ops = &clkops_omap2_dflt_wait,
1705 .parent = &func_48m_ck,
1706 .clkdm_name = "core_l3_clkdm",
1707 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1708 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1709 .recalc = &followparent_recalc,
1710};
1711
1712/*
1713 * This clock is a composite clock which does entire set changes then
1714 * forces a rebalance. It keys on the MPU speed, but it really could
1715 * be any key speed part of a set in the rate table.
1716 *
1717 * to really change a set, you need memory table sets which get changed
1718 * in sram, pre-notifiers & post notifiers, changing the top set, without
1719 * having low level display recalc's won't work... this is why dpm notifiers
1720 * work, isr's off, walk a list of clocks already _off_ and not messing with
1721 * the bus.
1722 *
1723 * This clock should have no parent. It embodies the entire upper level
1724 * active set. A parent will mess up some of the init also.
1725 */
1726static struct clk virt_prcm_set = {
1727 .name = "virt_prcm_set",
1728 .ops = &clkops_null,
1729 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1730 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
1731 .set_rate = &omap2_select_table_rate,
1732 .round_rate = &omap2_round_to_table_rate,
1733};
1734
1735
1736/*
1737 * clkdev integration
1738 */
1739
1740static struct omap_clk omap2420_clks[] = {
1741 /* external root sources */
1742 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X),
1743 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X),
1744 CLK(NULL, "osc_ck", &osc_ck, CK_242X),
1745 CLK(NULL, "sys_ck", &sys_ck, CK_242X),
1746 CLK(NULL, "alt_ck", &alt_ck, CK_242X),
1747 /* internal analog sources */
1748 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
1749 CLK(NULL, "apll96_ck", &apll96_ck, CK_242X),
1750 CLK(NULL, "apll54_ck", &apll54_ck, CK_242X),
1751 /* internal prcm root sources */
1752 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
1753 CLK(NULL, "core_ck", &core_ck, CK_242X),
1754 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
1755 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
1756 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
1757 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X),
1758 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
1759 CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
1760 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
1761 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
1762 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
1763 /* mpu domain clocks */
1764 CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
1765 /* dsp domain clocks */
1766 CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
1767 CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_242X),
1768 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
1769 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
1770 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
1771 /* GFX domain clocks */
1772 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X),
1773 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
1774 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
1775 /* DSS domain clocks */
1776 CLK("omapdss", "ick", &dss_ick, CK_242X),
1777 CLK("omapdss", "dss1_fck", &dss1_fck, CK_242X),
1778 CLK("omapdss", "dss2_fck", &dss2_fck, CK_242X),
1779 CLK("omapdss", "tv_fck", &dss_54m_fck, CK_242X),
1780 /* L3 domain clocks */
1781 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
1782 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
1783 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X),
1784 /* L4 domain clocks */
1785 CLK(NULL, "l4_ck", &l4_ck, CK_242X),
1786 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
1787 /* virtual meta-group clock */
1788 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
1789 /* general l4 interface ck, multi-parent functional clk */
1790 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
1791 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
1792 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
1793 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
1794 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
1795 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
1796 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
1797 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
1798 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
1799 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
1800 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
1801 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
1802 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
1803 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
1804 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
1805 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
1806 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
1807 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
1808 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
1809 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
1810 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
1811 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
1812 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
1813 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
1814 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
1815 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X),
1816 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
1817 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_242X),
1818 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
1819 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_242X),
1820 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
1821 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_242X),
1822 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
1823 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
1824 CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
1825 CLK(NULL, "uart2_fck", &uart2_fck, CK_242X),
1826 CLK(NULL, "uart3_ick", &uart3_ick, CK_242X),
1827 CLK(NULL, "uart3_fck", &uart3_fck, CK_242X),
1828 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
1829 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
1830 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
1831 CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_242X),
1832 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
1833 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
1834 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
1835 CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
1836 CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
1837 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
1838 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
1839 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
1840 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
1841 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
1842 CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
1843 CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
1844 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
1845 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
1846 CLK(NULL, "fac_ick", &fac_ick, CK_242X),
1847 CLK(NULL, "fac_fck", &fac_fck, CK_242X),
1848 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
1849 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
1850 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
1851 CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X),
1852 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_242X),
1853 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X),
1854 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_242X),
1855 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X),
1856 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
1857 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
1858 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
1859 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
1860 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
1861 CLK(NULL, "des_ick", &des_ick, CK_242X),
1862 CLK(NULL, "sha_ick", &sha_ick, CK_242X),
1863 CLK("omap_rng", "ick", &rng_ick, CK_242X),
1864 CLK(NULL, "aes_ick", &aes_ick, CK_242X),
1865 CLK(NULL, "pka_ick", &pka_ick, CK_242X),
1866 CLK(NULL, "usb_fck", &usb_fck, CK_242X),
1867};
1868
1869/*
1870 * init code
1871 */
1872
1873int __init omap2420_clk_init(void)
1874{
1875 const struct prcm_config *prcm;
1876 struct omap_clk *c;
1877 u32 clkrate;
1878
1879 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1880 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
1881 cpu_mask = RATE_IN_242X;
1882 rate_table = omap2420_rate_table;
1883
1884 clk_init(&omap2_clk_functions);
1885
1886 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1887 c++)
1888 clk_preinit(c->lk.clk);
1889
1890 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
1891 propagate_rate(&osc_ck);
1892 sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
1893 propagate_rate(&sys_ck);
1894
1895 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1896 c++) {
1897 clkdev_add(&c->lk);
1898 clk_register(c->lk.clk);
1899 omap2_init_clk_clkdm(c->lk.clk);
1900 }
1901
1902 /* Check the MPU rate set by bootloader */
1903 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
1904 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1905 if (!(prcm->flags & cpu_mask))
1906 continue;
1907 if (prcm->xtal_speed != sys_ck.rate)
1908 continue;
1909 if (prcm->dpll_speed <= clkrate)
1910 break;
1911 }
1912 curr_prcm_set = prcm;
1913
1914 recalculate_root_clocks();
1915
1916 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1917 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1918 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1919
1920 /*
1921 * Only enable those clocks we will need, let the drivers
1922 * enable other clocks as necessary
1923 */
1924 clk_enable_init_clocks();
1925
1926 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1927 vclk = clk_get(NULL, "virt_prcm_set");
1928 sclk = clk_get(NULL, "sys_ck");
1929 dclk = clk_get(NULL, "dpll_ck");
1930
1931 return 0;
1932}
1933
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 02:01:11 -0500