diff options
Diffstat (limited to 'arch/arm/mach-omap2/clock2420_data.c')
-rw-r--r-- | arch/arm/mach-omap2/clock2420_data.c | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 49adb0eec428..d5913f01e5d6 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c | |||
@@ -404,7 +404,6 @@ static struct clk mpu_ck = { /* Control cpu */ | |||
404 | .name = "mpu_ck", | 404 | .name = "mpu_ck", |
405 | .ops = &clkops_null, | 405 | .ops = &clkops_null, |
406 | .parent = &core_ck, | 406 | .parent = &core_ck, |
407 | .flags = DELAYED_APP, | ||
408 | .clkdm_name = "mpu_clkdm", | 407 | .clkdm_name = "mpu_clkdm", |
409 | .init = &omap2_init_clksel_parent, | 408 | .init = &omap2_init_clksel_parent, |
410 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | 409 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), |
@@ -443,7 +442,6 @@ static struct clk dsp_fck = { | |||
443 | .name = "dsp_fck", | 442 | .name = "dsp_fck", |
444 | .ops = &clkops_omap2_dflt_wait, | 443 | .ops = &clkops_omap2_dflt_wait, |
445 | .parent = &core_ck, | 444 | .parent = &core_ck, |
446 | .flags = DELAYED_APP, | ||
447 | .clkdm_name = "dsp_clkdm", | 445 | .clkdm_name = "dsp_clkdm", |
448 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 446 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
449 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | 447 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
@@ -470,7 +468,6 @@ static struct clk dsp_irate_ick = { | |||
470 | .name = "dsp_irate_ick", | 468 | .name = "dsp_irate_ick", |
471 | .ops = &clkops_null, | 469 | .ops = &clkops_null, |
472 | .parent = &dsp_fck, | 470 | .parent = &dsp_fck, |
473 | .flags = DELAYED_APP, | ||
474 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | 471 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
475 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, | 472 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, |
476 | .clksel = dsp_irate_ick_clksel, | 473 | .clksel = dsp_irate_ick_clksel, |
@@ -495,7 +492,6 @@ static struct clk iva1_ifck = { | |||
495 | .name = "iva1_ifck", | 492 | .name = "iva1_ifck", |
496 | .ops = &clkops_omap2_dflt_wait, | 493 | .ops = &clkops_omap2_dflt_wait, |
497 | .parent = &core_ck, | 494 | .parent = &core_ck, |
498 | .flags = DELAYED_APP, | ||
499 | .clkdm_name = "iva1_clkdm", | 495 | .clkdm_name = "iva1_clkdm", |
500 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 496 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
501 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, | 497 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, |
@@ -556,7 +552,6 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ | |||
556 | .name = "core_l3_ck", | 552 | .name = "core_l3_ck", |
557 | .ops = &clkops_null, | 553 | .ops = &clkops_null, |
558 | .parent = &core_ck, | 554 | .parent = &core_ck, |
559 | .flags = DELAYED_APP, | ||
560 | .clkdm_name = "core_l3_clkdm", | 555 | .clkdm_name = "core_l3_clkdm", |
561 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 556 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
562 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | 557 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, |
@@ -582,7 +577,6 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */ | |||
582 | .name = "usb_l4_ick", | 577 | .name = "usb_l4_ick", |
583 | .ops = &clkops_omap2_dflt_wait, | 578 | .ops = &clkops_omap2_dflt_wait, |
584 | .parent = &core_l3_ck, | 579 | .parent = &core_l3_ck, |
585 | .flags = DELAYED_APP, | ||
586 | .clkdm_name = "core_l4_clkdm", | 580 | .clkdm_name = "core_l4_clkdm", |
587 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 581 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
588 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | 582 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
@@ -614,14 +608,11 @@ static struct clk l4_ck = { /* used both as an ick and fck */ | |||
614 | .name = "l4_ck", | 608 | .name = "l4_ck", |
615 | .ops = &clkops_null, | 609 | .ops = &clkops_null, |
616 | .parent = &core_l3_ck, | 610 | .parent = &core_l3_ck, |
617 | .flags = DELAYED_APP, | ||
618 | .clkdm_name = "core_l4_clkdm", | 611 | .clkdm_name = "core_l4_clkdm", |
619 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 612 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
620 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | 613 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, |
621 | .clksel = l4_clksel, | 614 | .clksel = l4_clksel, |
622 | .recalc = &omap2_clksel_recalc, | 615 | .recalc = &omap2_clksel_recalc, |
623 | .round_rate = &omap2_clksel_round_rate, | ||
624 | .set_rate = &omap2_clksel_set_rate | ||
625 | }; | 616 | }; |
626 | 617 | ||
627 | /* | 618 | /* |
@@ -651,7 +642,6 @@ static struct clk ssi_ssr_sst_fck = { | |||
651 | .name = "ssi_fck", | 642 | .name = "ssi_fck", |
652 | .ops = &clkops_omap2_dflt_wait, | 643 | .ops = &clkops_omap2_dflt_wait, |
653 | .parent = &core_ck, | 644 | .parent = &core_ck, |
654 | .flags = DELAYED_APP, | ||
655 | .clkdm_name = "core_l3_clkdm", | 645 | .clkdm_name = "core_l3_clkdm", |
656 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 646 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
657 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | 647 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, |
@@ -659,8 +649,6 @@ static struct clk ssi_ssr_sst_fck = { | |||
659 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, | 649 | .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, |
660 | .clksel = ssi_ssr_sst_fck_clksel, | 650 | .clksel = ssi_ssr_sst_fck_clksel, |
661 | .recalc = &omap2_clksel_recalc, | 651 | .recalc = &omap2_clksel_recalc, |
662 | .round_rate = &omap2_clksel_round_rate, | ||
663 | .set_rate = &omap2_clksel_set_rate | ||
664 | }; | 652 | }; |
665 | 653 | ||
666 | /* | 654 | /* |
@@ -715,7 +703,6 @@ static struct clk gfx_2d_fck = { | |||
715 | .name = "gfx_2d_fck", | 703 | .name = "gfx_2d_fck", |
716 | .ops = &clkops_omap2_dflt_wait, | 704 | .ops = &clkops_omap2_dflt_wait, |
717 | .parent = &core_l3_ck, | 705 | .parent = &core_l3_ck, |
718 | .flags = DELAYED_APP, | ||
719 | .clkdm_name = "gfx_clkdm", | 706 | .clkdm_name = "gfx_clkdm", |
720 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 707 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
721 | .enable_bit = OMAP24XX_EN_2D_SHIFT, | 708 | .enable_bit = OMAP24XX_EN_2D_SHIFT, |
@@ -784,7 +771,6 @@ static struct clk dss1_fck = { | |||
784 | .name = "dss1_fck", | 771 | .name = "dss1_fck", |
785 | .ops = &clkops_omap2_dflt, | 772 | .ops = &clkops_omap2_dflt, |
786 | .parent = &core_ck, /* Core or sys */ | 773 | .parent = &core_ck, /* Core or sys */ |
787 | .flags = DELAYED_APP, | ||
788 | .clkdm_name = "dss_clkdm", | 774 | .clkdm_name = "dss_clkdm", |
789 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 775 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
790 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | 776 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
@@ -793,8 +779,6 @@ static struct clk dss1_fck = { | |||
793 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, | 779 | .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, |
794 | .clksel = dss1_fck_clksel, | 780 | .clksel = dss1_fck_clksel, |
795 | .recalc = &omap2_clksel_recalc, | 781 | .recalc = &omap2_clksel_recalc, |
796 | .round_rate = &omap2_clksel_round_rate, | ||
797 | .set_rate = &omap2_clksel_set_rate | ||
798 | }; | 782 | }; |
799 | 783 | ||
800 | static const struct clksel_rate dss2_fck_sys_rates[] = { | 784 | static const struct clksel_rate dss2_fck_sys_rates[] = { |
@@ -817,7 +801,6 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ | |||
817 | .name = "dss2_fck", | 801 | .name = "dss2_fck", |
818 | .ops = &clkops_omap2_dflt, | 802 | .ops = &clkops_omap2_dflt, |
819 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ | 803 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
820 | .flags = DELAYED_APP, | ||
821 | .clkdm_name = "dss_clkdm", | 804 | .clkdm_name = "dss_clkdm", |
822 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 805 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
823 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, | 806 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, |
@@ -1636,7 +1619,6 @@ static struct clk vlynq_fck = { | |||
1636 | .name = "vlynq_fck", | 1619 | .name = "vlynq_fck", |
1637 | .ops = &clkops_omap2_dflt_wait, | 1620 | .ops = &clkops_omap2_dflt_wait, |
1638 | .parent = &func_96m_ck, | 1621 | .parent = &func_96m_ck, |
1639 | .flags = DELAYED_APP, | ||
1640 | .clkdm_name = "core_l3_clkdm", | 1622 | .clkdm_name = "core_l3_clkdm", |
1641 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1623 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1642 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | 1624 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, |
@@ -1645,8 +1627,6 @@ static struct clk vlynq_fck = { | |||
1645 | .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, | 1627 | .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, |
1646 | .clksel = vlynq_fck_clksel, | 1628 | .clksel = vlynq_fck_clksel, |
1647 | .recalc = &omap2_clksel_recalc, | 1629 | .recalc = &omap2_clksel_recalc, |
1648 | .round_rate = &omap2_clksel_round_rate, | ||
1649 | .set_rate = &omap2_clksel_set_rate | ||
1650 | }; | 1630 | }; |
1651 | 1631 | ||
1652 | static struct clk des_ick = { | 1632 | static struct clk des_ick = { |