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-rw-r--r--arch/arm/mach-omap2/clock.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 70f8b073e69f..62cfd6cc7461 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -18,9 +18,6 @@
18 18
19#include <plat/clock.h> 19#include <plat/clock.h>
20 20
21/* The maximum error between a target DPLL rate and the rounded rate in Hz */
22#define DEFAULT_DPLL_RATE_TOLERANCE 50000
23
24/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ 21/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
25#define CORE_CLK_SRC_32K 0x0 22#define CORE_CLK_SRC_32K 0x0
26#define CORE_CLK_SRC_DPLL 0x1 23#define CORE_CLK_SRC_DPLL 0x1
@@ -55,7 +52,6 @@ void omap2_clk_disable(struct clk *clk);
55long omap2_clk_round_rate(struct clk *clk, unsigned long rate); 52long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
56int omap2_clk_set_rate(struct clk *clk, unsigned long rate); 53int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
57int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); 54int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
58int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
59long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); 55long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
60unsigned long omap3_dpll_recalc(struct clk *clk); 56unsigned long omap3_dpll_recalc(struct clk *clk);
61unsigned long omap3_clkoutx2_recalc(struct clk *clk); 57unsigned long omap3_clkoutx2_recalc(struct clk *clk);