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-rw-r--r--arch/arm/mach-omap2/clock.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 626e5fa93b6a..1fb330e0847d 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
21/* The maximum error between a target DPLL rate and the rounded rate in Hz */ 21/* The maximum error between a target DPLL rate and the rounded rate in Hz */
22#define DEFAULT_DPLL_RATE_TOLERANCE 50000 22#define DEFAULT_DPLL_RATE_TOLERANCE 50000
23 23
24int omap2_clk_init(void);
24int omap2_clk_enable(struct clk *clk); 25int omap2_clk_enable(struct clk *clk);
25void omap2_clk_disable(struct clk *clk); 26void omap2_clk_disable(struct clk *clk);
26long omap2_clk_round_rate(struct clk *clk, unsigned long rate); 27long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
@@ -36,6 +37,7 @@ void omap2_clk_disable_unused(struct clk *clk);
36#endif 37#endif
37 38
38void omap2_clksel_recalc(struct clk *clk); 39void omap2_clksel_recalc(struct clk *clk);
40void omap2_init_clk_clkdm(struct clk *clk);
39void omap2_init_clksel_parent(struct clk *clk); 41void omap2_init_clksel_parent(struct clk *clk);
40u32 omap2_clksel_get_divisor(struct clk *clk); 42u32 omap2_clksel_get_divisor(struct clk *clk);
41u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 43u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,