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-rw-r--r--arch/arm/mach-omap2/clock.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index ca6bf226859e..2679ddfa6424 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,21 @@
21/* The maximum error between a target DPLL rate and the rounded rate in Hz */ 21/* The maximum error between a target DPLL rate and the rounded rate in Hz */
22#define DEFAULT_DPLL_RATE_TOLERANCE 50000 22#define DEFAULT_DPLL_RATE_TOLERANCE 50000
23 23
24/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
25#define CORE_CLK_SRC_32K 0x0
26#define CORE_CLK_SRC_DPLL 0x1
27#define CORE_CLK_SRC_DPLL_X2 0x2
28
29/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
30#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
31#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
32#define OMAP2XXX_EN_DPLL_LOCKED 0x3
33
34/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
35#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
36#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
37#define OMAP3XXX_EN_DPLL_LOCKED 0x7
38
24int omap2_clk_init(void); 39int omap2_clk_init(void);
25int omap2_clk_enable(struct clk *clk); 40int omap2_clk_enable(struct clk *clk);
26void omap2_clk_disable(struct clk *clk); 41void omap2_clk_disable(struct clk *clk);