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-rw-r--r--arch/arm/mach-omap2/clock.c1362
1 files changed, 464 insertions, 898 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e6e85b7b097b..b57ffb5a22a5 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -1,20 +1,19 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/clock.c 2 * linux/arch/arm/mach-omap2/clock.c
3 * 3 *
4 * Copyright (C) 2005 Texas Instruments Inc. 4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Richard Woodruff <r-woodruff2@ti.com> 5 * Copyright (C) 2004-2008 Nokia Corporation
6 * Created for OMAP2.
7 *
8 * Cleaned up and modified to use omap shared clock framework by
9 * Tony Lindgren <tony@atomide.com>
10 * 6 *
11 * Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation 7 * Contacts:
12 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
13 * 10 *
14 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
17 */ 14 */
15#undef DEBUG
16
18#include <linux/module.h> 17#include <linux/module.h>
19#include <linux/kernel.h> 18#include <linux/kernel.h>
20#include <linux/device.h> 19#include <linux/device.h>
@@ -22,176 +21,227 @@
22#include <linux/errno.h> 21#include <linux/errno.h>
23#include <linux/delay.h> 22#include <linux/delay.h>
24#include <linux/clk.h> 23#include <linux/clk.h>
24#include <asm/bitops.h>
25 25
26#include <asm/io.h> 26#include <asm/io.h>
27 27
28#include <asm/arch/clock.h> 28#include <asm/arch/clock.h>
29#include <asm/arch/sram.h> 29#include <asm/arch/sram.h>
30#include <asm/arch/cpu.h>
30#include <asm/div64.h> 31#include <asm/div64.h>
31 32
32#include "prcm-regs.h"
33#include "memory.h" 33#include "memory.h"
34#include "sdrc.h"
34#include "clock.h" 35#include "clock.h"
36#include "prm.h"
37#include "prm-regbits-24xx.h"
38#include "cm.h"
39#include "cm-regbits-24xx.h"
40#include "cm-regbits-34xx.h"
35 41
36#undef DEBUG 42#define MAX_CLOCK_ENABLE_WAIT 100000
37
38//#define DOWN_VARIABLE_DPLL 1 /* Experimental */
39 43
40static struct prcm_config *curr_prcm_set; 44u8 cpu_mask;
41static u32 curr_perf_level = PRCM_FULL_SPEED;
42static struct clk *vclk;
43static struct clk *sclk;
44 45
45/*------------------------------------------------------------------------- 46/*-------------------------------------------------------------------------
46 * Omap2 specific clock functions 47 * Omap2 specific clock functions
47 *-------------------------------------------------------------------------*/ 48 *-------------------------------------------------------------------------*/
48 49
49/* Recalculate SYST_CLK */ 50/**
50static void omap2_sys_clk_recalc(struct clk * clk) 51 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
52 * @clk: OMAP clock struct ptr to use
53 *
54 * Given a pointer to a source-selectable struct clk, read the hardware
55 * register and determine what its parent is currently set to. Update the
56 * clk->parent field with the appropriate clk ptr.
57 */
58void omap2_init_clksel_parent(struct clk *clk)
51{ 59{
52 u32 div = PRCM_CLKSRC_CTRL; 60 const struct clksel *clks;
53 div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ 61 const struct clksel_rate *clkr;
54 div >>= clk->rate_offset; 62 u32 r, found = 0;
55 clk->rate = (clk->parent->rate / div); 63
56 propagate_rate(clk); 64 if (!clk->clksel)
65 return;
66
67 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
68 r >>= __ffs(clk->clksel_mask);
69
70 for (clks = clk->clksel; clks->parent && !found; clks++) {
71 for (clkr = clks->rates; clkr->div && !found; clkr++) {
72 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
73 if (clk->parent != clks->parent) {
74 pr_debug("clock: inited %s parent "
75 "to %s (was %s)\n",
76 clk->name, clks->parent->name,
77 ((clk->parent) ?
78 clk->parent->name : "NULL"));
79 clk->parent = clks->parent;
80 };
81 found = 1;
82 }
83 }
84 }
85
86 if (!found)
87 printk(KERN_ERR "clock: init parent: could not find "
88 "regval %0x for clock %s\n", r, clk->name);
89
90 return;
57} 91}
58 92
59static u32 omap2_get_dpll_rate(struct clk * tclk) 93/* Returns the DPLL rate */
94u32 omap2_get_dpll_rate(struct clk *clk)
60{ 95{
61 long long dpll_clk; 96 long long dpll_clk;
62 int dpll_mult, dpll_div, amult; 97 u32 dpll_mult, dpll_div, dpll;
98 const struct dpll_data *dd;
99
100 dd = clk->dpll_data;
101 /* REVISIT: What do we return on error? */
102 if (!dd)
103 return 0;
104
105 dpll = __raw_readl(dd->mult_div1_reg);
106 dpll_mult = dpll & dd->mult_mask;
107 dpll_mult >>= __ffs(dd->mult_mask);
108 dpll_div = dpll & dd->div1_mask;
109 dpll_div >>= __ffs(dd->div1_mask);
63 110
64 dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */ 111 dpll_clk = (long long)clk->parent->rate * dpll_mult;
65 dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */
66 dpll_clk = (long long)tclk->parent->rate * dpll_mult;
67 do_div(dpll_clk, dpll_div + 1); 112 do_div(dpll_clk, dpll_div + 1);
68 amult = CM_CLKSEL2_PLL & 0x3;
69 dpll_clk *= amult;
70 113
71 return dpll_clk; 114 return dpll_clk;
72} 115}
73 116
74static void omap2_followparent_recalc(struct clk *clk) 117/*
75{ 118 * Used for clocks that have the same value as the parent clock,
76 followparent_recalc(clk); 119 * divided by some factor
77} 120 */
78 121void omap2_fixed_divisor_recalc(struct clk *clk)
79static void omap2_propagate_rate(struct clk * clk)
80{ 122{
81 if (!(clk->flags & RATE_FIXED)) 123 WARN_ON(!clk->fixed_div);
82 clk->rate = clk->parent->rate;
83 124
84 propagate_rate(clk); 125 clk->rate = clk->parent->rate / clk->fixed_div;
85}
86 126
87static void omap2_set_osc_ck(int enable) 127 if (clk->flags & RATE_PROPAGATES)
88{ 128 propagate_rate(clk);
89 if (enable)
90 PRCM_CLKSRC_CTRL &= ~(0x3 << 3);
91 else
92 PRCM_CLKSRC_CTRL |= 0x3 << 3;
93} 129}
94 130
95/* Enable an APLL if off */ 131/**
96static void omap2_clk_fixed_enable(struct clk *clk) 132 * omap2_wait_clock_ready - wait for clock to enable
133 * @reg: physical address of clock IDLEST register
134 * @mask: value to mask against to determine if the clock is active
135 * @name: name of the clock (for printk)
136 *
137 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
138 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
139 */
140int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
97{ 141{
98 u32 cval, i=0; 142 int i = 0;
143 int ena = 0;
99 144
100 if (clk->enable_bit == 0xff) /* Parent will do it */ 145 /*
101 return; 146 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
147 * 34xx reverses this, just to keep us on our toes
148 */
149 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
150 ena = mask;
151 } else if (cpu_mask & RATE_IN_343X) {
152 ena = 0;
153 }
102 154
103 cval = CM_CLKEN_PLL; 155 /* Wait for lock */
156 while (((__raw_readl(reg) & mask) != ena) &&
157 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
158 udelay(1);
159 }
104 160
105 if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit)) 161 if (i < MAX_CLOCK_ENABLE_WAIT)
106 return; 162 pr_debug("Clock %s stable after %d loops\n", name, i);
163 else
164 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
165 name, MAX_CLOCK_ENABLE_WAIT);
107 166
108 cval &= ~(0x3 << clk->enable_bit);
109 cval |= (0x3 << clk->enable_bit);
110 CM_CLKEN_PLL = cval;
111 167
112 if (clk == &apll96_ck) 168 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
113 cval = (1 << 8); 169};
114 else if (clk == &apll54_ck)
115 cval = (1 << 6);
116 170
117 while (!(CM_IDLEST_CKGEN & cval)) { /* Wait for lock */
118 ++i;
119 udelay(1);
120 if (i == 100000) {
121 printk(KERN_ERR "Clock %s didn't lock\n", clk->name);
122 break;
123 }
124 }
125}
126 171
172/*
173 * Note: We don't need special code here for INVERT_ENABLE
174 * for the time being since INVERT_ENABLE only applies to clocks enabled by
175 * CM_CLKEN_PLL
176 */
127static void omap2_clk_wait_ready(struct clk *clk) 177static void omap2_clk_wait_ready(struct clk *clk)
128{ 178{
129 unsigned long reg, other_reg, st_reg; 179 void __iomem *reg, *other_reg, *st_reg;
130 u32 bit; 180 u32 bit;
131 int i; 181
132 182 /*
133 reg = (unsigned long) clk->enable_reg; 183 * REVISIT: This code is pretty ugly. It would be nice to generalize
134 if (reg == (unsigned long) &CM_FCLKEN1_CORE || 184 * it and pull it into struct clk itself somehow.
135 reg == (unsigned long) &CM_FCLKEN2_CORE) 185 */
136 other_reg = (reg & ~0xf0) | 0x10; 186 reg = clk->enable_reg;
137 else if (reg == (unsigned long) &CM_ICLKEN1_CORE || 187 if ((((u32)reg & 0xff) >= CM_FCLKEN1) &&
138 reg == (unsigned long) &CM_ICLKEN2_CORE) 188 (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
139 other_reg = (reg & ~0xf0) | 0x00; 189 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
190 else if ((((u32)reg & 0xff) >= CM_ICLKEN1) &&
191 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
192 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
140 else 193 else
141 return; 194 return;
142 195
196 /* REVISIT: What are the appropriate exclusions for 34XX? */
143 /* No check for DSS or cam clocks */ 197 /* No check for DSS or cam clocks */
144 if ((reg & 0x0f) == 0) { 198 if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
145 if (clk->enable_bit <= 1 || clk->enable_bit == 31) 199 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
200 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
201 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
146 return; 202 return;
147 } 203 }
148 204
205 /* REVISIT: What are the appropriate exclusions for 34XX? */
206 /* OMAP3: ignore DSS-mod clocks */
207 if (cpu_is_omap34xx() &&
208 (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0)))
209 return;
210
149 /* Check if both functional and interface clocks 211 /* Check if both functional and interface clocks
150 * are running. */ 212 * are running. */
151 bit = 1 << clk->enable_bit; 213 bit = 1 << clk->enable_bit;
152 if (!(__raw_readl(other_reg) & bit)) 214 if (!(__raw_readl(other_reg) & bit))
153 return; 215 return;
154 st_reg = (other_reg & ~0xf0) | 0x20; 216 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
155 i = 0; 217
156 while (!(__raw_readl(st_reg) & bit)) { 218 omap2_wait_clock_ready(st_reg, bit, clk->name);
157 i++;
158 if (i == 100000) {
159 printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
160 break;
161 }
162 }
163 if (i)
164 pr_debug("Clock %s stable after %d loops\n", clk->name, i);
165} 219}
166 220
167/* Enables clock without considering parent dependencies or use count 221/* Enables clock without considering parent dependencies or use count
168 * REVISIT: Maybe change this to use clk->enable like on omap1? 222 * REVISIT: Maybe change this to use clk->enable like on omap1?
169 */ 223 */
170static int _omap2_clk_enable(struct clk * clk) 224int _omap2_clk_enable(struct clk *clk)
171{ 225{
172 u32 regval32; 226 u32 regval32;
173 227
174 if (clk->flags & ALWAYS_ENABLED) 228 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
175 return 0; 229 return 0;
176 230
177 if (unlikely(clk == &osc_ck)) { 231 if (clk->enable)
178 omap2_set_osc_ck(1); 232 return clk->enable(clk);
179 return 0;
180 }
181 233
182 if (unlikely(clk->enable_reg == 0)) { 234 if (unlikely(clk->enable_reg == 0)) {
183 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 235 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
184 clk->name); 236 clk->name);
185 return 0; 237 return 0; /* REVISIT: -EINVAL */
186 }
187
188 if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
189 omap2_clk_fixed_enable(clk);
190 return 0;
191 } 238 }
192 239
193 regval32 = __raw_readl(clk->enable_reg); 240 regval32 = __raw_readl(clk->enable_reg);
194 regval32 |= (1 << clk->enable_bit); 241 if (clk->flags & INVERT_ENABLE)
242 regval32 &= ~(1 << clk->enable_bit);
243 else
244 regval32 |= (1 << clk->enable_bit);
195 __raw_writel(regval32, clk->enable_reg); 245 __raw_writel(regval32, clk->enable_reg);
196 wmb(); 246 wmb();
197 247
@@ -200,44 +250,48 @@ static int _omap2_clk_enable(struct clk * clk)
200 return 0; 250 return 0;
201} 251}
202 252
203/* Stop APLL */
204static void omap2_clk_fixed_disable(struct clk *clk)
205{
206 u32 cval;
207
208 if(clk->enable_bit == 0xff) /* let parent off do it */
209 return;
210
211 cval = CM_CLKEN_PLL;
212 cval &= ~(0x3 << clk->enable_bit);
213 CM_CLKEN_PLL = cval;
214}
215
216/* Disables clock without considering parent dependencies or use count */ 253/* Disables clock without considering parent dependencies or use count */
217static void _omap2_clk_disable(struct clk *clk) 254void _omap2_clk_disable(struct clk *clk)
218{ 255{
219 u32 regval32; 256 u32 regval32;
220 257
221 if (unlikely(clk == &osc_ck)) { 258 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
222 omap2_set_osc_ck(0);
223 return; 259 return;
224 }
225 260
226 if (clk->enable_reg == 0) 261 if (clk->disable) {
262 clk->disable(clk);
227 return; 263 return;
264 }
228 265
229 if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) { 266 if (clk->enable_reg == 0) {
230 omap2_clk_fixed_disable(clk); 267 /*
268 * 'Independent' here refers to a clock which is not
269 * controlled by its parent.
270 */
271 printk(KERN_ERR "clock: clk_disable called on independent "
272 "clock %s which has no enable_reg\n", clk->name);
231 return; 273 return;
232 } 274 }
233 275
234 regval32 = __raw_readl(clk->enable_reg); 276 regval32 = __raw_readl(clk->enable_reg);
235 regval32 &= ~(1 << clk->enable_bit); 277 if (clk->flags & INVERT_ENABLE)
278 regval32 |= (1 << clk->enable_bit);
279 else
280 regval32 &= ~(1 << clk->enable_bit);
236 __raw_writel(regval32, clk->enable_reg); 281 __raw_writel(regval32, clk->enable_reg);
237 wmb(); 282 wmb();
238} 283}
239 284
240static int omap2_clk_enable(struct clk *clk) 285void omap2_clk_disable(struct clk *clk)
286{
287 if (clk->usecount > 0 && !(--clk->usecount)) {
288 _omap2_clk_disable(clk);
289 if (likely((u32)clk->parent))
290 omap2_clk_disable(clk->parent);
291 }
292}
293
294int omap2_clk_enable(struct clk *clk)
241{ 295{
242 int ret = 0; 296 int ret = 0;
243 297
@@ -261,519 +315,314 @@ static int omap2_clk_enable(struct clk *clk)
261 return ret; 315 return ret;
262} 316}
263 317
264static void omap2_clk_disable(struct clk *clk)
265{
266 if (clk->usecount > 0 && !(--clk->usecount)) {
267 _omap2_clk_disable(clk);
268 if (likely((u32)clk->parent))
269 omap2_clk_disable(clk->parent);
270 }
271}
272
273/*
274 * Uses the current prcm set to tell if a rate is valid.
275 * You can go slower, but not faster within a given rate set.
276 */
277static u32 omap2_dpll_round_rate(unsigned long target_rate)
278{
279 u32 high, low;
280
281 if ((CM_CLKSEL2_PLL & 0x3) == 1) { /* DPLL clockout */
282 high = curr_prcm_set->dpll_speed * 2;
283 low = curr_prcm_set->dpll_speed;
284 } else { /* DPLL clockout x 2 */
285 high = curr_prcm_set->dpll_speed;
286 low = curr_prcm_set->dpll_speed / 2;
287 }
288
289#ifdef DOWN_VARIABLE_DPLL
290 if (target_rate > high)
291 return high;
292 else
293 return target_rate;
294#else
295 if (target_rate > low)
296 return high;
297 else
298 return low;
299#endif
300
301}
302
303/* 318/*
304 * Used for clocks that are part of CLKSEL_xyz governed clocks. 319 * Used for clocks that are part of CLKSEL_xyz governed clocks.
305 * REVISIT: Maybe change to use clk->enable() functions like on omap1? 320 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
306 */ 321 */
307static void omap2_clksel_recalc(struct clk * clk) 322void omap2_clksel_recalc(struct clk *clk)
308{ 323{
309 u32 fixed = 0, div = 0; 324 u32 div = 0;
310 325
311 if (clk == &dpll_ck) { 326 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
312 clk->rate = omap2_get_dpll_rate(clk);
313 fixed = 1;
314 div = 0;
315 }
316 327
317 if (clk == &iva1_mpu_int_ifck) { 328 div = omap2_clksel_get_divisor(clk);
318 div = 2; 329 if (div == 0)
319 fixed = 1;
320 }
321
322 if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) {
323 clk->rate = sys_ck.rate;
324 return; 330 return;
325 }
326 331
327 if (!fixed) { 332 if (unlikely(clk->rate == clk->parent->rate / div))
328 div = omap2_clksel_get_divisor(clk); 333 return;
329 if (div == 0) 334 clk->rate = clk->parent->rate / div;
330 return;
331 }
332 335
333 if (div != 0) { 336 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
334 if (unlikely(clk->rate == clk->parent->rate / div))
335 return;
336 clk->rate = clk->parent->rate / div;
337 }
338 337
339 if (unlikely(clk->flags & RATE_PROPAGATES)) 338 if (unlikely(clk->flags & RATE_PROPAGATES))
340 propagate_rate(clk); 339 propagate_rate(clk);
341} 340}
342 341
343/* 342/**
344 * Finds best divider value in an array based on the source and target 343 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
345 * rates. The divider array must be sorted with smallest divider first. 344 * @clk: OMAP struct clk ptr to inspect
345 * @src_clk: OMAP struct clk ptr of the parent clk to search for
346 *
347 * Scan the struct clksel array associated with the clock to find
348 * the element associated with the supplied parent clock address.
349 * Returns a pointer to the struct clksel on success or NULL on error.
346 */ 350 */
347static inline u32 omap2_divider_from_table(u32 size, u32 *div_array, 351const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
348 u32 src_rate, u32 tgt_rate) 352 struct clk *src_clk)
349{ 353{
350 int i, test_rate; 354 const struct clksel *clks;
351 355
352 if (div_array == NULL) 356 if (!clk->clksel)
353 return ~1; 357 return NULL;
354 358
355 for (i=0; i < size; i++) { 359 for (clks = clk->clksel; clks->parent; clks++) {
356 test_rate = src_rate / *div_array; 360 if (clks->parent == src_clk)
357 if (test_rate <= tgt_rate) 361 break; /* Found the requested parent */
358 return *div_array;
359 ++div_array;
360 } 362 }
361 363
362 return ~0; /* No acceptable divider */ 364 if (!clks->parent) {
365 printk(KERN_ERR "clock: Could not find parent clock %s in "
366 "clksel array of clock %s\n", src_clk->name,
367 clk->name);
368 return NULL;
369 }
370
371 return clks;
363} 372}
364 373
365/* 374/**
366 * Find divisor for the given clock and target rate. 375 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
376 * @clk: OMAP struct clk to use
377 * @target_rate: desired clock rate
378 * @new_div: ptr to where we should store the divisor
367 * 379 *
380 * Finds 'best' divider value in an array based on the source and target
381 * rates. The divider array must be sorted with smallest divider first.
368 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 382 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
369 * they are only settable as part of virtual_prcm set. 383 * they are only settable as part of virtual_prcm set.
384 *
385 * Returns the rounded clock rate or returns 0xffffffff on error.
370 */ 386 */
371static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate, 387u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
372 u32 *new_div) 388 u32 *new_div)
373{ 389{
374 u32 gfx_div[] = {2, 3, 4}; 390 unsigned long test_rate;
375 u32 sysclkout_div[] = {1, 2, 4, 8, 16}; 391 const struct clksel *clks;
376 u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16}; 392 const struct clksel_rate *clkr;
377 u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18}; 393 u32 last_div = 0;
378 u32 best_div = ~0, asize = 0; 394
379 u32 *div_array = NULL; 395 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
380 396 clk->name, target_rate);
381 switch (tclk->flags & SRC_RATE_SEL_MASK) { 397
382 case CM_GFX_SEL1: 398 *new_div = 1;
383 asize = 3; 399
384 div_array = gfx_div; 400 clks = omap2_get_clksel_by_parent(clk, clk->parent);
385 break; 401 if (clks == NULL)
386 case CM_PLL_SEL1: 402 return ~0;
387 return omap2_dpll_round_rate(target_rate); 403
388 case CM_SYSCLKOUT_SEL1: 404 for (clkr = clks->rates; clkr->div; clkr++) {
389 asize = 5; 405 if (!(clkr->flags & cpu_mask))
390 div_array = sysclkout_div; 406 continue;
391 break; 407
392 case CM_CORE_SEL1: 408 /* Sanity check */
393 if(tclk == &dss1_fck){ 409 if (clkr->div <= last_div)
394 if(tclk->parent == &core_ck){ 410 printk(KERN_ERR "clock: clksel_rate table not sorted "
395 asize = 10; 411 "for clock %s", clk->name);
396 div_array = dss1_div; 412
397 } else { 413 last_div = clkr->div;
398 *new_div = 0; /* fixed clk */ 414
399 return(tclk->parent->rate); 415 test_rate = clk->parent->rate / clkr->div;
400 } 416
401 } else if((tclk == &vlynq_fck) && cpu_is_omap2420()){ 417 if (test_rate <= target_rate)
402 if(tclk->parent == &core_ck){ 418 break; /* found it */
403 asize = 10;
404 div_array = vylnq_div;
405 } else {
406 *new_div = 0; /* fixed clk */
407 return(tclk->parent->rate);
408 }
409 }
410 break;
411 } 419 }
412 420
413 best_div = omap2_divider_from_table(asize, div_array, 421 if (!clkr->div) {
414 tclk->parent->rate, target_rate); 422 printk(KERN_ERR "clock: Could not find divisor for target "
415 if (best_div == ~0){ 423 "rate %ld for clock %s parent %s\n", target_rate,
416 *new_div = 1; 424 clk->name, clk->parent->name);
417 return best_div; /* signal error */ 425 return ~0;
418 } 426 }
419 427
420 *new_div = best_div; 428 *new_div = clkr->div;
421 return (tclk->parent->rate / best_div); 429
430 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
431 (clk->parent->rate / clkr->div));
432
433 return (clk->parent->rate / clkr->div);
422} 434}
423 435
424/* Given a clock and a rate apply a clock specific rounding function */ 436/**
425static long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 437 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
438 * @clk: OMAP struct clk to use
439 * @target_rate: desired clock rate
440 *
441 * Compatibility wrapper for OMAP clock framework
442 * Finds best target rate based on the source clock and possible dividers.
443 * rates. The divider array must be sorted with smallest divider first.
444 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
445 * they are only settable as part of virtual_prcm set.
446 *
447 * Returns the rounded clock rate or returns 0xffffffff on error.
448 */
449long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
426{ 450{
427 u32 new_div = 0; 451 u32 new_div;
428 int valid_rate;
429 452
430 if (clk->flags & RATE_FIXED) 453 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
431 return clk->rate; 454}
432 455
433 if (clk->flags & RATE_CKCTL) {
434 valid_rate = omap2_clksel_round_rate(clk, rate, &new_div);
435 return valid_rate;
436 }
437 456
457/* Given a clock and a rate apply a clock specific rounding function */
458long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
459{
438 if (clk->round_rate != 0) 460 if (clk->round_rate != 0)
439 return clk->round_rate(clk, rate); 461 return clk->round_rate(clk, rate);
440 462
463 if (clk->flags & RATE_FIXED)
464 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
465 "on fixed-rate clock %s\n", clk->name);
466
441 return clk->rate; 467 return clk->rate;
442} 468}
443 469
444/* 470/**
445 * Check the DLL lock state, and return tue if running in unlock mode. 471 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
446 * This is needed to compensate for the shifted DLL value in unlock mode. 472 * @clk: OMAP struct clk to use
473 * @field_val: register field value to find
474 *
475 * Given a struct clk of a rate-selectable clksel clock, and a register field
476 * value to search for, find the corresponding clock divisor. The register
477 * field value should be pre-masked and shifted down so the LSB is at bit 0
478 * before calling. Returns 0 on error
447 */ 479 */
448static u32 omap2_dll_force_needed(void) 480u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
449{ 481{
450 u32 dll_state = SDRC_DLLA_CTRL; /* dlla and dllb are a set */ 482 const struct clksel *clks;
483 const struct clksel_rate *clkr;
451 484
452 if ((dll_state & (1 << 2)) == (1 << 2)) 485 clks = omap2_get_clksel_by_parent(clk, clk->parent);
453 return 1; 486 if (clks == NULL)
454 else
455 return 0; 487 return 0;
456}
457 488
458static u32 omap2_reprogram_sdrc(u32 level, u32 force) 489 for (clkr = clks->rates; clkr->div; clkr++) {
459{ 490 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
460 u32 slow_dll_ctrl, fast_dll_ctrl, m_type; 491 break;
461 u32 prev = curr_perf_level, flags;
462
463 if ((curr_perf_level == level) && !force)
464 return prev;
465
466 m_type = omap2_memory_get_type();
467 slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
468 fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
469
470 if (level == PRCM_HALF_SPEED) {
471 local_irq_save(flags);
472 PRCM_VOLTSETUP = 0xffff;
473 omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
474 slow_dll_ctrl, m_type);
475 curr_perf_level = PRCM_HALF_SPEED;
476 local_irq_restore(flags);
477 } 492 }
478 if (level == PRCM_FULL_SPEED) { 493
479 local_irq_save(flags); 494 if (!clkr->div) {
480 PRCM_VOLTSETUP = 0xffff; 495 printk(KERN_ERR "clock: Could not find fieldval %d for "
481 omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED, 496 "clock %s parent %s\n", field_val, clk->name,
482 fast_dll_ctrl, m_type); 497 clk->parent->name);
483 curr_perf_level = PRCM_FULL_SPEED; 498 return 0;
484 local_irq_restore(flags);
485 } 499 }
486 500
487 return prev; 501 return clkr->div;
488} 502}
489 503
490static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate) 504/**
505 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
506 * @clk: OMAP struct clk to use
507 * @div: integer divisor to search for
508 *
509 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
510 * find the corresponding register field value. The return register value is
511 * the value before left-shifting. Returns 0xffffffff on error
512 */
513u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
491{ 514{
492 u32 flags, cur_rate, low, mult, div, valid_rate, done_rate; 515 const struct clksel *clks;
493 u32 bypass = 0; 516 const struct clksel_rate *clkr;
494 struct prcm_config tmpset;
495 int ret = -EINVAL;
496 517
497 local_irq_save(flags); 518 /* should never happen */
498 cur_rate = omap2_get_dpll_rate(&dpll_ck); 519 WARN_ON(div == 0);
499 mult = CM_CLKSEL2_PLL & 0x3;
500
501 if ((rate == (cur_rate / 2)) && (mult == 2)) {
502 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
503 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
504 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
505 } else if (rate != cur_rate) {
506 valid_rate = omap2_dpll_round_rate(rate);
507 if (valid_rate != rate)
508 goto dpll_exit;
509
510 if ((CM_CLKSEL2_PLL & 0x3) == 1)
511 low = curr_prcm_set->dpll_speed;
512 else
513 low = curr_prcm_set->dpll_speed / 2;
514
515 tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL;
516 tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
517 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
518 tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL;
519 tmpset.cm_clksel2_pll &= ~0x3;
520 if (rate > low) {
521 tmpset.cm_clksel2_pll |= 0x2;
522 mult = ((rate / 2) / 1000000);
523 done_rate = PRCM_FULL_SPEED;
524 } else {
525 tmpset.cm_clksel2_pll |= 0x1;
526 mult = (rate / 1000000);
527 done_rate = PRCM_HALF_SPEED;
528 }
529 tmpset.cm_clksel1_pll |= ((div << 8) | (mult << 12));
530
531 /* Worst case */
532 tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS;
533
534 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
535 bypass = 1;
536 520
537 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */ 521 clks = omap2_get_clksel_by_parent(clk, clk->parent);
538 522 if (clks == NULL)
539 /* Force dll lock mode */ 523 return 0;
540 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
541 bypass);
542 524
543 /* Errata: ret dll entry state */ 525 for (clkr = clks->rates; clkr->div; clkr++) {
544 omap2_init_memory_params(omap2_dll_force_needed()); 526 if ((clkr->flags & cpu_mask) && (clkr->div == div))
545 omap2_reprogram_sdrc(done_rate, 0); 527 break;
546 } 528 }
547 omap2_clksel_recalc(&dpll_ck);
548 ret = 0;
549 529
550dpll_exit: 530 if (!clkr->div) {
551 local_irq_restore(flags); 531 printk(KERN_ERR "clock: Could not find divisor %d for "
552 return(ret); 532 "clock %s parent %s\n", div, clk->name,
553} 533 clk->parent->name);
534 return 0;
535 }
554 536
555/* Just return the MPU speed */ 537 return clkr->val;
556static void omap2_mpu_recalc(struct clk * clk)
557{
558 clk->rate = curr_prcm_set->mpu_speed;
559} 538}
560 539
561/* 540/**
562 * Look for a rate equal or less than the target rate given a configuration set. 541 * omap2_get_clksel - find clksel register addr & field mask for a clk
542 * @clk: struct clk to use
543 * @field_mask: ptr to u32 to store the register field mask
563 * 544 *
564 * What's not entirely clear is "which" field represents the key field. 545 * Returns the address of the clksel register upon success or NULL on error.
565 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
566 * just uses the ARM rates.
567 */ 546 */
568static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate) 547void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
569{ 548{
570 struct prcm_config * ptr; 549 if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0)))
571 long highest_rate; 550 return NULL;
572
573 if (clk != &virt_prcm_set)
574 return -EINVAL;
575
576 highest_rate = -EINVAL;
577
578 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
579 if (ptr->xtal_speed != sys_ck.rate)
580 continue;
581 551
582 highest_rate = ptr->mpu_speed; 552 *field_mask = clk->clksel_mask;
583 553
584 /* Can check only after xtal frequency check */ 554 return clk->clksel_reg;
585 if (ptr->mpu_speed <= rate)
586 break;
587 }
588 return highest_rate;
589} 555}
590 556
591/* 557/**
592 * omap2_convert_field_to_div() - turn field value into integer divider 558 * omap2_clksel_get_divisor - get current divider applied to parent clock.
559 * @clk: OMAP struct clk to use.
560 *
561 * Returns the integer divisor upon success or 0 on error.
593 */ 562 */
594static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val) 563u32 omap2_clksel_get_divisor(struct clk *clk)
595{ 564{
596 u32 i; 565 u32 field_mask, field_val;
597 u32 clkout_array[] = {1, 2, 4, 8, 16}; 566 void __iomem *div_addr;
598 567
599 if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) { 568 div_addr = omap2_get_clksel(clk, &field_mask);
600 for (i = 0; i < 5; i++) { 569 if (div_addr == 0)
601 if (field_val == i) 570 return 0;
602 return clkout_array[i]; 571
603 } 572 field_val = __raw_readl(div_addr) & field_mask;
604 return ~0; 573 field_val >>= __ffs(field_mask);
605 } else 574
606 return field_val; 575 return omap2_clksel_to_divisor(clk, field_val);
607} 576}
608 577
609/* 578int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
610 * Returns the CLKSEL divider register value
611 * REVISIT: This should be cleaned up to work nicely with void __iomem *
612 */
613static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
614 struct clk *clk)
615{ 579{
616 int ret = ~0; 580 u32 field_mask, field_val, reg_val, validrate, new_div = 0;
617 u32 reg_val, div_off; 581 void __iomem *div_addr;
618 u32 div_addr = 0;
619 u32 mask = ~0;
620
621 div_off = clk->rate_offset;
622
623 switch ((*div_sel & SRC_RATE_SEL_MASK)) {
624 case CM_MPU_SEL1:
625 div_addr = (u32)&CM_CLKSEL_MPU;
626 mask = 0x1f;
627 break;
628 case CM_DSP_SEL1:
629 div_addr = (u32)&CM_CLKSEL_DSP;
630 if (cpu_is_omap2420()) {
631 if ((div_off == 0) || (div_off == 8))
632 mask = 0x1f;
633 else if (div_off == 5)
634 mask = 0x3;
635 } else if (cpu_is_omap2430()) {
636 if (div_off == 0)
637 mask = 0x1f;
638 else if (div_off == 5)
639 mask = 0x3;
640 }
641 break;
642 case CM_GFX_SEL1:
643 div_addr = (u32)&CM_CLKSEL_GFX;
644 if (div_off == 0)
645 mask = 0x7;
646 break;
647 case CM_MODEM_SEL1:
648 div_addr = (u32)&CM_CLKSEL_MDM;
649 if (div_off == 0)
650 mask = 0xf;
651 break;
652 case CM_SYSCLKOUT_SEL1:
653 div_addr = (u32)&PRCM_CLKOUT_CTRL;
654 if ((div_off == 3) || (div_off == 11))
655 mask= 0x3;
656 break;
657 case CM_CORE_SEL1:
658 div_addr = (u32)&CM_CLKSEL1_CORE;
659 switch (div_off) {
660 case 0: /* l3 */
661 case 8: /* dss1 */
662 case 15: /* vylnc-2420 */
663 case 20: /* ssi */
664 mask = 0x1f; break;
665 case 5: /* l4 */
666 mask = 0x3; break;
667 case 13: /* dss2 */
668 mask = 0x1; break;
669 case 25: /* usb */
670 mask = 0x7; break;
671 }
672 }
673 582
674 *field_mask = mask; 583 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
584 if (validrate != rate)
585 return -EINVAL;
675 586
676 if (unlikely(mask == ~0)) 587 div_addr = omap2_get_clksel(clk, &field_mask);
677 div_addr = 0; 588 if (div_addr == 0)
589 return -EINVAL;
678 590
679 *div_sel = div_addr; 591 field_val = omap2_divisor_to_clksel(clk, new_div);
592 if (field_val == ~0)
593 return -EINVAL;
680 594
681 if (unlikely(div_addr == 0)) 595 reg_val = __raw_readl(div_addr);
682 return ret; 596 reg_val &= ~field_mask;
597 reg_val |= (field_val << __ffs(field_mask));
598 __raw_writel(reg_val, div_addr);
599 wmb();
683 600
684 /* Isolate field */ 601 clk->rate = clk->parent->rate / new_div;
685 reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off);
686 602
687 /* Normalize back to divider value */ 603 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
688 reg_val >>= div_off; 604 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
605 wmb();
606 }
689 607
690 return reg_val; 608 return 0;
691} 609}
692 610
693/*
694 * Return divider to be applied to parent clock.
695 * Return 0 on error.
696 */
697static u32 omap2_clksel_get_divisor(struct clk *clk)
698{
699 int ret = 0;
700 u32 div, div_sel, div_off, field_mask, field_val;
701
702 /* isolate control register */
703 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
704
705 div_off = clk->rate_offset;
706 field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
707 if (div_sel == 0)
708 return ret;
709
710 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
711 div = omap2_clksel_to_divisor(div_sel, field_val);
712
713 return div;
714}
715 611
716/* Set the clock rate for a clock source */ 612/* Set the clock rate for a clock source */
717static int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 613int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
718
719{ 614{
720 int ret = -EINVAL; 615 int ret = -EINVAL;
721 void __iomem * reg;
722 u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
723 u32 new_div = 0;
724
725 if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
726 if (clk == &dpll_ck)
727 return omap2_reprogram_dpll(clk, rate);
728
729 /* Isolate control register */
730 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
731 div_off = clk->rate_offset;
732
733 validrate = omap2_clksel_round_rate(clk, rate, &new_div);
734 if (validrate != rate)
735 return(ret);
736 616
737 field_val = omap2_get_clksel(&div_sel, &field_mask, clk); 617 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
738 if (div_sel == 0)
739 return ret;
740
741 if (clk->flags & CM_SYSCLKOUT_SEL1) {
742 switch (new_div) {
743 case 16:
744 field_val = 4;
745 break;
746 case 8:
747 field_val = 3;
748 break;
749 case 4:
750 field_val = 2;
751 break;
752 case 2:
753 field_val = 1;
754 break;
755 case 1:
756 field_val = 0;
757 break;
758 }
759 } else
760 field_val = new_div;
761 618
762 reg = (void __iomem *)div_sel; 619 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
763 620 rate table mechanism, driven by mpu_speed */
764 reg_val = __raw_readl(reg); 621 if (clk->flags & CONFIG_PARTICIPANT)
765 reg_val &= ~(field_mask << div_off); 622 return -EINVAL;
766 reg_val |= (field_val << div_off);
767 __raw_writel(reg_val, reg);
768 wmb();
769 clk->rate = clk->parent->rate / field_val;
770 623
771 if (clk->flags & DELAYED_APP) { 624 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
772 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); 625 if (clk->set_rate != 0)
773 wmb();
774 }
775 ret = 0;
776 } else if (clk->set_rate != 0)
777 ret = clk->set_rate(clk, rate); 626 ret = clk->set_rate(clk, rate);
778 627
779 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) 628 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
@@ -782,242 +631,92 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
782 return ret; 631 return ret;
783} 632}
784 633
785/* Converts encoded control register address into a full address */ 634/*
786static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset, 635 * Converts encoded control register address into a full address
787 struct clk *src_clk, u32 *field_mask) 636 * On error, *src_addr will be returned as 0.
788{ 637 */
789 u32 val = ~0, src_reg_addr = 0, mask = 0; 638static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
790 639 struct clk *src_clk, u32 *field_mask,
791 /* Find target control register.*/ 640 struct clk *clk, u32 *parent_div)
792 switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
793 case CM_CORE_SEL1:
794 src_reg_addr = (u32)&CM_CLKSEL1_CORE;
795 if (reg_offset == 13) { /* DSS2_fclk */
796 mask = 0x1;
797 if (src_clk == &sys_ck)
798 val = 0;
799 if (src_clk == &func_48m_ck)
800 val = 1;
801 } else if (reg_offset == 8) { /* DSS1_fclk */
802 mask = 0x1f;
803 if (src_clk == &sys_ck)
804 val = 0;
805 else if (src_clk == &core_ck) /* divided clock */
806 val = 0x10; /* rate needs fixing */
807 } else if ((reg_offset == 15) && cpu_is_omap2420()){ /*vlnyq*/
808 mask = 0x1F;
809 if(src_clk == &func_96m_ck)
810 val = 0;
811 else if (src_clk == &core_ck)
812 val = 0x10;
813 }
814 break;
815 case CM_CORE_SEL2:
816 src_reg_addr = (u32)&CM_CLKSEL2_CORE;
817 mask = 0x3;
818 if (src_clk == &func_32k_ck)
819 val = 0x0;
820 if (src_clk == &sys_ck)
821 val = 0x1;
822 if (src_clk == &alt_ck)
823 val = 0x2;
824 break;
825 case CM_WKUP_SEL1:
826 src_reg_addr = (u32)&CM_CLKSEL_WKUP;
827 mask = 0x3;
828 if (src_clk == &func_32k_ck)
829 val = 0x0;
830 if (src_clk == &sys_ck)
831 val = 0x1;
832 if (src_clk == &alt_ck)
833 val = 0x2;
834 break;
835 case CM_PLL_SEL1:
836 src_reg_addr = (u32)&CM_CLKSEL1_PLL;
837 mask = 0x1;
838 if (reg_offset == 0x3) {
839 if (src_clk == &apll96_ck)
840 val = 0;
841 if (src_clk == &alt_ck)
842 val = 1;
843 }
844 else if (reg_offset == 0x5) {
845 if (src_clk == &apll54_ck)
846 val = 0;
847 if (src_clk == &alt_ck)
848 val = 1;
849 }
850 break;
851 case CM_PLL_SEL2:
852 src_reg_addr = (u32)&CM_CLKSEL2_PLL;
853 mask = 0x3;
854 if (src_clk == &func_32k_ck)
855 val = 0x0;
856 if (src_clk == &dpll_ck)
857 val = 0x2;
858 break;
859 case CM_SYSCLKOUT_SEL1:
860 src_reg_addr = (u32)&PRCM_CLKOUT_CTRL;
861 mask = 0x3;
862 if (src_clk == &dpll_ck)
863 val = 0;
864 if (src_clk == &sys_ck)
865 val = 1;
866 if (src_clk == &func_96m_ck)
867 val = 2;
868 if (src_clk == &func_54m_ck)
869 val = 3;
870 break;
871 }
872
873 if (val == ~0) /* Catch errors in offset */
874 *type_to_addr = 0;
875 else
876 *type_to_addr = src_reg_addr;
877 *field_mask = mask;
878
879 return val;
880}
881
882static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
883{ 641{
884 void __iomem * reg; 642 const struct clksel *clks;
885 u32 src_sel, src_off, field_val, field_mask, reg_val, rate; 643 const struct clksel_rate *clkr;
886 int ret = -EINVAL;
887
888 if (unlikely(clk->flags & CONFIG_PARTICIPANT))
889 return ret;
890
891 if (clk->flags & SRC_SEL_MASK) { /* On-chip SEL collection */
892 src_sel = (SRC_RATE_SEL_MASK & clk->flags);
893 src_off = clk->src_offset;
894
895 if (src_sel == 0)
896 goto set_parent_error;
897
898 field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
899 &field_mask);
900
901 reg = (void __iomem *)src_sel;
902
903 if (clk->usecount > 0)
904 _omap2_clk_disable(clk);
905
906 /* Set new source value (previous dividers if any in effect) */
907 reg_val = __raw_readl(reg) & ~(field_mask << src_off);
908 reg_val |= (field_val << src_off);
909 __raw_writel(reg_val, reg);
910 wmb();
911 644
912 if (clk->flags & DELAYED_APP) { 645 *parent_div = 0;
913 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); 646 *src_addr = 0;
914 wmb();
915 }
916 if (clk->usecount > 0)
917 _omap2_clk_enable(clk);
918
919 clk->parent = new_parent;
920 647
921 /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/ 648 clks = omap2_get_clksel_by_parent(clk, src_clk);
922 if ((new_parent == &core_ck) && (clk == &dss1_fck)) 649 if (clks == NULL)
923 clk->rate = new_parent->rate / 0x10; 650 return 0;
924 else
925 clk->rate = new_parent->rate;
926 651
927 if (unlikely(clk->flags & RATE_PROPAGATES)) 652 for (clkr = clks->rates; clkr->div; clkr++) {
928 propagate_rate(clk); 653 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
654 break; /* Found the default rate for this platform */
655 }
929 656
657 if (!clkr->div) {
658 printk(KERN_ERR "clock: Could not find default rate for "
659 "clock %s parent %s\n", clk->name,
660 src_clk->parent->name);
930 return 0; 661 return 0;
931 } else {
932 clk->parent = new_parent;
933 rate = new_parent->rate;
934 omap2_clk_set_rate(clk, rate);
935 ret = 0;
936 } 662 }
937 663
938 set_parent_error: 664 /* Should never happen. Add a clksel mask to the struct clk. */
939 return ret; 665 WARN_ON(clk->clksel_mask == 0);
666
667 *field_mask = clk->clksel_mask;
668 *src_addr = clk->clksel_reg;
669 *parent_div = clkr->div;
670
671 return clkr->val;
940} 672}
941 673
942/* Sets basic clocks based on the specified rate */ 674int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
943static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
944{ 675{
945 u32 flags, cur_rate, done_rate, bypass = 0; 676 void __iomem *src_addr;
946 u8 cpu_mask = 0; 677 u32 field_val, field_mask, reg_val, parent_div;
947 struct prcm_config *prcm;
948 unsigned long found_speed = 0;
949 678
950 if (clk != &virt_prcm_set) 679 if (unlikely(clk->flags & CONFIG_PARTICIPANT))
951 return -EINVAL; 680 return -EINVAL;
952 681
953 /* FIXME: Change cpu_is_omap2420() to cpu_is_omap242x() */ 682 if (!clk->clksel)
954 if (cpu_is_omap2420())
955 cpu_mask = RATE_IN_242X;
956 else if (cpu_is_omap2430())
957 cpu_mask = RATE_IN_243X;
958
959 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
960 if (!(prcm->flags & cpu_mask))
961 continue;
962
963 if (prcm->xtal_speed != sys_ck.rate)
964 continue;
965
966 if (prcm->mpu_speed <= rate) {
967 found_speed = prcm->mpu_speed;
968 break;
969 }
970 }
971
972 if (!found_speed) {
973 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
974 rate / 1000000);
975 return -EINVAL; 683 return -EINVAL;
976 }
977
978 curr_prcm_set = prcm;
979 cur_rate = omap2_get_dpll_rate(&dpll_ck);
980
981 if (prcm->dpll_speed == cur_rate / 2) {
982 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
983 } else if (prcm->dpll_speed == cur_rate * 2) {
984 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
985 } else if (prcm->dpll_speed != cur_rate) {
986 local_irq_save(flags);
987 684
988 if (prcm->dpll_speed == prcm->xtal_speed) 685 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
989 bypass = 1; 686 &field_mask, clk, &parent_div);
687 if (src_addr == 0)
688 return -EINVAL;
990 689
991 if ((prcm->cm_clksel2_pll & 0x3) == 2) 690 if (clk->usecount > 0)
992 done_rate = PRCM_FULL_SPEED; 691 _omap2_clk_disable(clk);
993 else
994 done_rate = PRCM_HALF_SPEED;
995 692
996 /* MPU divider */ 693 /* Set new source value (previous dividers if any in effect) */
997 CM_CLKSEL_MPU = prcm->cm_clksel_mpu; 694 reg_val = __raw_readl(src_addr) & ~field_mask;
695 reg_val |= (field_val << __ffs(field_mask));
696 __raw_writel(reg_val, src_addr);
697 wmb();
998 698
999 /* dsp + iva1 div(2420), iva2.1(2430) */ 699 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
1000 CM_CLKSEL_DSP = prcm->cm_clksel_dsp; 700 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
701 wmb();
702 }
1001 703
1002 CM_CLKSEL_GFX = prcm->cm_clksel_gfx; 704 if (clk->usecount > 0)
705 _omap2_clk_enable(clk);
1003 706
1004 /* Major subsystem dividers */ 707 clk->parent = new_parent;
1005 CM_CLKSEL1_CORE = prcm->cm_clksel1_core;
1006 if (cpu_is_omap2430())
1007 CM_CLKSEL_MDM = prcm->cm_clksel_mdm;
1008 708
1009 /* x2 to enter init_mem */ 709 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
1010 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); 710 clk->rate = new_parent->rate;
1011 711
1012 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, 712 if (parent_div > 0)
1013 bypass); 713 clk->rate /= parent_div;
1014 714
1015 omap2_init_memory_params(omap2_dll_force_needed()); 715 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
1016 omap2_reprogram_sdrc(done_rate, 0); 716 clk->name, clk->parent->name, clk->rate);
1017 717
1018 local_irq_restore(flags); 718 if (unlikely(clk->flags & RATE_PROPAGATES))
1019 } 719 propagate_rate(clk);
1020 omap2_clksel_recalc(&dpll_ck);
1021 720
1022 return 0; 721 return 0;
1023} 722}
@@ -1027,150 +726,17 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
1027 *-------------------------------------------------------------------------*/ 726 *-------------------------------------------------------------------------*/
1028 727
1029#ifdef CONFIG_OMAP_RESET_CLOCKS 728#ifdef CONFIG_OMAP_RESET_CLOCKS
1030static void __init omap2_clk_disable_unused(struct clk *clk) 729void omap2_clk_disable_unused(struct clk *clk)
1031{ 730{
1032 u32 regval32; 731 u32 regval32, v;
732
733 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1033 734
1034 regval32 = __raw_readl(clk->enable_reg); 735 regval32 = __raw_readl(clk->enable_reg);
1035 if ((regval32 & (1 << clk->enable_bit)) == 0) 736 if ((regval32 & (1 << clk->enable_bit)) == v)
1036 return; 737 return;
1037 738
1038 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); 739 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1039 _omap2_clk_disable(clk); 740 _omap2_clk_disable(clk);
1040} 741}
1041#else
1042#define omap2_clk_disable_unused NULL
1043#endif 742#endif
1044
1045static struct clk_functions omap2_clk_functions = {
1046 .clk_enable = omap2_clk_enable,
1047 .clk_disable = omap2_clk_disable,
1048 .clk_round_rate = omap2_clk_round_rate,
1049 .clk_set_rate = omap2_clk_set_rate,
1050 .clk_set_parent = omap2_clk_set_parent,
1051 .clk_disable_unused = omap2_clk_disable_unused,
1052};
1053
1054static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
1055{
1056 u32 div, aplls, sclk = 13000000;
1057
1058 aplls = CM_CLKSEL1_PLL;
1059 aplls &= ((1 << 23) | (1 << 24) | (1 << 25));
1060 aplls >>= 23; /* Isolate field, 0,2,3 */
1061
1062 if (aplls == 0)
1063 sclk = 19200000;
1064 else if (aplls == 2)
1065 sclk = 13000000;
1066 else if (aplls == 3)
1067 sclk = 12000000;
1068
1069 div = PRCM_CLKSRC_CTRL;
1070 div &= ((1 << 7) | (1 << 6));
1071 div >>= sys->rate_offset;
1072
1073 osc->rate = sclk * div;
1074 sys->rate = sclk;
1075}
1076
1077/*
1078 * Set clocks for bypass mode for reboot to work.
1079 */
1080void omap2_clk_prepare_for_reboot(void)
1081{
1082 u32 rate;
1083
1084 if (vclk == NULL || sclk == NULL)
1085 return;
1086
1087 rate = clk_get_rate(sclk);
1088 clk_set_rate(vclk, rate);
1089}
1090
1091/*
1092 * Switch the MPU rate if specified on cmdline.
1093 * We cannot do this early until cmdline is parsed.
1094 */
1095static int __init omap2_clk_arch_init(void)
1096{
1097 if (!mpurate)
1098 return -EINVAL;
1099
1100 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
1101 printk(KERN_ERR "Could not find matching MPU rate\n");
1102
1103 propagate_rate(&osc_ck); /* update main root fast */
1104 propagate_rate(&func_32k_ck); /* update main root slow */
1105
1106 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
1107 "%ld.%01ld/%ld/%ld MHz\n",
1108 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1109 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1110
1111 return 0;
1112}
1113arch_initcall(omap2_clk_arch_init);
1114
1115int __init omap2_clk_init(void)
1116{
1117 struct prcm_config *prcm;
1118 struct clk ** clkp;
1119 u32 clkrate;
1120
1121 clk_init(&omap2_clk_functions);
1122 omap2_get_crystal_rate(&osc_ck, &sys_ck);
1123
1124 for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
1125 clkp++) {
1126
1127 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
1128 clk_register(*clkp);
1129 continue;
1130 }
1131
1132 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
1133 clk_register(*clkp);
1134 continue;
1135 }
1136 }
1137
1138 /* Check the MPU rate set by bootloader */
1139 clkrate = omap2_get_dpll_rate(&dpll_ck);
1140 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1141 if (prcm->xtal_speed != sys_ck.rate)
1142 continue;
1143 if (prcm->dpll_speed <= clkrate)
1144 break;
1145 }
1146 curr_prcm_set = prcm;
1147
1148 propagate_rate(&osc_ck); /* update main root fast */
1149 propagate_rate(&func_32k_ck); /* update main root slow */
1150
1151 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
1152 "%ld.%01ld/%ld/%ld MHz\n",
1153 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1154 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1155
1156 /*
1157 * Only enable those clocks we will need, let the drivers
1158 * enable other clocks as necessary
1159 */
1160 clk_enable(&sync_32k_ick);
1161 clk_enable(&omapctrl_ick);
1162
1163 /* Force the APLLs always active. The clocks are idled
1164 * automatically by hardware. */
1165 clk_enable(&apll96_ck);
1166 clk_enable(&apll54_ck);
1167
1168 if (cpu_is_omap2430())
1169 clk_enable(&sdrc_ick);
1170
1171 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1172 vclk = clk_get(NULL, "virt_prcm_set");
1173 sclk = clk_get(NULL, "sys_ck");
1174
1175 return 0;
1176}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-08 15:22:03 -0400