diff options
Diffstat (limited to 'arch/arm/mach-omap2/clock.c')
-rw-r--r-- | arch/arm/mach-omap2/clock.c | 37 |
1 files changed, 23 insertions, 14 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 7edf0f69da1e..d1b648a4efbf 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -659,26 +659,35 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |||
659 | 659 | ||
660 | /* Isolate control register */ | 660 | /* Isolate control register */ |
661 | div_sel = (SRC_RATE_SEL_MASK & clk->flags); | 661 | div_sel = (SRC_RATE_SEL_MASK & clk->flags); |
662 | div_off = clk->src_offset; | 662 | div_off = clk->rate_offset; |
663 | 663 | ||
664 | validrate = omap2_clksel_round_rate(clk, rate, &new_div); | 664 | validrate = omap2_clksel_round_rate(clk, rate, &new_div); |
665 | if(validrate != rate) | 665 | if (validrate != rate) |
666 | return(ret); | 666 | return(ret); |
667 | 667 | ||
668 | field_val = omap2_get_clksel(&div_sel, &field_mask, clk); | 668 | field_val = omap2_get_clksel(&div_sel, &field_mask, clk); |
669 | if (div_sel == 0) | 669 | if (div_sel == 0) |
670 | return ret; | 670 | return ret; |
671 | 671 | ||
672 | if(clk->flags & CM_SYSCLKOUT_SEL1){ | 672 | if (clk->flags & CM_SYSCLKOUT_SEL1) { |
673 | switch(new_div){ | 673 | switch (new_div) { |
674 | case 16: field_val = 4; break; | 674 | case 16: |
675 | case 8: field_val = 3; break; | 675 | field_val = 4; |
676 | case 4: field_val = 2; break; | 676 | break; |
677 | case 2: field_val = 1; break; | 677 | case 8: |
678 | case 1: field_val = 0; break; | 678 | field_val = 3; |
679 | break; | ||
680 | case 4: | ||
681 | field_val = 2; | ||
682 | break; | ||
683 | case 2: | ||
684 | field_val = 1; | ||
685 | break; | ||
686 | case 1: | ||
687 | field_val = 0; | ||
688 | break; | ||
679 | } | 689 | } |
680 | } | 690 | } else |
681 | else | ||
682 | field_val = new_div; | 691 | field_val = new_div; |
683 | 692 | ||
684 | reg = (void __iomem *)div_sel; | 693 | reg = (void __iomem *)div_sel; |
@@ -743,7 +752,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset, | |||
743 | val = 0x2; | 752 | val = 0x2; |
744 | break; | 753 | break; |
745 | case CM_WKUP_SEL1: | 754 | case CM_WKUP_SEL1: |
746 | src_reg_addr = (u32)&CM_CLKSEL2_CORE; | 755 | src_reg_addr = (u32)&CM_CLKSEL_WKUP; |
747 | mask = 0x3; | 756 | mask = 0x3; |
748 | if (src_clk == &func_32k_ck) | 757 | if (src_clk == &func_32k_ck) |
749 | val = 0x0; | 758 | val = 0x0; |
@@ -783,9 +792,9 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset, | |||
783 | val = 0; | 792 | val = 0; |
784 | if (src_clk == &sys_ck) | 793 | if (src_clk == &sys_ck) |
785 | val = 1; | 794 | val = 1; |
786 | if (src_clk == &func_54m_ck) | ||
787 | val = 2; | ||
788 | if (src_clk == &func_96m_ck) | 795 | if (src_clk == &func_96m_ck) |
796 | val = 2; | ||
797 | if (src_clk == &func_54m_ck) | ||
789 | val = 3; | 798 | val = 3; |
790 | break; | 799 | break; |
791 | } | 800 | } |