diff options
Diffstat (limited to 'arch/arm/mach-omap2/clock.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock.c | 156 |
1 files changed, 79 insertions, 77 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index b0665f161c03..456e2ad5f621 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <mach/clock.h> | 27 | #include <mach/clock.h> |
| 28 | #include <mach/clockdomain.h> | 28 | #include <mach/clockdomain.h> |
| 29 | #include <mach/cpu.h> | 29 | #include <mach/cpu.h> |
| 30 | #include <mach/prcm.h> | ||
| 30 | #include <asm/div64.h> | 31 | #include <asm/div64.h> |
| 31 | 32 | ||
| 32 | #include <mach/sdrc.h> | 33 | #include <mach/sdrc.h> |
| @@ -38,8 +39,6 @@ | |||
| 38 | #include "cm-regbits-24xx.h" | 39 | #include "cm-regbits-24xx.h" |
| 39 | #include "cm-regbits-34xx.h" | 40 | #include "cm-regbits-34xx.h" |
| 40 | 41 | ||
| 41 | #define MAX_CLOCK_ENABLE_WAIT 100000 | ||
| 42 | |||
| 43 | /* DPLL rate rounding: minimum DPLL multiplier, divider values */ | 42 | /* DPLL rate rounding: minimum DPLL multiplier, divider values */ |
| 44 | #define DPLL_MIN_MULTIPLIER 1 | 43 | #define DPLL_MIN_MULTIPLIER 1 |
| 45 | #define DPLL_MIN_DIVIDER 1 | 44 | #define DPLL_MIN_DIVIDER 1 |
| @@ -274,83 +273,97 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk) | |||
| 274 | } | 273 | } |
| 275 | 274 | ||
| 276 | /** | 275 | /** |
| 277 | * omap2_wait_clock_ready - wait for clock to enable | 276 | * omap2_clk_dflt_find_companion - find companion clock to @clk |
| 278 | * @reg: physical address of clock IDLEST register | 277 | * @clk: struct clk * to find the companion clock of |
| 279 | * @mask: value to mask against to determine if the clock is active | 278 | * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in |
| 280 | * @name: name of the clock (for printk) | 279 | * @other_bit: u8 ** to return the companion clock bit shift in |
| 280 | * | ||
| 281 | * Note: We don't need special code here for INVERT_ENABLE for the | ||
| 282 | * time being since INVERT_ENABLE only applies to clocks enabled by | ||
| 283 | * CM_CLKEN_PLL | ||
| 281 | * | 284 | * |
| 282 | * Returns 1 if the clock enabled in time, or 0 if it failed to enable | 285 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's |
| 283 | * in roughly MAX_CLOCK_ENABLE_WAIT microseconds. | 286 | * just a matter of XORing the bits. |
| 287 | * | ||
| 288 | * Some clocks don't have companion clocks. For example, modules with | ||
| 289 | * only an interface clock (such as MAILBOXES) don't have a companion | ||
| 290 | * clock. Right now, this code relies on the hardware exporting a bit | ||
| 291 | * in the correct companion register that indicates that the | ||
| 292 | * nonexistent 'companion clock' is active. Future patches will | ||
| 293 | * associate this type of code with per-module data structures to | ||
| 294 | * avoid this issue, and remove the casts. No return value. | ||
| 284 | */ | 295 | */ |
| 285 | int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) | 296 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, |
| 297 | u8 *other_bit) | ||
| 286 | { | 298 | { |
| 287 | int i = 0; | 299 | u32 r; |
| 288 | int ena = 0; | ||
| 289 | 300 | ||
| 290 | /* | 301 | /* |
| 291 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | 302 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes |
| 292 | * 34xx reverses this, just to keep us on our toes | 303 | * it's just a matter of XORing the bits. |
| 293 | */ | 304 | */ |
| 294 | if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) | 305 | r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); |
| 295 | ena = mask; | ||
| 296 | else if (cpu_mask & RATE_IN_343X) | ||
| 297 | ena = 0; | ||
| 298 | |||
| 299 | /* Wait for lock */ | ||
| 300 | while (((__raw_readl(reg) & mask) != ena) && | ||
| 301 | (i++ < MAX_CLOCK_ENABLE_WAIT)) { | ||
| 302 | udelay(1); | ||
| 303 | } | ||
| 304 | |||
| 305 | if (i <= MAX_CLOCK_ENABLE_WAIT) | ||
| 306 | pr_debug("Clock %s stable after %d loops\n", name, i); | ||
| 307 | else | ||
| 308 | printk(KERN_ERR "Clock %s didn't enable in %d tries\n", | ||
| 309 | name, MAX_CLOCK_ENABLE_WAIT); | ||
| 310 | |||
| 311 | |||
| 312 | return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0; | ||
| 313 | }; | ||
| 314 | 306 | ||
| 307 | *other_reg = (__force void __iomem *)r; | ||
| 308 | *other_bit = clk->enable_bit; | ||
| 309 | } | ||
| 315 | 310 | ||
| 316 | /* | 311 | /** |
| 317 | * Note: We don't need special code here for INVERT_ENABLE | 312 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk |
| 318 | * for the time being since INVERT_ENABLE only applies to clocks enabled by | 313 | * @clk: struct clk * to find IDLEST info for |
| 319 | * CM_CLKEN_PLL | 314 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in |
| 315 | * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in | ||
| 316 | * | ||
| 317 | * Return the CM_IDLEST register address and bit shift corresponding | ||
| 318 | * to the module that "owns" this clock. This default code assumes | ||
| 319 | * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that | ||
| 320 | * the IDLEST register address ID corresponds to the CM_*CLKEN | ||
| 321 | * register address ID (e.g., that CM_FCLKEN2 corresponds to | ||
| 322 | * CM_IDLEST2). This is not true for all modules. No return value. | ||
| 320 | */ | 323 | */ |
| 321 | static void omap2_clk_wait_ready(struct clk *clk) | 324 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
| 325 | u8 *idlest_bit) | ||
| 322 | { | 326 | { |
| 323 | void __iomem *reg, *other_reg, *st_reg; | 327 | u32 r; |
| 324 | u32 bit; | ||
| 325 | 328 | ||
| 326 | /* | 329 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
| 327 | * REVISIT: This code is pretty ugly. It would be nice to generalize | 330 | *idlest_reg = (__force void __iomem *)r; |
| 328 | * it and pull it into struct clk itself somehow. | 331 | *idlest_bit = clk->enable_bit; |
| 329 | */ | 332 | } |
| 330 | reg = clk->enable_reg; | ||
| 331 | 333 | ||
| 332 | /* | 334 | /** |
| 333 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes | 335 | * omap2_module_wait_ready - wait for an OMAP module to leave IDLE |
| 334 | * it's just a matter of XORing the bits. | 336 | * @clk: struct clk * belonging to the module |
| 335 | */ | 337 | * |
| 336 | other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN)); | 338 | * If the necessary clocks for the OMAP hardware IP block that |
| 339 | * corresponds to clock @clk are enabled, then wait for the module to | ||
| 340 | * indicate readiness (i.e., to leave IDLE). This code does not | ||
| 341 | * belong in the clock code and will be moved in the medium term to | ||
| 342 | * module-dependent code. No return value. | ||
| 343 | */ | ||
| 344 | static void omap2_module_wait_ready(struct clk *clk) | ||
| 345 | { | ||
| 346 | void __iomem *companion_reg, *idlest_reg; | ||
| 347 | u8 other_bit, idlest_bit; | ||
| 348 | |||
| 349 | /* Not all modules have multiple clocks that their IDLEST depends on */ | ||
| 350 | if (clk->ops->find_companion) { | ||
| 351 | clk->ops->find_companion(clk, &companion_reg, &other_bit); | ||
| 352 | if (!(__raw_readl(companion_reg) & (1 << other_bit))) | ||
| 353 | return; | ||
| 354 | } | ||
| 337 | 355 | ||
| 338 | /* Check if both functional and interface clocks | 356 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit); |
| 339 | * are running. */ | ||
| 340 | bit = 1 << clk->enable_bit; | ||
| 341 | if (!(__raw_readl(other_reg) & bit)) | ||
| 342 | return; | ||
| 343 | st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */ | ||
| 344 | 357 | ||
| 345 | omap2_wait_clock_ready(st_reg, bit, clk->name); | 358 | omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name); |
| 346 | } | 359 | } |
| 347 | 360 | ||
| 348 | static int omap2_dflt_clk_enable(struct clk *clk) | 361 | int omap2_dflt_clk_enable(struct clk *clk) |
| 349 | { | 362 | { |
| 350 | u32 v; | 363 | u32 v; |
| 351 | 364 | ||
| 352 | if (unlikely(clk->enable_reg == NULL)) { | 365 | if (unlikely(clk->enable_reg == NULL)) { |
| 353 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", | 366 | pr_err("clock.c: Enable for %s without enable code\n", |
| 354 | clk->name); | 367 | clk->name); |
| 355 | return 0; /* REVISIT: -EINVAL */ | 368 | return 0; /* REVISIT: -EINVAL */ |
| 356 | } | 369 | } |
| @@ -363,26 +376,13 @@ static int omap2_dflt_clk_enable(struct clk *clk) | |||
| 363 | __raw_writel(v, clk->enable_reg); | 376 | __raw_writel(v, clk->enable_reg); |
| 364 | v = __raw_readl(clk->enable_reg); /* OCP barrier */ | 377 | v = __raw_readl(clk->enable_reg); /* OCP barrier */ |
| 365 | 378 | ||
| 366 | return 0; | 379 | if (clk->ops->find_idlest) |
| 367 | } | 380 | omap2_module_wait_ready(clk); |
| 368 | 381 | ||
| 369 | static int omap2_dflt_clk_enable_wait(struct clk *clk) | 382 | return 0; |
| 370 | { | ||
| 371 | int ret; | ||
| 372 | |||
| 373 | if (!clk->enable_reg) { | ||
| 374 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", | ||
| 375 | clk->name); | ||
| 376 | return 0; /* REVISIT: -EINVAL */ | ||
| 377 | } | ||
| 378 | |||
| 379 | ret = omap2_dflt_clk_enable(clk); | ||
| 380 | if (ret == 0) | ||
| 381 | omap2_clk_wait_ready(clk); | ||
| 382 | return ret; | ||
| 383 | } | 383 | } |
| 384 | 384 | ||
| 385 | static void omap2_dflt_clk_disable(struct clk *clk) | 385 | void omap2_dflt_clk_disable(struct clk *clk) |
| 386 | { | 386 | { |
| 387 | u32 v; | 387 | u32 v; |
| 388 | 388 | ||
| @@ -406,8 +406,10 @@ static void omap2_dflt_clk_disable(struct clk *clk) | |||
| 406 | } | 406 | } |
| 407 | 407 | ||
| 408 | const struct clkops clkops_omap2_dflt_wait = { | 408 | const struct clkops clkops_omap2_dflt_wait = { |
| 409 | .enable = omap2_dflt_clk_enable_wait, | 409 | .enable = omap2_dflt_clk_enable, |
| 410 | .disable = omap2_dflt_clk_disable, | 410 | .disable = omap2_dflt_clk_disable, |
| 411 | .find_companion = omap2_clk_dflt_find_companion, | ||
| 412 | .find_idlest = omap2_clk_dflt_find_idlest, | ||
| 411 | }; | 413 | }; |
| 412 | 414 | ||
| 413 | const struct clkops clkops_omap2_dflt = { | 415 | const struct clkops clkops_omap2_dflt = { |
