1 files changed, 221 insertions, 771 deletions

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index f2a92d614f0f..a6d0b34b7990 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -2,7 +2,7 @@
  *  linux/arch/arm/mach-omap2/clock.c
  *
  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
- *  Copyright (C) 2004-2008 Nokia Corporation
+ *  Copyright (C) 2004-2010 Nokia Corporation
  *
  *  Contacts:
  *  Richard Woodruff <r-woodruff2@ti.com>
@@ -14,24 +14,20 @@
  */
 #undef DEBUG
 
-#include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/device.h>
 #include <linux/list.h>
 #include <linux/errno.h>
+#include <linux/err.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
 
-#include <mach/clock.h>
-#include <mach/clockdomain.h>
-#include <mach/cpu.h>
-#include <mach/prcm.h>
-#include <asm/div64.h>
+#include <plat/clock.h>
+#include <plat/clockdomain.h>
+#include <plat/cpu.h>
+#include <plat/prcm.h>
 
-#include <mach/sdrc.h>
-#include "sdrc.h"
 #include "clock.h"
 #include "prm.h"
 #include "prm-regbits-24xx.h"
@@ -39,108 +35,44 @@
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
-/* DPLL rate rounding: minimum DPLL multiplier, divider values */
-#define DPLL_MIN_MULTIPLIER             1
-#define DPLL_MIN_DIVIDER                1
-
-/* Possible error results from _dpll_test_mult */
-#define DPLL_MULT_UNDERFLOW             -1
+u8 cpu_mask;
 
 /*
- * Scale factor to mitigate roundoff errors in DPLL rate rounding.
- * The higher the scale factor, the greater the risk of arithmetic overflow,
- * but the closer the rounded rate to the target rate.  DPLL_SCALE_FACTOR
- * must be a power of DPLL_SCALE_BASE.
+ * OMAP2+ specific clock functions
  */
-#define DPLL_SCALE_FACTOR               64
-#define DPLL_SCALE_BASE                 2
-#define DPLL_ROUNDING_VAL               ((DPLL_SCALE_BASE / 2) * \
-                                         (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
-
-/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
-#define DPLL_FINT_BAND1_MIN             750000
-#define DPLL_FINT_BAND1_MAX             2100000
-#define DPLL_FINT_BAND2_MIN             7500000
-#define DPLL_FINT_BAND2_MAX             21000000
-
-/* _dpll_test_fint() return codes */
-#define DPLL_FINT_UNDERFLOW             -1
-#define DPLL_FINT_INVALID               -2
-
-u8 cpu_mask;
 
-/*-------------------------------------------------------------------------
- * OMAP2/3 specific clock functions
- *-------------------------------------------------------------------------*/
+/* Private functions */
 
 /**
- * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
- * @clk: struct clk *
- *
- * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
- * don't take effect until the VALID_CONFIG bit is written, write the
- * VALID_CONFIG bit and wait for the write to complete.  No return value.
- */
-static void _omap2xxx_clk_commit(struct clk *clk)
-{
-        if (!cpu_is_omap24xx())
-                return;
-
-        if (!(clk->flags & DELAYED_APP))
-                return;
-
-        prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
-                OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
-        /* OCP barrier */
-        prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
-}
-
-/*
- * _dpll_test_fint - test whether an Fint value is valid for the DPLL
- * @clk: DPLL struct clk to test
- * @n: divider value (N) to test
+ * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
+ * @clk: struct clk * belonging to the module
  *
- * Tests whether a particular divider @n will result in a valid DPLL
- * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
- * Correction".  Returns 0 if OK, -1 if the enclosing loop can terminate
- * (assuming that it is counting N upwards), or -2 if the enclosing loop
- * should skip to the next iteration (again assuming N is increasing).
+ * If the necessary clocks for the OMAP hardware IP block that
+ * corresponds to clock @clk are enabled, then wait for the module to
+ * indicate readiness (i.e., to leave IDLE).  This code does not
+ * belong in the clock code and will be moved in the medium term to
+ * module-dependent code.  No return value.
  */
-static int _dpll_test_fint(struct clk *clk, u8 n)
+static void _omap2_module_wait_ready(struct clk *clk)
 {
-        struct dpll_data *dd;
-        long fint;
-        int ret = 0;
-
-        dd = clk->dpll_data;
-
-        /* DPLL divider must result in a valid jitter correction val */
-        fint = clk->parent->rate / (n + 1);
-        if (fint < DPLL_FINT_BAND1_MIN) {
-
-                pr_debug("rejecting n=%d due to Fint failure, "
-                         "lowering max_divider\n", n);
-                dd->max_divider = n;
-                ret = DPLL_FINT_UNDERFLOW;
-
-        } else if (fint > DPLL_FINT_BAND1_MAX &&
-                   fint < DPLL_FINT_BAND2_MIN) {
-
-                pr_debug("rejecting n=%d due to Fint failure\n", n);
-                ret = DPLL_FINT_INVALID;
-
-        } else if (fint > DPLL_FINT_BAND2_MAX) {
-
-                pr_debug("rejecting n=%d due to Fint failure, "
-                         "boosting min_divider\n", n);
-                dd->min_divider = n;
-                ret = DPLL_FINT_INVALID;
+        void __iomem *companion_reg, *idlest_reg;
+        u8 other_bit, idlest_bit, idlest_val;
 
+        /* Not all modules have multiple clocks that their IDLEST depends on */
+        if (clk->ops->find_companion) {
+                clk->ops->find_companion(clk, &companion_reg, &other_bit);
+                if (!(__raw_readl(companion_reg) & (1 << other_bit)))
+                        return;
         }
 
-        return ret;
+        clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
+
+        omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
+                             clk->name);
 }
 
+/* Public functions */
+
 /**
  * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
  * @clk: OMAP clock struct ptr to use
@@ -168,111 +100,6 @@ void omap2_init_clk_clkdm(struct clk *clk)
 }
 
 /**
- * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
- * @clk: OMAP clock struct ptr to use
- *
- * Given a pointer to a source-selectable struct clk, read the hardware
- * register and determine what its parent is currently set to.  Update the
- * clk->parent field with the appropriate clk ptr.
- */
-void omap2_init_clksel_parent(struct clk *clk)
-{
-        const struct clksel *clks;
-        const struct clksel_rate *clkr;
-        u32 r, found = 0;
-
-        if (!clk->clksel)
-                return;
-
-        r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
-        r >>= __ffs(clk->clksel_mask);
-
-        for (clks = clk->clksel; clks->parent && !found; clks++) {
-                for (clkr = clks->rates; clkr->div && !found; clkr++) {
-                        if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
-                                if (clk->parent != clks->parent) {
-                                        pr_debug("clock: inited %s parent "
-                                                 "to %s (was %s)\n",
-                                                 clk->name, clks->parent->name,
-                                                 ((clk->parent) ?
-                                                  clk->parent->name : "NULL"));
-                                        clk_reparent(clk, clks->parent);
-                                };
-                                found = 1;
-                        }
-                }
-        }
-
-        if (!found)
-                printk(KERN_ERR "clock: init parent: could not find "
-                       "regval %0x for clock %s\n", r,  clk->name);
-
-        return;
-}
-
-/**
- * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
- * @clk: struct clk * of a DPLL
- *
- * DPLLs can be locked or bypassed - basically, enabled or disabled.
- * When locked, the DPLL output depends on the M and N values.  When
- * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
- * or sys_clk.  Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
- * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
- * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
- * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
- * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
- * if the clock @clk is not a DPLL.
- */
-u32 omap2_get_dpll_rate(struct clk *clk)
-{
-        long long dpll_clk;
-        u32 dpll_mult, dpll_div, v;
-        struct dpll_data *dd;
-
-        dd = clk->dpll_data;
-        if (!dd)
-                return 0;
-
-        /* Return bypass rate if DPLL is bypassed */
-        v = __raw_readl(dd->control_reg);
-        v &= dd->enable_mask;
-        v >>= __ffs(dd->enable_mask);
-
-        if (cpu_is_omap24xx()) {
-                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
-                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
-                        return dd->clk_bypass->rate;
-        } else if (cpu_is_omap34xx()) {
-                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
-                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
-                        return dd->clk_bypass->rate;
-        }
-
-        v = __raw_readl(dd->mult_div1_reg);
-        dpll_mult = v & dd->mult_mask;
-        dpll_mult >>= __ffs(dd->mult_mask);
-        dpll_div = v & dd->div1_mask;
-        dpll_div >>= __ffs(dd->div1_mask);
-
-        dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
-        do_div(dpll_clk, dpll_div + 1);
-
-        return dpll_clk;
-}
-
-/*
- * Used for clocks that have the same value as the parent clock,
- * divided by some factor
- */
-unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
-{
-        WARN_ON(!clk->fixed_div);
-
-        return clk->parent->rate / clk->fixed_div;
-}
-
-/**
  * omap2_clk_dflt_find_companion - find companion clock to @clk
  * @clk: struct clk * to find the companion clock of
  * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
@@ -312,7 +139,8 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
  * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
  * @clk: struct clk * to find IDLEST info for
  * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
- * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in
+ * @idlest_bit: u8 * to return the CM_IDLEST bit shift in
+ * @idlest_val: u8 * to return the idle status indicator
  *
  * Return the CM_IDLEST register address and bit shift corresponding
  * to the module that "owns" this clock.  This default code assumes
@@ -322,40 +150,26 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
  * CM_IDLEST2).  This is not true for all modules.  No return value.
  */
 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
-                                u8 *idlest_bit)
+                                u8 *idlest_bit, u8 *idlest_val)
 {
         u32 r;
 
         r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
         *idlest_reg = (__force void __iomem *)r;
         *idlest_bit = clk->enable_bit;
-}
 
-/**
- * omap2_module_wait_ready - wait for an OMAP module to leave IDLE
- * @clk: struct clk * belonging to the module
- *
- * If the necessary clocks for the OMAP hardware IP block that
- * corresponds to clock @clk are enabled, then wait for the module to
- * indicate readiness (i.e., to leave IDLE).  This code does not
- * belong in the clock code and will be moved in the medium term to
- * module-dependent code.  No return value.
- */
-static void omap2_module_wait_ready(struct clk *clk)
-{
-        void __iomem *companion_reg, *idlest_reg;
-        u8 other_bit, idlest_bit;
-
-        /* Not all modules have multiple clocks that their IDLEST depends on */
-        if (clk->ops->find_companion) {
-                clk->ops->find_companion(clk, &companion_reg, &other_bit);
-                if (!(__raw_readl(companion_reg) & (1 << other_bit)))
-                        return;
-        }
-
-        clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit);
+        /*
+         * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
+         * 34xx reverses this, just to keep us on our toes
+         * AM35xx uses both, depending on the module.
+         */
+        if (cpu_is_omap24xx())
+                *idlest_val = OMAP24XX_CM_IDLEST_VAL;
+        else if (cpu_is_omap34xx())
+                *idlest_val = OMAP34XX_CM_IDLEST_VAL;
+        else
+                BUG();
 
-        omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name);
 }
 
 int omap2_dflt_clk_enable(struct clk *clk)
@@ -377,7 +191,7 @@ int omap2_dflt_clk_enable(struct clk *clk)
         v = __raw_readl(clk->enable_reg); /* OCP barrier */
 
         if (clk->ops->find_idlest)
-                omap2_module_wait_ready(clk);
+                _omap2_module_wait_ready(clk);
 
         return 0;
 }
@@ -417,331 +231,109 @@ const struct clkops clkops_omap2_dflt = {
         .disable        = omap2_dflt_clk_disable,
 };
 
-/* Enables clock without considering parent dependencies or use count
- * REVISIT: Maybe change this to use clk->enable like on omap1?
+/**
+ * omap2_clk_disable - disable a clock, if the system is not using it
+ * @clk: struct clk * to disable
+ *
+ * Decrements the usecount on struct clk @clk.  If there are no users
+ * left, call the clkops-specific clock disable function to disable it
+ * in hardware.  If the clock is part of a clockdomain (which they all
+ * should be), request that the clockdomain be disabled.  (It too has
+ * a usecount, and so will not be disabled in the hardware until it no
+ * longer has any users.)  If the clock has a parent clock (most of
+ * them do), then call ourselves, recursing on the parent clock.  This
+ * can cause an entire branch of the clock tree to be powered off by
+ * simply disabling one clock.  Intended to be called with the clockfw_lock
+ * spinlock held.  No return value.
  */
-static int _omap2_clk_enable(struct clk *clk)
-{
-        return clk->ops->enable(clk);
-}
-
-/* Disables clock without considering parent dependencies or use count */
-static void _omap2_clk_disable(struct clk *clk)
-{
-        clk->ops->disable(clk);
-}
-
 void omap2_clk_disable(struct clk *clk)
 {
-        if (clk->usecount > 0 && !(--clk->usecount)) {
-                _omap2_clk_disable(clk);
-                if (clk->parent)
-                        omap2_clk_disable(clk->parent);
-                if (clk->clkdm)
-                        omap2_clkdm_clk_disable(clk->clkdm, clk);
-
+        if (clk->usecount == 0) {
+                WARN(1, "clock: %s: omap2_clk_disable() called, but usecount "
+                     "already 0?", clk->name);
+                return;
         }
-}
 
-int omap2_clk_enable(struct clk *clk)
-{
-        int ret = 0;
+        pr_debug("clock: %s: decrementing usecount\n", clk->name);
 
-        if (clk->usecount++ == 0) {
-                if (clk->clkdm)
-                        omap2_clkdm_clk_enable(clk->clkdm, clk);
+        clk->usecount--;
 
-                if (clk->parent) {
-                        ret = omap2_clk_enable(clk->parent);
-                        if (ret)
-                                goto err;
-                }
+        if (clk->usecount > 0)
+                return;
 
-                ret = _omap2_clk_enable(clk);
-                if (ret) {
-                        if (clk->parent)
-                                omap2_clk_disable(clk->parent);
+        pr_debug("clock: %s: disabling in hardware\n", clk->name);
 
-                        goto err;
-                }
-        }
-        return ret;
+        clk->ops->disable(clk);
 
-err:
         if (clk->clkdm)
                 omap2_clkdm_clk_disable(clk->clkdm, clk);
-        clk->usecount--;
-        return ret;
-}
 
-/*
- * Used for clocks that are part of CLKSEL_xyz governed clocks.
- * REVISIT: Maybe change to use clk->enable() functions like on omap1?
- */
-unsigned long omap2_clksel_recalc(struct clk *clk)
-{
-        unsigned long rate;
-        u32 div = 0;
-
-        pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
-
-        div = omap2_clksel_get_divisor(clk);
-        if (div == 0)
-                return clk->rate;
-
-        rate = clk->parent->rate / div;
-
-        pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div);
-
-        return rate;
-}
-
-/**
- * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
- * @clk: OMAP struct clk ptr to inspect
- * @src_clk: OMAP struct clk ptr of the parent clk to search for
- *
- * Scan the struct clksel array associated with the clock to find
- * the element associated with the supplied parent clock address.
- * Returns a pointer to the struct clksel on success or NULL on error.
- */
-static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
-                                                       struct clk *src_clk)
-{
-        const struct clksel *clks;
-
-        if (!clk->clksel)
-                return NULL;
-
-        for (clks = clk->clksel; clks->parent; clks++) {
-                if (clks->parent == src_clk)
-                        break; /* Found the requested parent */
-        }
-
-        if (!clks->parent) {
-                printk(KERN_ERR "clock: Could not find parent clock %s in "
-                       "clksel array of clock %s\n", src_clk->name,
-                       clk->name);
-                return NULL;
-        }
-
-        return clks;
+        if (clk->parent)
+                omap2_clk_disable(clk->parent);
 }
 
 /**
- * omap2_clksel_round_rate_div - find divisor for the given clock and rate
- * @clk: OMAP struct clk to use
- * @target_rate: desired clock rate
- * @new_div: ptr to where we should store the divisor
- *
- * Finds 'best' divider value in an array based on the source and target
- * rates.  The divider array must be sorted with smallest divider first.
- * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
- * they are only settable as part of virtual_prcm set.
+ * omap2_clk_enable - request that the system enable a clock
+ * @clk: struct clk * to enable
  *
- * Returns the rounded clock rate or returns 0xffffffff on error.
+ * Increments the usecount on struct clk @clk.  If there were no users
+ * previously, then recurse up the clock tree, enabling all of the
+ * clock's parents and all of the parent clockdomains, and finally,
+ * enabling @clk's clockdomain, and @clk itself.  Intended to be
+ * called with the clockfw_lock spinlock held.  Returns 0 upon success
+ * or a negative error code upon failure.
  */
-u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
-                                u32 *new_div)
-{
-        unsigned long test_rate;
-        const struct clksel *clks;
-        const struct clksel_rate *clkr;
-        u32 last_div = 0;
-
-        pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
-                 clk->name, target_rate);
-
-        *new_div = 1;
-
-        clks = omap2_get_clksel_by_parent(clk, clk->parent);
-        if (!clks)
-                return ~0;
-
-        for (clkr = clks->rates; clkr->div; clkr++) {
-                if (!(clkr->flags & cpu_mask))
-                    continue;
-
-                /* Sanity check */
-                if (clkr->div <= last_div)
-                        pr_err("clock: clksel_rate table not sorted "
-                               "for clock %s", clk->name);
-
-                last_div = clkr->div;
-
-                test_rate = clk->parent->rate / clkr->div;
-
-                if (test_rate <= target_rate)
-                        break; /* found it */
-        }
-
-        if (!clkr->div) {
-                pr_err("clock: Could not find divisor for target "
-                       "rate %ld for clock %s parent %s\n", target_rate,
-                       clk->name, clk->parent->name);
-                return ~0;
-        }
-
-        *new_div = clkr->div;
-
-        pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
-                 (clk->parent->rate / clkr->div));
-
-        return (clk->parent->rate / clkr->div);
-}
-
-/**
- * omap2_clksel_round_rate - find rounded rate for the given clock and rate
- * @clk: OMAP struct clk to use
- * @target_rate: desired clock rate
- *
- * Compatibility wrapper for OMAP clock framework
- * Finds best target rate based on the source clock and possible dividers.
- * rates. The divider array must be sorted with smallest divider first.
- * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
- * they are only settable as part of virtual_prcm set.
- *
- * Returns the rounded clock rate or returns 0xffffffff on error.
- */
-long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
-{
-        u32 new_div;
-
-        return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
-}
-
-
-/* Given a clock and a rate apply a clock specific rounding function */
-long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+int omap2_clk_enable(struct clk *clk)
 {
-        if (clk->round_rate)
-                return clk->round_rate(clk, rate);
+        int ret;
 
-        if (clk->flags & RATE_FIXED)
-                printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
-                       "on fixed-rate clock %s\n", clk->name);
+        pr_debug("clock: %s: incrementing usecount\n", clk->name);
 
-        return clk->rate;
-}
+        clk->usecount++;
 
-/**
- * omap2_clksel_to_divisor() - turn clksel field value into integer divider
- * @clk: OMAP struct clk to use
- * @field_val: register field value to find
- *
- * Given a struct clk of a rate-selectable clksel clock, and a register field
- * value to search for, find the corresponding clock divisor.  The register
- * field value should be pre-masked and shifted down so the LSB is at bit 0
- * before calling.  Returns 0 on error
- */
-u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
-{
-        const struct clksel *clks;
-        const struct clksel_rate *clkr;
-
-        clks = omap2_get_clksel_by_parent(clk, clk->parent);
-        if (!clks)
+        if (clk->usecount > 1)
                 return 0;
 
-        for (clkr = clks->rates; clkr->div; clkr++) {
-                if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
-                        break;
-        }
+        pr_debug("clock: %s: enabling in hardware\n", clk->name);
 
-        if (!clkr->div) {
-                printk(KERN_ERR "clock: Could not find fieldval %d for "
-                       "clock %s parent %s\n", field_val, clk->name,
-                       clk->parent->name);
-                return 0;
+        if (clk->parent) {
+                ret = omap2_clk_enable(clk->parent);
+                if (ret) {
+                        WARN(1, "clock: %s: could not enable parent %s: %d\n",
+                             clk->name, clk->parent->name, ret);
+                        goto oce_err1;
+                }
         }
 
-        return clkr->div;
-}
-
-/**
- * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
- * @clk: OMAP struct clk to use
- * @div: integer divisor to search for
- *
- * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
- * find the corresponding register field value.  The return register value is
- * the value before left-shifting.  Returns ~0 on error
- */
-u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
-{
-        const struct clksel *clks;
-        const struct clksel_rate *clkr;
-
-        /* should never happen */
-        WARN_ON(div == 0);
-
-        clks = omap2_get_clksel_by_parent(clk, clk->parent);
-        if (!clks)
-                return ~0;
-
-        for (clkr = clks->rates; clkr->div; clkr++) {
-                if ((clkr->flags & cpu_mask) && (clkr->div == div))
-                        break;
+        if (clk->clkdm) {
+                ret = omap2_clkdm_clk_enable(clk->clkdm, clk);
+                if (ret) {
+                        WARN(1, "clock: %s: could not enable clockdomain %s: "
+                             "%d\n", clk->name, clk->clkdm->name, ret);
+                        goto oce_err2;
+                }
         }
 
-        if (!clkr->div) {
-                printk(KERN_ERR "clock: Could not find divisor %d for "
-                       "clock %s parent %s\n", div, clk->name,
-                       clk->parent->name);
-                return ~0;
+        ret = clk->ops->enable(clk);
+        if (ret) {
+                WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret);
+                goto oce_err3;
         }
 
-        return clkr->val;
-}
-
-/**
- * omap2_clksel_get_divisor - get current divider applied to parent clock.
- * @clk: OMAP struct clk to use.
- *
- * Returns the integer divisor upon success or 0 on error.
- */
-u32 omap2_clksel_get_divisor(struct clk *clk)
-{
-        u32 v;
-
-        if (!clk->clksel_mask)
-                return 0;
-
-        v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
-        v >>= __ffs(clk->clksel_mask);
-
-        return omap2_clksel_to_divisor(clk, v);
-}
-
-int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
-{
-        u32 v, field_val, validrate, new_div = 0;
-
-        if (!clk->clksel_mask)
-                return -EINVAL;
-
-        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
-        if (validrate != rate)
-                return -EINVAL;
-
-        field_val = omap2_divisor_to_clksel(clk, new_div);
-        if (field_val == ~0)
-                return -EINVAL;
-
-        v = __raw_readl(clk->clksel_reg);
-        v &= ~clk->clksel_mask;
-        v |= field_val << __ffs(clk->clksel_mask);
-        __raw_writel(v, clk->clksel_reg);
-        v = __raw_readl(clk->clksel_reg); /* OCP barrier */
-
-        clk->rate = clk->parent->rate / new_div;
+        return 0;
 
-        _omap2xxx_clk_commit(clk);
+oce_err3:
+        if (clk->clkdm)
+                omap2_clkdm_clk_disable(clk->clkdm, clk);
+oce_err2:
+        if (clk->parent)
+                omap2_clk_disable(clk->parent);
+oce_err1:
+        clk->usecount--;
 
-        return 0;
+        return ret;
 }
 
-
 /* Set the clock rate for a clock source */
 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 {
@@ -749,11 +341,6 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 
         pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
 
-        /* CONFIG_PARTICIPANT clocks are changed only in sets via the
-           rate table mechanism, driven by mpu_speed  */
-        if (clk->flags & CONFIG_PARTICIPANT)
-                return -EINVAL;
-
         /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
         if (clk->set_rate)
                 ret = clk->set_rate(clk, rate);
@@ -761,289 +348,152 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
         return ret;
 }
 
-/*
- * Converts encoded control register address into a full address
- * On error, the return value (parent_div) will be 0.
- */
-static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
-                                       u32 *field_val)
-{
-        const struct clksel *clks;
-        const struct clksel_rate *clkr;
-
-        clks = omap2_get_clksel_by_parent(clk, src_clk);
-        if (!clks)
-                return 0;
-
-        for (clkr = clks->rates; clkr->div; clkr++) {
-                if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE)
-                        break; /* Found the default rate for this platform */
-        }
-
-        if (!clkr->div) {
-                printk(KERN_ERR "clock: Could not find default rate for "
-                       "clock %s parent %s\n", clk->name,
-                       src_clk->parent->name);
-                return 0;
-        }
-
-        /* Should never happen.  Add a clksel mask to the struct clk. */
-        WARN_ON(clk->clksel_mask == 0);
-
-        *field_val = clkr->val;
-
-        return clkr->div;
-}
-
 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 {
-        u32 field_val, v, parent_div;
-
-        if (clk->flags & CONFIG_PARTICIPANT)
-                return -EINVAL;
-
         if (!clk->clksel)
                 return -EINVAL;
 
-        parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
-        if (!parent_div)
-                return -EINVAL;
-
-        /* Set new source value (previous dividers if any in effect) */
-        v = __raw_readl(clk->clksel_reg);
-        v &= ~clk->clksel_mask;
-        v |= field_val << __ffs(clk->clksel_mask);
-        __raw_writel(v, clk->clksel_reg);
-        v = __raw_readl(clk->clksel_reg);    /* OCP barrier */
-
-        _omap2xxx_clk_commit(clk);
-
-        clk_reparent(clk, new_parent);
-
-        /* CLKSEL clocks follow their parents' rates, divided by a divisor */
-        clk->rate = new_parent->rate;
-
-        if (parent_div > 0)
-                clk->rate /= parent_div;
-
-        pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
-                 clk->name, clk->parent->name, clk->rate);
+        if (clk->parent == new_parent)
+                return 0;
 
-        return 0;
+        return omap2_clksel_set_parent(clk, new_parent);
 }
 
-/* DPLL rate rounding code */
-
-/**
- * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
- * @clk: struct clk * of the DPLL
- * @tolerance: maximum rate error tolerance
- *
- * Set the maximum DPLL rate error tolerance for the rate rounding
- * algorithm.  The rate tolerance is an attempt to balance DPLL power
- * saving (the least divider value "n") vs. rate fidelity (the least
- * difference between the desired DPLL target rate and the rounded
- * rate out of the algorithm).  So, increasing the tolerance is likely
- * to decrease DPLL power consumption and increase DPLL rate error.
- * Returns -EINVAL if provided a null clock ptr or a clk that is not a
- * DPLL; or 0 upon success.
- */
-int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
-{
-        if (!clk || !clk->dpll_data)
-                return -EINVAL;
+/* OMAP3/4 non-CORE DPLL clkops */
 
-        clk->dpll_data->rate_tolerance = tolerance;
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 
-        return 0;
-}
+const struct clkops clkops_omap3_noncore_dpll_ops = {
+        .enable         = omap3_noncore_dpll_enable,
+        .disable        = omap3_noncore_dpll_disable,
+};
 
-static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
-                                            unsigned int m, unsigned int n)
-{
-        unsigned long long num;
+#endif
 
-        num = (unsigned long long)parent_rate * m;
-        do_div(num, n);
-        return num;
-}
 
 /*
- * _dpll_test_mult - test a DPLL multiplier value
- * @m: pointer to the DPLL m (multiplier) value under test
- * @n: current DPLL n (divider) value under test
- * @new_rate: pointer to storage for the resulting rounded rate
- * @target_rate: the desired DPLL rate
- * @parent_rate: the DPLL's parent clock rate
- *
- * This code tests a DPLL multiplier value, ensuring that the
- * resulting rate will not be higher than the target_rate, and that
- * the multiplier value itself is valid for the DPLL.  Initially, the
- * integer pointed to by the m argument should be prescaled by
- * multiplying by DPLL_SCALE_FACTOR.  The code will replace this with
- * a non-scaled m upon return.  This non-scaled m will result in a
- * new_rate as close as possible to target_rate (but not greater than
- * target_rate) given the current (parent_rate, n, prescaled m)
- * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
- * non-scaled m attempted to underflow, which can allow the calling
- * function to bail out early; or 0 upon success.
+ * OMAP2+ clock reset and init functions
  */
-static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
-                           unsigned long target_rate,
-                           unsigned long parent_rate)
+
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+void omap2_clk_disable_unused(struct clk *clk)
 {
-        int r = 0, carry = 0;
+        u32 regval32, v;
 
-        /* Unscale m and round if necessary */
-        if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
-                carry = 1;
-        *m = (*m / DPLL_SCALE_FACTOR) + carry;
+        v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
 
-        /*
-         * The new rate must be <= the target rate to avoid programming
-         * a rate that is impossible for the hardware to handle
-         */
-        *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
-        if (*new_rate > target_rate) {
-                (*m)--;
-                *new_rate = 0;
-        }
+        regval32 = __raw_readl(clk->enable_reg);
+        if ((regval32 & (1 << clk->enable_bit)) == v)
+                return;
 
-        /* Guard against m underflow */
-        if (*m < DPLL_MIN_MULTIPLIER) {
-                *m = DPLL_MIN_MULTIPLIER;
-                *new_rate = 0;
-                r = DPLL_MULT_UNDERFLOW;
+        printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name);
+        if (cpu_is_omap34xx()) {
+                omap2_clk_enable(clk);
+                omap2_clk_disable(clk);
+        } else {
+                clk->ops->disable(clk);
         }
-
-        if (*new_rate == 0)
-                *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
-
-        return r;
+        if (clk->clkdm != NULL)
+                pwrdm_clkdm_state_switch(clk->clkdm);
 }
+#endif
 
 /**
- * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
- * @clk: struct clk * for a DPLL
- * @target_rate: desired DPLL clock rate
+ * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
+ * @mpurate_ck_name: clk name of the clock to change rate
  *
- * Given a DPLL, a desired target rate, and a rate tolerance, round
- * the target rate to a possible, programmable rate for this DPLL.
- * Rate tolerance is assumed to be set by the caller before this
- * function is called.  Attempts to select the minimum possible n
- * within the tolerance to reduce power consumption.  Stores the
- * computed (m, n) in the DPLL's dpll_data structure so set_rate()
- * will not need to call this (expensive) function again.  Returns ~0
- * if the target rate cannot be rounded, either because the rate is
- * too low or because the rate tolerance is set too tightly; or the
- * rounded rate upon success.
+ * Change the ARM MPU clock rate to the rate specified on the command
+ * line, if one was specified.  @mpurate_ck_name should be
+ * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx.
+ * XXX Does not handle voltage scaling - on OMAP2xxx this is currently
+ * handled by the virt_prcm_set clock, but this should be handled by
+ * the OPP layer.  XXX This is intended to be handled by the OPP layer
+ * code in the near future and should be removed from the clock code.
+ * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects
+ * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name
+ * cannot be found, or 0 upon success.
  */
-long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
+int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
 {
-        int m, n, r, e, scaled_max_m;
-        unsigned long scaled_rt_rp, new_rate;
-        int min_e = -1, min_e_m = -1, min_e_n = -1;
-        struct dpll_data *dd;
-
-        if (!clk || !clk->dpll_data)
-                return ~0;
-
-        dd = clk->dpll_data;
+        struct clk *mpurate_ck;
+        int r;
 
-        pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
-                 "%ld\n", clk->name, target_rate);
-
-        scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
-        scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
-
-        dd->last_rounded_rate = 0;
-
-        for (n = dd->min_divider; n <= dd->max_divider; n++) {
-
-                /* Is the (input clk, divider) pair valid for the DPLL? */
-                r = _dpll_test_fint(clk, n);
-                if (r == DPLL_FINT_UNDERFLOW)
-                        break;
-                else if (r == DPLL_FINT_INVALID)
-                        continue;
-
-                /* Compute the scaled DPLL multiplier, based on the divider */
-                m = scaled_rt_rp * n;
-
-                /*
-                 * Since we're counting n up, a m overflow means we
-                 * can bail out completely (since as n increases in
-                 * the next iteration, there's no way that m can
-                 * increase beyond the current m)
-                 */
-                if (m > scaled_max_m)
-                        break;
-
-                r = _dpll_test_mult(&m, n, &new_rate, target_rate,
-                                    dd->clk_ref->rate);
-
-                /* m can't be set low enough for this n - try with a larger n */
-                if (r == DPLL_MULT_UNDERFLOW)
-                        continue;
-
-                e = target_rate - new_rate;
-                pr_debug("clock: n = %d: m = %d: rate error is %d "
-                         "(new_rate = %ld)\n", n, m, e, new_rate);
-
-                if (min_e == -1 ||
-                    min_e >= (int)(abs(e) - dd->rate_tolerance)) {
-                        min_e = e;
-                        min_e_m = m;
-                        min_e_n = n;
-
-                        pr_debug("clock: found new least error %d\n", min_e);
+        if (!mpurate)
+                return -EINVAL;
 
-                        /* We found good settings -- bail out now */
-                        if (min_e <= dd->rate_tolerance)
-                                break;
-                }
-        }
+        mpurate_ck = clk_get(NULL, mpurate_ck_name);
+        if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name))
+                return -ENOENT;
 
-        if (min_e < 0) {
-                pr_debug("clock: error: target rate or tolerance too low\n");
-                return ~0;
+        r = clk_set_rate(mpurate_ck, mpurate);
+        if (IS_ERR_VALUE(r)) {
+                WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
+                     mpurate_ck->name, mpurate, r);
+                return -EINVAL;
         }
 
-        dd->last_rounded_m = min_e_m;
-        dd->last_rounded_n = min_e_n;
-        dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
-                                                       min_e_m,  min_e_n);
+        calibrate_delay();
+        recalculate_root_clocks();
 
-        pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
-                 min_e, min_e_m, min_e_n);
-        pr_debug("clock: final rate: %ld  (target rate: %ld)\n",
-                 dd->last_rounded_rate, target_rate);
+        clk_put(mpurate_ck);
 
-        return dd->last_rounded_rate;
+        return 0;
 }
 
-/*-------------------------------------------------------------------------
- * Omap2 clock reset and init functions
- *-------------------------------------------------------------------------*/
-
-#ifdef CONFIG_OMAP_RESET_CLOCKS
-void omap2_clk_disable_unused(struct clk *clk)
+/**
+ * omap2_clk_print_new_rates - print summary of current clock tree rates
+ * @hfclkin_ck_name: clk name for the off-chip HF oscillator
+ * @core_ck_name: clk name for the on-chip CORE_CLK
+ * @mpu_ck_name: clk name for the ARM MPU clock
+ *
+ * Prints a short message to the console with the HFCLKIN oscillator
+ * rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
+ * Called by the boot-time MPU rate switching code.   XXX This is intended
+ * to be handled by the OPP layer code in the near future and should be
+ * removed from the clock code.  No return value.
+ */
+void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
+                                      const char *core_ck_name,
+                                      const char *mpu_ck_name)
 {
-        u32 regval32, v;
+        struct clk *hfclkin_ck, *core_ck, *mpu_ck;
+        unsigned long hfclkin_rate;
 
-        v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
+        mpu_ck = clk_get(NULL, mpu_ck_name);
+        if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
+                return;
 
-        regval32 = __raw_readl(clk->enable_reg);
-        if ((regval32 & (1 << clk->enable_bit)) == v)
+        core_ck = clk_get(NULL, core_ck_name);
+        if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
                 return;
 
-        printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name);
-        if (cpu_is_omap34xx()) {
-                omap2_clk_enable(clk);
-                omap2_clk_disable(clk);
-        } else
-                _omap2_clk_disable(clk);
-        if (clk->clkdm != NULL)
-                pwrdm_clkdm_state_switch(clk->clkdm);
-}
+        hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
+        if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
+                return;
+
+        hfclkin_rate = clk_get_rate(hfclkin_ck);
+
+        pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
+                "%ld.%01ld/%ld/%ld MHz\n",
+                (hfclkin_rate / 1000000),
+                ((hfclkin_rate / 100000) % 10),
+                (clk_get_rate(core_ck) / 1000000),
+                (clk_get_rate(mpu_ck) / 1000000));
+}
+
+/* Common data */
+
+struct clk_functions omap2_clk_functions = {
+        .clk_enable             = omap2_clk_enable,
+        .clk_disable            = omap2_clk_disable,
+        .clk_round_rate         = omap2_clk_round_rate,
+        .clk_set_rate           = omap2_clk_set_rate,
+        .clk_set_parent         = omap2_clk_set_parent,
+        .clk_disable_unused     = omap2_clk_disable_unused,
+#ifdef CONFIG_CPU_FREQ
+        /* These will be removed when the OPP code is integrated */
+        .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
+        .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table,
 #endif
+};
+