diff options
Diffstat (limited to 'arch/arm/mach-omap2/clkt2xxx_apll.c')
-rw-r--r-- | arch/arm/mach-omap2/clkt2xxx_apll.c | 56 |
1 files changed, 14 insertions, 42 deletions
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index e3f0c1e262a7..75561a6b04d3 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c | |||
@@ -37,44 +37,16 @@ | |||
37 | #define APLLS_CLKIN_13MHZ 2 | 37 | #define APLLS_CLKIN_13MHZ 2 |
38 | #define APLLS_CLKIN_12MHZ 3 | 38 | #define APLLS_CLKIN_12MHZ 3 |
39 | 39 | ||
40 | void __iomem *cm_idlest_pll; | ||
41 | |||
42 | /* Private functions */ | 40 | /* Private functions */ |
43 | 41 | ||
44 | /* Enable an APLL if off */ | 42 | static int _apll96_enable(struct clk *clk) |
45 | static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) | ||
46 | { | ||
47 | u32 cval, apll_mask; | ||
48 | |||
49 | apll_mask = EN_APLL_LOCKED << clk->enable_bit; | ||
50 | |||
51 | cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); | ||
52 | |||
53 | if ((cval & apll_mask) == apll_mask) | ||
54 | return 0; /* apll already enabled */ | ||
55 | |||
56 | cval &= ~apll_mask; | ||
57 | cval |= apll_mask; | ||
58 | omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | ||
59 | |||
60 | omap2_cm_wait_idlest(cm_idlest_pll, status_mask, | ||
61 | OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk)); | ||
62 | |||
63 | /* | ||
64 | * REVISIT: Should we return an error code if omap2_wait_clock_ready() | ||
65 | * fails? | ||
66 | */ | ||
67 | return 0; | ||
68 | } | ||
69 | |||
70 | static int omap2_clk_apll96_enable(struct clk *clk) | ||
71 | { | 43 | { |
72 | return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK); | 44 | return omap2xxx_cm_apll96_enable(); |
73 | } | 45 | } |
74 | 46 | ||
75 | static int omap2_clk_apll54_enable(struct clk *clk) | 47 | static int _apll54_enable(struct clk *clk) |
76 | { | 48 | { |
77 | return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK); | 49 | return omap2xxx_cm_apll54_enable(); |
78 | } | 50 | } |
79 | 51 | ||
80 | static void _apll96_allow_idle(struct clk *clk) | 52 | static void _apll96_allow_idle(struct clk *clk) |
@@ -97,28 +69,28 @@ static void _apll54_deny_idle(struct clk *clk) | |||
97 | omap2xxx_cm_set_apll54_disable_autoidle(); | 69 | omap2xxx_cm_set_apll54_disable_autoidle(); |
98 | } | 70 | } |
99 | 71 | ||
100 | /* Stop APLL */ | 72 | static void _apll96_disable(struct clk *clk) |
101 | static void omap2_clk_apll_disable(struct clk *clk) | ||
102 | { | 73 | { |
103 | u32 cval; | 74 | omap2xxx_cm_apll96_disable(); |
75 | } | ||
104 | 76 | ||
105 | cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); | 77 | static void _apll54_disable(struct clk *clk) |
106 | cval &= ~(EN_APLL_LOCKED << clk->enable_bit); | 78 | { |
107 | omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | 79 | omap2xxx_cm_apll54_disable(); |
108 | } | 80 | } |
109 | 81 | ||
110 | /* Public data */ | 82 | /* Public data */ |
111 | 83 | ||
112 | const struct clkops clkops_apll96 = { | 84 | const struct clkops clkops_apll96 = { |
113 | .enable = omap2_clk_apll96_enable, | 85 | .enable = _apll96_enable, |
114 | .disable = omap2_clk_apll_disable, | 86 | .disable = _apll96_disable, |
115 | .allow_idle = _apll96_allow_idle, | 87 | .allow_idle = _apll96_allow_idle, |
116 | .deny_idle = _apll96_deny_idle, | 88 | .deny_idle = _apll96_deny_idle, |
117 | }; | 89 | }; |
118 | 90 | ||
119 | const struct clkops clkops_apll54 = { | 91 | const struct clkops clkops_apll54 = { |
120 | .enable = omap2_clk_apll54_enable, | 92 | .enable = _apll54_enable, |
121 | .disable = omap2_clk_apll_disable, | 93 | .disable = _apll54_disable, |
122 | .allow_idle = _apll54_allow_idle, | 94 | .allow_idle = _apll54_allow_idle, |
123 | .deny_idle = _apll54_deny_idle, | 95 | .deny_idle = _apll54_deny_idle, |
124 | }; | 96 | }; |