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Diffstat (limited to 'arch/arm/mach-omap2/cclock33xx_data.c')
-rw-r--r--arch/arm/mach-omap2/cclock33xx_data.c181
1 files changed, 94 insertions, 87 deletions
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 476b82066cb6..6ebc7803bc3e 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -413,6 +413,14 @@ static struct clk smartreflex1_fck;
413DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL); 413DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
414DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null); 414DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
415 415
416static struct clk sha0_fck;
417DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
418DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
419
420static struct clk aes0_fck;
421DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
422DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
423
416/* 424/*
417 * Modules clock nodes 425 * Modules clock nodes
418 * 426 *
@@ -838,80 +846,82 @@ DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
838 * clkdev 846 * clkdev
839 */ 847 */
840static struct omap_clk am33xx_clks[] = { 848static struct omap_clk am33xx_clks[] = {
841 CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX), 849 CLK(NULL, "clk_32768_ck", &clk_32768_ck),
842 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX), 850 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck),
843 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX), 851 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
844 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX), 852 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck),
845 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX), 853 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck),
846 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX), 854 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
847 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX), 855 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
848 CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX), 856 CLK(NULL, "tclkin_ck", &tclkin_ck),
849 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX), 857 CLK(NULL, "dpll_core_ck", &dpll_core_ck),
850 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX), 858 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
851 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX), 859 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck),
852 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), 860 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck),
853 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), 861 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck),
854 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), 862 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
855 CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX), 863 CLK("cpu0", NULL, &dpll_mpu_ck),
856 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), 864 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
857 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), 865 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck),
858 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), 866 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck),
859 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX), 867 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck),
860 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX), 868 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck),
861 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX), 869 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck),
862 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX), 870 CLK(NULL, "dpll_per_ck", &dpll_per_ck),
863 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX), 871 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
864 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX), 872 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck),
865 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX), 873 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck),
866 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX), 874 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck),
867 CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX), 875 CLK(NULL, "cefuse_fck", &cefuse_fck),
868 CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck, CK_AM33XX), 876 CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck),
869 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX), 877 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick),
870 CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX), 878 CLK(NULL, "dcan0_fck", &dcan0_fck),
871 CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX), 879 CLK("481cc000.d_can", NULL, &dcan0_fck),
872 CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX), 880 CLK(NULL, "dcan1_fck", &dcan1_fck),
873 CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX), 881 CLK("481d0000.d_can", NULL, &dcan1_fck),
874 CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX), 882 CLK(NULL, "debugss_ick", &debugss_ick),
875 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX), 883 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk),
876 CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX), 884 CLK(NULL, "mcasp0_fck", &mcasp0_fck),
877 CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX), 885 CLK(NULL, "mcasp1_fck", &mcasp1_fck),
878 CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX), 886 CLK(NULL, "mmu_fck", &mmu_fck),
879 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX), 887 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
880 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX), 888 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
881 CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX), 889 CLK(NULL, "sha0_fck", &sha0_fck),
882 CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX), 890 CLK(NULL, "aes0_fck", &aes0_fck),
883 CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX), 891 CLK(NULL, "timer1_fck", &timer1_fck),
884 CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX), 892 CLK(NULL, "timer2_fck", &timer2_fck),
885 CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX), 893 CLK(NULL, "timer3_fck", &timer3_fck),
886 CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX), 894 CLK(NULL, "timer4_fck", &timer4_fck),
887 CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX), 895 CLK(NULL, "timer5_fck", &timer5_fck),
888 CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX), 896 CLK(NULL, "timer6_fck", &timer6_fck),
889 CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX), 897 CLK(NULL, "timer7_fck", &timer7_fck),
890 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX), 898 CLK(NULL, "usbotg_fck", &usbotg_fck),
891 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX), 899 CLK(NULL, "ieee5000_fck", &ieee5000_fck),
892 CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX), 900 CLK(NULL, "wdt1_fck", &wdt1_fck),
893 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX), 901 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk),
894 CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX), 902 CLK(NULL, "l3_gclk", &l3_gclk),
895 CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX), 903 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
896 CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX), 904 CLK(NULL, "l4hs_gclk", &l4hs_gclk),
897 CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX), 905 CLK(NULL, "l3s_gclk", &l3s_gclk),
898 CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX), 906 CLK(NULL, "l4fw_gclk", &l4fw_gclk),
899 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX), 907 CLK(NULL, "l4ls_gclk", &l4ls_gclk),
900 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX), 908 CLK(NULL, "clk_24mhz", &clk_24mhz),
901 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX), 909 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck),
902 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX), 910 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk),
903 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX), 911 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk),
904 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX), 912 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck),
905 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX), 913 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk),
906 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX), 914 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
907 CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX), 915 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
908 CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX), 916 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
909 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX), 917 CLK(NULL, "lcd_gclk", &lcd_gclk),
910 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX), 918 CLK(NULL, "mmc_clk", &mmc_clk),
911 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX), 919 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck),
912 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX), 920 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck),
913 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX), 921 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck),
914 CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX), 922 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
923 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
924 CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
915}; 925};
916 926
917 927
@@ -926,21 +936,10 @@ static const char *enable_init_clks[] = {
926 936
927int __init am33xx_clk_init(void) 937int __init am33xx_clk_init(void)
928{ 938{
929 struct omap_clk *c; 939 if (soc_is_am33xx())
930 u32 cpu_clkflg;
931
932 if (soc_is_am33xx()) {
933 cpu_mask = RATE_IN_AM33XX; 940 cpu_mask = RATE_IN_AM33XX;
934 cpu_clkflg = CK_AM33XX;
935 }
936 941
937 for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) { 942 omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
938 if (c->cpu & cpu_clkflg) {
939 clkdev_add(&c->lk);
940 if (!__clk_init(NULL, c->lk.clk))
941 omap2_init_clk_hw_omap_clocks(c->lk.clk);
942 }
943 }
944 943
945 omap2_clk_disable_autoidle_all(); 944 omap2_clk_disable_autoidle_all();
946 945
@@ -958,6 +957,14 @@ int __init am33xx_clk_init(void)
958 957
959 clk_set_parent(&timer3_fck, &sys_clkin_ck); 958 clk_set_parent(&timer3_fck, &sys_clkin_ck);
960 clk_set_parent(&timer6_fck, &sys_clkin_ck); 959 clk_set_parent(&timer6_fck, &sys_clkin_ck);
960 /*
961 * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
962 * the design/spec, so as a result, for example, timer which supposed
963 * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
964 * not expected by any use-case, so change WDT1 clock source to PRCM
965 * 32KHz clock.
966 */
967 clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
961 968
962 return 0; 969 return 0;
963} 970}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 13:09:38 -0500