1 files changed, 54 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 0c6be6b4a7e2..8ba8fb5b2514 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -28,6 +28,7 @@
 #include <plat/control.h>
 #include <plat/timer-gp.h>
 #include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
 
 static struct platform_device sdp4430_lcd_device = {
         .name           = "sdp4430_lcd",
@@ -50,6 +51,59 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
         { OMAP_TAG_LCD,         &sdp4430_lcd_config },
 };
 
+#ifdef CONFIG_CACHE_L2X0
+noinline void omap_smc1(u32 fn, u32 arg)
+{
+        register u32 r12 asm("r12") = fn;
+        register u32 r0 asm("r0") = arg;
+
+        /* This is common routine cache secure monitor API used to
+         * modify the PL310 secure registers.
+         * r0 contains the value to be modified and "r12" contains
+         * the monitor API number. It uses few CPU registers
+         * internally and hence they need be backed up including
+         * link register "lr".
+         * Explicitly save r11 and r12 the compiler generated code
+         * won't save it.
+         */
+        asm volatile(
+                "stmfd r13!, {r11,r12}\n"
+                "dsb\n"
+                "smc\n"
+                "ldmfd r13!, {r11,r12}\n"
+                : "+r" (r0), "+r" (r12)
+                :
+                : "r4", "r5", "r10", "lr", "cc");
+}
+EXPORT_SYMBOL(omap_smc1);
+
+static int __init omap_l2_cache_init(void)
+{
+        void __iomem *l2cache_base;
+
+        /* To avoid code running on other OMAPs in
+         * multi-omap builds
+         */
+        if (!cpu_is_omap44xx())
+                return -ENODEV;
+
+        /* Static mapping, never released */
+        l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
+        BUG_ON(!l2cache_base);
+
+        /* Enable PL310 L2 Cache controller */
+        omap_smc1(0x102, 0x1);
+
+        /* 32KB way size, 16-way associativity,
+        * parity disabled
+        */
+        l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
+
+        return 0;
+}
+early_initcall(omap_l2_cache_init);
+#endif
+
 static void __init gic_init_irq(void)
 {
         void __iomem *base;