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-rw-r--r--arch/arm/mach-omap1/devices.c2
-rw-r--r--arch/arm/mach-omap1/pm.h4
-rw-r--r--arch/arm/mach-omap1/serial.c6
-rw-r--r--arch/arm/mach-omap1/sram.S12
-rw-r--r--arch/arm/mach-omap1/time.c4
5 files changed, 14 insertions, 14 deletions
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index bbbaeb0abcd3..06808434ea04 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -71,7 +71,7 @@ static inline void omap_init_rtc(void) {}
71# define INT_DSP_MAILBOX1 INT_1610_DSP_MAILBOX1 71# define INT_DSP_MAILBOX1 INT_1610_DSP_MAILBOX1
72#endif 72#endif
73 73
74#define OMAP1_MBOX_BASE IO_ADDRESS(OMAP16XX_MAILBOX_BASE) 74#define OMAP1_MBOX_BASE OMAP1_IO_ADDRESS(OMAP16XX_MAILBOX_BASE)
75 75
76static struct resource mbox_resources[] = { 76static struct resource mbox_resources[] = {
77 { 77 {
diff --git a/arch/arm/mach-omap1/pm.h b/arch/arm/mach-omap1/pm.h
index 9ed5e2c1de4d..c4f05bdcf8a6 100644
--- a/arch/arm/mach-omap1/pm.h
+++ b/arch/arm/mach-omap1/pm.h
@@ -39,11 +39,11 @@
39 * Register and offset definitions to be used in PM assembler code 39 * Register and offset definitions to be used in PM assembler code
40 * ---------------------------------------------------------------------------- 40 * ----------------------------------------------------------------------------
41 */ 41 */
42#define CLKGEN_REG_ASM_BASE IO_ADDRESS(0xfffece00) 42#define CLKGEN_REG_ASM_BASE OMAP1_IO_ADDRESS(0xfffece00)
43#define ARM_IDLECT1_ASM_OFFSET 0x04 43#define ARM_IDLECT1_ASM_OFFSET 0x04
44#define ARM_IDLECT2_ASM_OFFSET 0x08 44#define ARM_IDLECT2_ASM_OFFSET 0x08
45 45
46#define TCMIF_ASM_BASE IO_ADDRESS(0xfffecc00) 46#define TCMIF_ASM_BASE OMAP1_IO_ADDRESS(0xfffecc00)
47#define EMIFS_CONFIG_ASM_OFFSET 0x0c 47#define EMIFS_CONFIG_ASM_OFFSET 0x0c
48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20 48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
49 49
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index f754cee4f3c3..6f54b2c591cf 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -64,7 +64,7 @@ static void __init omap_serial_reset(struct plat_serial8250_port *p)
64 64
65static struct plat_serial8250_port serial_platform_data[] = { 65static struct plat_serial8250_port serial_platform_data[] = {
66 { 66 {
67 .membase = IO_ADDRESS(OMAP_UART1_BASE), 67 .membase = OMAP1_IO_ADDRESS(OMAP_UART1_BASE),
68 .mapbase = OMAP_UART1_BASE, 68 .mapbase = OMAP_UART1_BASE,
69 .irq = INT_UART1, 69 .irq = INT_UART1,
70 .flags = UPF_BOOT_AUTOCONF, 70 .flags = UPF_BOOT_AUTOCONF,
@@ -73,7 +73,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
73 .uartclk = OMAP16XX_BASE_BAUD * 16, 73 .uartclk = OMAP16XX_BASE_BAUD * 16,
74 }, 74 },
75 { 75 {
76 .membase = IO_ADDRESS(OMAP_UART2_BASE), 76 .membase = OMAP1_IO_ADDRESS(OMAP_UART2_BASE),
77 .mapbase = OMAP_UART2_BASE, 77 .mapbase = OMAP_UART2_BASE,
78 .irq = INT_UART2, 78 .irq = INT_UART2,
79 .flags = UPF_BOOT_AUTOCONF, 79 .flags = UPF_BOOT_AUTOCONF,
@@ -82,7 +82,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
82 .uartclk = OMAP16XX_BASE_BAUD * 16, 82 .uartclk = OMAP16XX_BASE_BAUD * 16,
83 }, 83 },
84 { 84 {
85 .membase = IO_ADDRESS(OMAP_UART3_BASE), 85 .membase = OMAP1_IO_ADDRESS(OMAP_UART3_BASE),
86 .mapbase = OMAP_UART3_BASE, 86 .mapbase = OMAP_UART3_BASE,
87 .irq = INT_UART3, 87 .irq = INT_UART3,
88 .flags = UPF_BOOT_AUTOCONF, 88 .flags = UPF_BOOT_AUTOCONF,
diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S
index 261cdc48228b..7724e520d07c 100644
--- a/arch/arm/mach-omap1/sram.S
+++ b/arch/arm/mach-omap1/sram.S
@@ -21,13 +21,13 @@
21ENTRY(omap1_sram_reprogram_clock) 21ENTRY(omap1_sram_reprogram_clock)
22 stmfd sp!, {r0 - r12, lr} @ save registers on stack 22 stmfd sp!, {r0 - r12, lr} @ save registers on stack
23 23
24 mov r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000 24 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
25 orr r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x00ff0000 25 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
26 orr r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x0000ff00 26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
27 27
28 mov r3, #IO_ADDRESS(ARM_CKCTL) & 0xff000000 28 mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
29 orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x00ff0000 29 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
30 orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x0000ff00 30 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
31 31
32 tst r0, #1 << 4 @ want lock mode? 32 tst r0, #1 << 4 @ want lock mode?
33 beq newck @ nope 33 beq newck @ nope
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 4d56408d3cff..1be6a214d88d 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -62,8 +62,8 @@ typedef struct {
62 u32 read_tim; /* READ_TIM, R */ 62 u32 read_tim; /* READ_TIM, R */
63} omap_mpu_timer_regs_t; 63} omap_mpu_timer_regs_t;
64 64
65#define omap_mpu_timer_base(n) \ 65#define omap_mpu_timer_base(n) \
66((volatile omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ 66((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
67 (n)*OMAP_MPU_TIMER_OFFSET)) 67 (n)*OMAP_MPU_TIMER_OFFSET))
68 68
69static inline unsigned long omap_mpu_timer_read(int nr) 69static inline unsigned long omap_mpu_timer_read(int nr)