1 files changed, 22 insertions, 47 deletions

diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 6885d2fac183..03e1e1062ad4 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -68,49 +68,50 @@ typedef struct {
 } omap_mpu_timer_regs_t;
 
 #define omap_mpu_timer_base(n)                                                  \
-((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE +        \
+((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE +        \
                                  (n)*OMAP_MPU_TIMER_OFFSET))
 
 static inline unsigned long notrace omap_mpu_timer_read(int nr)
 {
-        volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
-        return timer->read_tim;
+        omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
+        return readl(&timer->read_tim);
 }
 
 static inline void omap_mpu_set_autoreset(int nr)
 {
-        volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
+        omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
 
-        timer->cntl = timer->cntl | MPU_TIMER_AR;
+        writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl);
 }
 
 static inline void omap_mpu_remove_autoreset(int nr)
 {
-        volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
+        omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
 
-        timer->cntl = timer->cntl & ~MPU_TIMER_AR;
+        writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl);
 }
 
 static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
                                         int autoreset)
 {
-        volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
-        unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST);
+        omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
+        unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST;
 
-        if (autoreset) timerflags |= MPU_TIMER_AR;
+        if (autoreset)
+                timerflags |= MPU_TIMER_AR;
 
-        timer->cntl = MPU_TIMER_CLOCK_ENABLE;
+        writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl);
         udelay(1);
-        timer->load_tim = load_val;
+        writel(load_val, &timer->load_tim);
         udelay(1);
-        timer->cntl = timerflags;
+        writel(timerflags, &timer->cntl);
 }
 
 static inline void omap_mpu_timer_stop(int nr)
 {
-        volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
+        omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
 
-        timer->cntl &= ~MPU_TIMER_ST;
+        writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl);
 }
 
 /*
@@ -189,38 +190,11 @@ static __init void omap_init_mpu_timer(unsigned long rate)
  * ---------------------------------------------------------------------------
  */
 
-static unsigned long omap_mpu_timer2_overflows;
-
-static irqreturn_t omap_mpu_timer2_interrupt(int irq, void *dev_id)
-{
-        omap_mpu_timer2_overflows++;
-        return IRQ_HANDLED;
-}
-
-static struct irqaction omap_mpu_timer2_irq = {
-        .name           = "mpu_timer2",
-        .flags          = IRQF_DISABLED,
-        .handler        = omap_mpu_timer2_interrupt,
-};
-
-static cycle_t mpu_read(struct clocksource *cs)
-{
-        return ~omap_mpu_timer_read(1);
-}
-
-static struct clocksource clocksource_mpu = {
-        .name           = "mpu_timer2",
-        .rating         = 300,
-        .read           = mpu_read,
-        .mask           = CLOCKSOURCE_MASK(32),
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
 static DEFINE_CLOCK_DATA(cd);
 
 static inline unsigned long long notrace _omap_mpu_sched_clock(void)
 {
-        u32 cyc = mpu_read(&clocksource_mpu);
+        u32 cyc = ~omap_mpu_timer_read(1);
         return cyc_to_sched_clock(&cd, cyc, (u32)~0);
 }
 
@@ -238,21 +212,22 @@ static unsigned long long notrace omap_mpu_sched_clock(void)
 
 static void notrace mpu_update_sched_clock(void)
 {
-        u32 cyc = mpu_read(&clocksource_mpu);
+        u32 cyc = ~omap_mpu_timer_read(1);
         update_sched_clock(&cd, cyc, (u32)~0);
 }
 
 static void __init omap_init_clocksource(unsigned long rate)
 {
+        omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1);
         static char err[] __initdata = KERN_ERR
                         "%s: can't register clocksource!\n";
 
-        setup_irq(INT_TIMER2, &omap_mpu_timer2_irq);
         omap_mpu_timer_start(1, ~0, 1);
         init_sched_clock(&cd, mpu_update_sched_clock, 32, rate);
 
-        if (clocksource_register_hz(&clocksource_mpu, rate))
-                printk(err, clocksource_mpu.name);
+        if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate,
+                        300, 32, clocksource_mmio_readl_down))
+                printk(err, "mpu_timer2");
 }
 
 static void __init omap_mpu_timer_init(void)