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-rw-r--r--arch/arm/mach-omap1/sleep.S161
1 files changed, 0 insertions, 161 deletions
diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S
index abef33d10f01..68f5b39030b6 100644
--- a/arch/arm/mach-omap1/sleep.S
+++ b/arch/arm/mach-omap1/sleep.S
@@ -39,167 +39,6 @@
39 39
40 .text 40 .text
41 41
42/*
43 * Forces OMAP into idle state
44 *
45 * omapXXXX_idle_loop_suspend()
46 *
47 * Note: This code get's copied to internal SRAM at boot. When the OMAP
48 * wakes up it continues execution at the point it went to sleep.
49 *
50 * Note: Because of slightly different configuration values we have
51 * processor specific functions here.
52 */
53
54#if defined(CONFIG_ARCH_OMAP730)
55ENTRY(omap730_idle_loop_suspend)
56
57 stmfd sp!, {r0 - r12, lr} @ save registers on stack
58
59 @ load base address of ARM_IDLECT1 and ARM_IDLECT2
60 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
61 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
62 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
63
64 @ turn off clock domains
65 @ get ARM_IDLECT2 into r2
66 ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
67 mov r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff
68 orr r5, r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff00
69 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
70
71 @ request ARM idle
72 @ get ARM_IDLECT1 into r1
73 ldrh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
74 orr r3, r1, #OMAP730_IDLE_LOOP_REQUEST & 0xffff
75 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
76
77 mov r5, #IDLE_WAIT_CYCLES & 0xff
78 orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
79l_730: subs r5, r5, #1
80 bne l_730
81/*
82 * Let's wait for the next clock tick to wake us up.
83 */
84 mov r0, #0
85 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
86/*
87 * omap730_idle_loop_suspend()'s resume point.
88 *
89 * It will just start executing here, so we'll restore stuff from the
90 * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
91 */
92
93 @ restore ARM_IDLECT1 and ARM_IDLECT2 and return
94 @ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
95 strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
96 strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
97
98 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
99
100ENTRY(omap730_idle_loop_suspend_sz)
101 .word . - omap730_idle_loop_suspend
102#endif /* CONFIG_ARCH_OMAP730 */
103
104#ifdef CONFIG_ARCH_OMAP15XX
105ENTRY(omap1510_idle_loop_suspend)
106
107 stmfd sp!, {r0 - r12, lr} @ save registers on stack
108
109 @ load base address of ARM_IDLECT1 and ARM_IDLECT2
110 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
111 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
112 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
113
114 @ turn off clock domains
115 @ get ARM_IDLECT2 into r2
116 ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
117 mov r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
118 orr r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
119 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
120
121 @ request ARM idle
122 @ get ARM_IDLECT1 into r1
123 ldrh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
124 orr r3, r1, #OMAP1510_IDLE_LOOP_REQUEST & 0xffff
125 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
126
127 mov r5, #IDLE_WAIT_CYCLES & 0xff
128 orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
129l_1510: subs r5, r5, #1
130 bne l_1510
131/*
132 * Let's wait for the next clock tick to wake us up.
133 */
134 mov r0, #0
135 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
136/*
137 * omap1510_idle_loop_suspend()'s resume point.
138 *
139 * It will just start executing here, so we'll restore stuff from the
140 * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
141 */
142
143 @ restore ARM_IDLECT1 and ARM_IDLECT2 and return
144 @ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
145 strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
146 strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
147
148 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
149
150ENTRY(omap1510_idle_loop_suspend_sz)
151 .word . - omap1510_idle_loop_suspend
152#endif /* CONFIG_ARCH_OMAP15XX */
153
154#if defined(CONFIG_ARCH_OMAP16XX)
155ENTRY(omap1610_idle_loop_suspend)
156
157 stmfd sp!, {r0 - r12, lr} @ save registers on stack
158
159 @ load base address of ARM_IDLECT1 and ARM_IDLECT2
160 mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
161 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
162 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
163
164 @ turn off clock domains
165 @ get ARM_IDLECT2 into r2
166 ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
167 mov r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff
168 orr r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00
169 strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
170
171 @ request ARM idle
172 @ get ARM_IDLECT1 into r1
173 ldrh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
174 orr r3, r1, #OMAP1610_IDLE_LOOP_REQUEST & 0xffff
175 strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
176
177 mov r5, #IDLE_WAIT_CYCLES & 0xff
178 orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
179l_1610: subs r5, r5, #1
180 bne l_1610
181/*
182 * Let's wait for the next clock tick to wake us up.
183 */
184 mov r0, #0
185 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
186/*
187 * omap1610_idle_loop_suspend()'s resume point.
188 *
189 * It will just start executing here, so we'll restore stuff from the
190 * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
191 */
192
193 @ restore ARM_IDLECT1 and ARM_IDLECT2 and return
194 @ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
195 strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
196 strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
197
198 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
199
200ENTRY(omap1610_idle_loop_suspend_sz)
201 .word . - omap1610_idle_loop_suspend
202#endif /* CONFIG_ARCH_OMAP16XX */
203 42
204/* 43/*
205 * Forces OMAP into deep sleep state 44 * Forces OMAP into deep sleep state
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