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Diffstat (limited to 'arch/arm/mach-omap1/mcbsp.c')
-rw-r--r--arch/arm/mach-omap1/mcbsp.c98
1 files changed, 10 insertions, 88 deletions
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index ca7a0cc1707c..575ba31295cf 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -28,81 +28,8 @@
28#define DPS_RSTCT2_PER_EN (1 << 0) 28#define DPS_RSTCT2_PER_EN (1 << 0)
29#define DSP_RSTCT2_WD_PER_EN (1 << 1) 29#define DSP_RSTCT2_WD_PER_EN (1 << 1)
30 30
31struct mcbsp_internal_clk {
32 struct clk clk;
33 struct clk **childs;
34 int n_childs;
35};
36
37#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) 31#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
38static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk) 32const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" };
39{
40 const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" };
41 int i;
42
43 mclk->n_childs = ARRAY_SIZE(clk_names);
44 mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
45 GFP_KERNEL);
46
47 for (i = 0; i < mclk->n_childs; i++) {
48 /* We fake a platform device to get correct device id */
49 struct platform_device pdev;
50
51 pdev.dev.bus = &platform_bus_type;
52 pdev.id = mclk->clk.id;
53 mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
54 if (IS_ERR(mclk->childs[i]))
55 printk(KERN_ERR "Could not get clock %s (%d).\n",
56 clk_names[i], mclk->clk.id);
57 }
58}
59
60static int omap_mcbsp_clk_enable(struct clk *clk)
61{
62 struct mcbsp_internal_clk *mclk = container_of(clk,
63 struct mcbsp_internal_clk, clk);
64 int i;
65
66 for (i = 0; i < mclk->n_childs; i++)
67 clk_enable(mclk->childs[i]);
68 return 0;
69}
70
71static void omap_mcbsp_clk_disable(struct clk *clk)
72{
73 struct mcbsp_internal_clk *mclk = container_of(clk,
74 struct mcbsp_internal_clk, clk);
75 int i;
76
77 for (i = 0; i < mclk->n_childs; i++)
78 clk_disable(mclk->childs[i]);
79}
80
81static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
82 {
83 .clk = {
84 .name = "mcbsp_clk",
85 .id = 1,
86 .enable = omap_mcbsp_clk_enable,
87 .disable = omap_mcbsp_clk_disable,
88 },
89 },
90 {
91 .clk = {
92 .name = "mcbsp_clk",
93 .id = 3,
94 .enable = omap_mcbsp_clk_enable,
95 .disable = omap_mcbsp_clk_disable,
96 },
97 },
98};
99
100#define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks)
101#else
102#define omap_mcbsp_clks_size 0
103static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
104static inline void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
105{ }
106#endif 33#endif
107 34
108static void omap1_mcbsp_request(unsigned int id) 35static void omap1_mcbsp_request(unsigned int id)
@@ -167,8 +94,9 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
167 .rx_irq = INT_McBSP1RX, 94 .rx_irq = INT_McBSP1RX,
168 .tx_irq = INT_McBSP1TX, 95 .tx_irq = INT_McBSP1TX,
169 .ops = &omap1_mcbsp_ops, 96 .ops = &omap1_mcbsp_ops,
170 .clk_name = "mcbsp_clk", 97 .clk_names = clk_names,
171 }, 98 .num_clks = 3,
99 },
172 { 100 {
173 .phys_base = OMAP1510_MCBSP2_BASE, 101 .phys_base = OMAP1510_MCBSP2_BASE,
174 .dma_rx_sync = OMAP_DMA_MCBSP2_RX, 102 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
@@ -184,7 +112,8 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
184 .rx_irq = INT_McBSP3RX, 112 .rx_irq = INT_McBSP3RX,
185 .tx_irq = INT_McBSP3TX, 113 .tx_irq = INT_McBSP3TX,
186 .ops = &omap1_mcbsp_ops, 114 .ops = &omap1_mcbsp_ops,
187 .clk_name = "mcbsp_clk", 115 .clk_names = clk_names,
116 .num_clks = 3,
188 }, 117 },
189}; 118};
190#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) 119#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata)
@@ -202,7 +131,8 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
202 .rx_irq = INT_McBSP1RX, 131 .rx_irq = INT_McBSP1RX,
203 .tx_irq = INT_McBSP1TX, 132 .tx_irq = INT_McBSP1TX,
204 .ops = &omap1_mcbsp_ops, 133 .ops = &omap1_mcbsp_ops,
205 .clk_name = "mcbsp_clk", 134 .clk_names = clk_names,
135 .num_clks = 3,
206 }, 136 },
207 { 137 {
208 .phys_base = OMAP1610_MCBSP2_BASE, 138 .phys_base = OMAP1610_MCBSP2_BASE,
@@ -219,7 +149,8 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
219 .rx_irq = INT_McBSP3RX, 149 .rx_irq = INT_McBSP3RX,
220 .tx_irq = INT_McBSP3TX, 150 .tx_irq = INT_McBSP3TX,
221 .ops = &omap1_mcbsp_ops, 151 .ops = &omap1_mcbsp_ops,
222 .clk_name = "mcbsp_clk", 152 .clk_names = clk_names,
153 .num_clks = 3,
223 }, 154 },
224}; 155};
225#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) 156#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata)
@@ -230,15 +161,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
230 161
231int __init omap1_mcbsp_init(void) 162int __init omap1_mcbsp_init(void)
232{ 163{
233 int i;
234
235 for (i = 0; i < omap_mcbsp_clks_size; i++) {
236 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
237 omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
238 clk_register(&omap_mcbsp_clks[i].clk);
239 }
240 }
241
242 if (cpu_is_omap730()) 164 if (cpu_is_omap730())
243 omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ; 165 omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ;
244 if (cpu_is_omap15xx()) 166 if (cpu_is_omap15xx())