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Diffstat (limited to 'arch/arm/mach-omap1/mcbsp.c')
-rw-r--r--arch/arm/mach-omap1/mcbsp.c333
1 files changed, 265 insertions, 68 deletions
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 820973666f34..d9af9811dedd 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -10,6 +10,7 @@
10 * 10 *
11 * Multichannel mode not supported. 11 * Multichannel mode not supported.
12 */ 12 */
13#include <linux/ioport.h>
13#include <linux/module.h> 14#include <linux/module.h>
14#include <linux/init.h> 15#include <linux/init.h>
15#include <linux/clk.h> 16#include <linux/clk.h>
@@ -78,100 +79,294 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
78}; 79};
79 80
80#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 81#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
82struct resource omap7xx_mcbsp_res[][6] = {
83 {
84 {
85 .start = OMAP7XX_MCBSP1_BASE,
86 .end = OMAP7XX_MCBSP1_BASE + SZ_256,
87 .flags = IORESOURCE_MEM,
88 },
89 {
90 .name = "rx",
91 .start = INT_7XX_McBSP1RX,
92 .flags = IORESOURCE_IRQ,
93 },
94 {
95 .name = "tx",
96 .start = INT_7XX_McBSP1TX,
97 .flags = IORESOURCE_IRQ,
98 },
99 {
100 .name = "rx",
101 .start = OMAP_DMA_MCBSP1_RX,
102 .flags = IORESOURCE_DMA,
103 },
104 {
105 .name = "tx",
106 .start = OMAP_DMA_MCBSP1_TX,
107 .flags = IORESOURCE_DMA,
108 },
109 },
110 {
111 {
112 .start = OMAP7XX_MCBSP2_BASE,
113 .end = OMAP7XX_MCBSP2_BASE + SZ_256,
114 .flags = IORESOURCE_MEM,
115 },
116 {
117 .name = "rx",
118 .start = INT_7XX_McBSP2RX,
119 .flags = IORESOURCE_IRQ,
120 },
121 {
122 .name = "tx",
123 .start = INT_7XX_McBSP2TX,
124 .flags = IORESOURCE_IRQ,
125 },
126 {
127 .name = "rx",
128 .start = OMAP_DMA_MCBSP3_RX,
129 .flags = IORESOURCE_DMA,
130 },
131 {
132 .name = "tx",
133 .start = OMAP_DMA_MCBSP3_TX,
134 .flags = IORESOURCE_DMA,
135 },
136 },
137};
138
139#define omap7xx_mcbsp_res_0 omap7xx_mcbsp_res[0]
140
81static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = { 141static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
82 { 142 {
83 .phys_base = OMAP7XX_MCBSP1_BASE,
84 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
85 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
86 .rx_irq = INT_7XX_McBSP1RX,
87 .tx_irq = INT_7XX_McBSP1TX,
88 .ops = &omap1_mcbsp_ops, 143 .ops = &omap1_mcbsp_ops,
89 }, 144 },
90 { 145 {
91 .phys_base = OMAP7XX_MCBSP2_BASE,
92 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
93 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
94 .rx_irq = INT_7XX_McBSP2RX,
95 .tx_irq = INT_7XX_McBSP2TX,
96 .ops = &omap1_mcbsp_ops, 146 .ops = &omap1_mcbsp_ops,
97 }, 147 },
98}; 148};
99#define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata) 149#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1])
100#define OMAP7XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) 150#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res)
101#else 151#else
152#define omap7xx_mcbsp_res_0 NULL
102#define omap7xx_mcbsp_pdata NULL 153#define omap7xx_mcbsp_pdata NULL
103#define OMAP7XX_MCBSP_PDATA_SZ 0 154#define OMAP7XX_MCBSP_RES_SZ 0
104#define OMAP7XX_MCBSP_REG_NUM 0 155#define OMAP7XX_MCBSP_COUNT 0
105#endif 156#endif
106 157
107#ifdef CONFIG_ARCH_OMAP15XX 158#ifdef CONFIG_ARCH_OMAP15XX
159struct resource omap15xx_mcbsp_res[][6] = {
160 {
161 {
162 .start = OMAP1510_MCBSP1_BASE,
163 .end = OMAP1510_MCBSP1_BASE + SZ_256,
164 .flags = IORESOURCE_MEM,
165 },
166 {
167 .name = "rx",
168 .start = INT_McBSP1RX,
169 .flags = IORESOURCE_IRQ,
170 },
171 {
172 .name = "tx",
173 .start = INT_McBSP1TX,
174 .flags = IORESOURCE_IRQ,
175 },
176 {
177 .name = "rx",
178 .start = OMAP_DMA_MCBSP1_RX,
179 .flags = IORESOURCE_DMA,
180 },
181 {
182 .name = "tx",
183 .start = OMAP_DMA_MCBSP1_TX,
184 .flags = IORESOURCE_DMA,
185 },
186 },
187 {
188 {
189 .start = OMAP1510_MCBSP2_BASE,
190 .end = OMAP1510_MCBSP2_BASE + SZ_256,
191 .flags = IORESOURCE_MEM,
192 },
193 {
194 .name = "rx",
195 .start = INT_1510_SPI_RX,
196 .flags = IORESOURCE_IRQ,
197 },
198 {
199 .name = "tx",
200 .start = INT_1510_SPI_TX,
201 .flags = IORESOURCE_IRQ,
202 },
203 {
204 .name = "rx",
205 .start = OMAP_DMA_MCBSP2_RX,
206 .flags = IORESOURCE_DMA,
207 },
208 {
209 .name = "tx",
210 .start = OMAP_DMA_MCBSP2_TX,
211 .flags = IORESOURCE_DMA,
212 },
213 },
214 {
215 {
216 .start = OMAP1510_MCBSP3_BASE,
217 .end = OMAP1510_MCBSP3_BASE + SZ_256,
218 .flags = IORESOURCE_MEM,
219 },
220 {
221 .name = "rx",
222 .start = INT_McBSP3RX,
223 .flags = IORESOURCE_IRQ,
224 },
225 {
226 .name = "tx",
227 .start = INT_McBSP3TX,
228 .flags = IORESOURCE_IRQ,
229 },
230 {
231 .name = "rx",
232 .start = OMAP_DMA_MCBSP3_RX,
233 .flags = IORESOURCE_DMA,
234 },
235 {
236 .name = "tx",
237 .start = OMAP_DMA_MCBSP3_TX,
238 .flags = IORESOURCE_DMA,
239 },
240 },
241};
242
243#define omap15xx_mcbsp_res_0 omap15xx_mcbsp_res[0]
244
108static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { 245static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
109 { 246 {
110 .phys_base = OMAP1510_MCBSP1_BASE,
111 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
112 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
113 .rx_irq = INT_McBSP1RX,
114 .tx_irq = INT_McBSP1TX,
115 .ops = &omap1_mcbsp_ops, 247 .ops = &omap1_mcbsp_ops,
116 }, 248 },
117 { 249 {
118 .phys_base = OMAP1510_MCBSP2_BASE,
119 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
120 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
121 .rx_irq = INT_1510_SPI_RX,
122 .tx_irq = INT_1510_SPI_TX,
123 .ops = &omap1_mcbsp_ops, 250 .ops = &omap1_mcbsp_ops,
124 }, 251 },
125 { 252 {
126 .phys_base = OMAP1510_MCBSP3_BASE,
127 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
128 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
129 .rx_irq = INT_McBSP3RX,
130 .tx_irq = INT_McBSP3TX,
131 .ops = &omap1_mcbsp_ops, 253 .ops = &omap1_mcbsp_ops,
132 }, 254 },
133}; 255};
134#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) 256#define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1])
135#define OMAP15XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) 257#define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res)
136#else 258#else
259#define omap15xx_mcbsp_res_0 NULL
137#define omap15xx_mcbsp_pdata NULL 260#define omap15xx_mcbsp_pdata NULL
138#define OMAP15XX_MCBSP_PDATA_SZ 0 261#define OMAP15XX_MCBSP_RES_SZ 0
139#define OMAP15XX_MCBSP_REG_NUM 0 262#define OMAP15XX_MCBSP_COUNT 0
140#endif 263#endif
141 264
142#ifdef CONFIG_ARCH_OMAP16XX 265#ifdef CONFIG_ARCH_OMAP16XX
266struct resource omap16xx_mcbsp_res[][6] = {
267 {
268 {
269 .start = OMAP1610_MCBSP1_BASE,
270 .end = OMAP1610_MCBSP1_BASE + SZ_256,
271 .flags = IORESOURCE_MEM,
272 },
273 {
274 .name = "rx",
275 .start = INT_McBSP1RX,
276 .flags = IORESOURCE_IRQ,
277 },
278 {
279 .name = "tx",
280 .start = INT_McBSP1TX,
281 .flags = IORESOURCE_IRQ,
282 },
283 {
284 .name = "rx",
285 .start = OMAP_DMA_MCBSP1_RX,
286 .flags = IORESOURCE_DMA,
287 },
288 {
289 .name = "tx",
290 .start = OMAP_DMA_MCBSP1_TX,
291 .flags = IORESOURCE_DMA,
292 },
293 },
294 {
295 {
296 .start = OMAP1610_MCBSP2_BASE,
297 .end = OMAP1610_MCBSP2_BASE + SZ_256,
298 .flags = IORESOURCE_MEM,
299 },
300 {
301 .name = "rx",
302 .start = INT_1610_McBSP2_RX,
303 .flags = IORESOURCE_IRQ,
304 },
305 {
306 .name = "tx",
307 .start = INT_1610_McBSP2_TX,
308 .flags = IORESOURCE_IRQ,
309 },
310 {
311 .name = "rx",
312 .start = OMAP_DMA_MCBSP2_RX,
313 .flags = IORESOURCE_DMA,
314 },
315 {
316 .name = "tx",
317 .start = OMAP_DMA_MCBSP2_TX,
318 .flags = IORESOURCE_DMA,
319 },
320 },
321 {
322 {
323 .start = OMAP1610_MCBSP3_BASE,
324 .end = OMAP1610_MCBSP3_BASE + SZ_256,
325 .flags = IORESOURCE_MEM,
326 },
327 {
328 .name = "rx",
329 .start = INT_McBSP3RX,
330 .flags = IORESOURCE_IRQ,
331 },
332 {
333 .name = "tx",
334 .start = INT_McBSP3TX,
335 .flags = IORESOURCE_IRQ,
336 },
337 {
338 .name = "rx",
339 .start = OMAP_DMA_MCBSP3_RX,
340 .flags = IORESOURCE_DMA,
341 },
342 {
343 .name = "tx",
344 .start = OMAP_DMA_MCBSP3_TX,
345 .flags = IORESOURCE_DMA,
346 },
347 },
348};
349
350#define omap16xx_mcbsp_res_0 omap16xx_mcbsp_res[0]
351
143static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { 352static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
144 { 353 {
145 .phys_base = OMAP1610_MCBSP1_BASE,
146 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
147 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
148 .rx_irq = INT_McBSP1RX,
149 .tx_irq = INT_McBSP1TX,
150 .ops = &omap1_mcbsp_ops, 354 .ops = &omap1_mcbsp_ops,
151 }, 355 },
152 { 356 {
153 .phys_base = OMAP1610_MCBSP2_BASE,
154 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
155 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
156 .rx_irq = INT_1610_McBSP2_RX,
157 .tx_irq = INT_1610_McBSP2_TX,
158 .ops = &omap1_mcbsp_ops, 357 .ops = &omap1_mcbsp_ops,
159 }, 358 },
160 { 359 {
161 .phys_base = OMAP1610_MCBSP3_BASE,
162 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
163 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
164 .rx_irq = INT_McBSP3RX,
165 .tx_irq = INT_McBSP3TX,
166 .ops = &omap1_mcbsp_ops, 360 .ops = &omap1_mcbsp_ops,
167 }, 361 },
168}; 362};
169#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) 363#define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1])
170#define OMAP16XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) 364#define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res)
171#else 365#else
366#define omap16xx_mcbsp_res_0 NULL
172#define omap16xx_mcbsp_pdata NULL 367#define omap16xx_mcbsp_pdata NULL
173#define OMAP16XX_MCBSP_PDATA_SZ 0 368#define OMAP16XX_MCBSP_RES_SZ 0
174#define OMAP16XX_MCBSP_REG_NUM 0 369#define OMAP16XX_MCBSP_COUNT 0
175#endif 370#endif
176 371
177static int __init omap1_mcbsp_init(void) 372static int __init omap1_mcbsp_init(void)
@@ -179,16 +374,12 @@ static int __init omap1_mcbsp_init(void)
179 if (!cpu_class_is_omap1()) 374 if (!cpu_class_is_omap1())
180 return -ENODEV; 375 return -ENODEV;
181 376
182 if (cpu_is_omap7xx()) { 377 if (cpu_is_omap7xx())
183 omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; 378 omap_mcbsp_count = OMAP7XX_MCBSP_COUNT;
184 omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16); 379 else if (cpu_is_omap15xx())
185 } else if (cpu_is_omap15xx()) { 380 omap_mcbsp_count = OMAP15XX_MCBSP_COUNT;
186 omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; 381 else if (cpu_is_omap16xx())
187 omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16); 382 omap_mcbsp_count = OMAP16XX_MCBSP_COUNT;
188 } else if (cpu_is_omap16xx()) {
189 omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
190 omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16);
191 }
192 383
193 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), 384 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
194 GFP_KERNEL); 385 GFP_KERNEL);
@@ -196,16 +387,22 @@ static int __init omap1_mcbsp_init(void)
196 return -ENOMEM; 387 return -ENOMEM;
197 388
198 if (cpu_is_omap7xx()) 389 if (cpu_is_omap7xx())
199 omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata, 390 omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0,
200 OMAP7XX_MCBSP_PDATA_SZ); 391 OMAP7XX_MCBSP_RES_SZ,
392 omap7xx_mcbsp_pdata,
393 OMAP7XX_MCBSP_COUNT);
201 394
202 if (cpu_is_omap15xx()) 395 if (cpu_is_omap15xx())
203 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata, 396 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res_0,
204 OMAP15XX_MCBSP_PDATA_SZ); 397 OMAP15XX_MCBSP_RES_SZ,
398 omap15xx_mcbsp_pdata,
399 OMAP15XX_MCBSP_COUNT);
205 400
206 if (cpu_is_omap16xx()) 401 if (cpu_is_omap16xx())
207 omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata, 402 omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res_0,
208 OMAP16XX_MCBSP_PDATA_SZ); 403 OMAP16XX_MCBSP_RES_SZ,
404 omap16xx_mcbsp_pdata,
405 OMAP16XX_MCBSP_COUNT);
209 406
210 return omap_mcbsp_init(); 407 return omap_mcbsp_init();
211} 408}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 03:07:34 -0500