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Diffstat (limited to 'arch/arm/mach-omap1/irq.c')
-rw-r--r--arch/arm/mach-omap1/irq.c44
1 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 6bddbc869f4c..47701584df35 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -70,48 +70,48 @@ static inline void irq_bank_writel(unsigned long value, int bank, int offset)
70 omap_writel(value, irq_banks[bank].base_reg + offset); 70 omap_writel(value, irq_banks[bank].base_reg + offset);
71} 71}
72 72
73static void omap_ack_irq(unsigned int irq) 73static void omap_ack_irq(struct irq_data *d)
74{ 74{
75 if (irq > 31) 75 if (d->irq > 31)
76 omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET); 76 omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
77 77
78 omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET); 78 omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
79} 79}
80 80
81static void omap_mask_irq(unsigned int irq) 81static void omap_mask_irq(struct irq_data *d)
82{ 82{
83 int bank = IRQ_BANK(irq); 83 int bank = IRQ_BANK(d->irq);
84 u32 l; 84 u32 l;
85 85
86 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 86 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
87 l |= 1 << IRQ_BIT(irq); 87 l |= 1 << IRQ_BIT(d->irq);
88 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 88 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
89} 89}
90 90
91static void omap_unmask_irq(unsigned int irq) 91static void omap_unmask_irq(struct irq_data *d)
92{ 92{
93 int bank = IRQ_BANK(irq); 93 int bank = IRQ_BANK(d->irq);
94 u32 l; 94 u32 l;
95 95
96 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 96 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
97 l &= ~(1 << IRQ_BIT(irq)); 97 l &= ~(1 << IRQ_BIT(d->irq));
98 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); 98 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
99} 99}
100 100
101static void omap_mask_ack_irq(unsigned int irq) 101static void omap_mask_ack_irq(struct irq_data *d)
102{ 102{
103 omap_mask_irq(irq); 103 omap_mask_irq(d);
104 omap_ack_irq(irq); 104 omap_ack_irq(d);
105} 105}
106 106
107static int omap_wake_irq(unsigned int irq, unsigned int enable) 107static int omap_wake_irq(struct irq_data *d, unsigned int enable)
108{ 108{
109 int bank = IRQ_BANK(irq); 109 int bank = IRQ_BANK(d->irq);
110 110
111 if (enable) 111 if (enable)
112 irq_banks[bank].wake_enable |= IRQ_BIT(irq); 112 irq_banks[bank].wake_enable |= IRQ_BIT(d->irq);
113 else 113 else
114 irq_banks[bank].wake_enable &= ~IRQ_BIT(irq); 114 irq_banks[bank].wake_enable &= ~IRQ_BIT(d->irq);
115 115
116 return 0; 116 return 0;
117} 117}
@@ -168,10 +168,10 @@ static struct omap_irq_bank omap1610_irq_banks[] = {
168 168
169static struct irq_chip omap_irq_chip = { 169static struct irq_chip omap_irq_chip = {
170 .name = "MPU", 170 .name = "MPU",
171 .ack = omap_mask_ack_irq, 171 .irq_ack = omap_mask_ack_irq,
172 .mask = omap_mask_irq, 172 .irq_mask = omap_mask_irq,
173 .unmask = omap_unmask_irq, 173 .irq_unmask = omap_unmask_irq,
174 .set_wake = omap_wake_irq, 174 .irq_set_wake = omap_wake_irq,
175}; 175};
176 176
177void __init omap_init_irq(void) 177void __init omap_init_irq(void)
@@ -239,9 +239,9 @@ void __init omap_init_irq(void)
239 /* Unmask level 2 handler */ 239 /* Unmask level 2 handler */
240 240
241 if (cpu_is_omap7xx()) 241 if (cpu_is_omap7xx())
242 omap_unmask_irq(INT_7XX_IH2_IRQ); 242 omap_unmask_irq(irq_get_irq_data(INT_7XX_IH2_IRQ));
243 else if (cpu_is_omap15xx()) 243 else if (cpu_is_omap15xx())
244 omap_unmask_irq(INT_1510_IH2_IRQ); 244 omap_unmask_irq(irq_get_irq_data(INT_1510_IH2_IRQ));
245 else if (cpu_is_omap16xx()) 245 else if (cpu_is_omap16xx())
246 omap_unmask_irq(INT_1610_IH2_IRQ); 246 omap_unmask_irq(irq_get_irq_data(INT_1610_IH2_IRQ));
247} 247}