1 files changed, 90 insertions, 0 deletions

diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index e382b438c64e..77382d8b6b2f 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -22,6 +22,7 @@
 #include <mach/board.h>
 #include <mach/mux.h>
 #include <mach/gpio.h>
+#include <mach/mmc.h>
 
 /*-------------------------------------------------------------------------*/
 
@@ -99,6 +100,95 @@ static inline void omap_init_mbox(void)
 static inline void omap_init_mbox(void) { }
 #endif
 
+/*-------------------------------------------------------------------------*/
+
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+
+static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
+                        int controller_nr)
+{
+        if (controller_nr == 0) {
+                omap_cfg_reg(MMC_CMD);
+                omap_cfg_reg(MMC_CLK);
+                omap_cfg_reg(MMC_DAT0);
+                if (cpu_is_omap1710()) {
+                        omap_cfg_reg(M15_1710_MMC_CLKI);
+                        omap_cfg_reg(P19_1710_MMC_CMDDIR);
+                        omap_cfg_reg(P20_1710_MMC_DATDIR0);
+                }
+                if (mmc_controller->slots[0].wires == 4) {
+                        omap_cfg_reg(MMC_DAT1);
+                        /* NOTE: DAT2 can be on W10 (here) or M15 */
+                        if (!mmc_controller->slots[0].nomux)
+                                omap_cfg_reg(MMC_DAT2);
+                        omap_cfg_reg(MMC_DAT3);
+                }
+        }
+
+        /* Block 2 is on newer chips, and has many pinout options */
+        if (cpu_is_omap16xx() && controller_nr == 1) {
+                if (!mmc_controller->slots[1].nomux) {
+                        omap_cfg_reg(Y8_1610_MMC2_CMD);
+                        omap_cfg_reg(Y10_1610_MMC2_CLK);
+                        omap_cfg_reg(R18_1610_MMC2_CLKIN);
+                        omap_cfg_reg(W8_1610_MMC2_DAT0);
+                        if (mmc_controller->slots[1].wires == 4) {
+                                omap_cfg_reg(V8_1610_MMC2_DAT1);
+                                omap_cfg_reg(W15_1610_MMC2_DAT2);
+                                omap_cfg_reg(R10_1610_MMC2_DAT3);
+                        }
+
+                        /* These are needed for the level shifter */
+                        omap_cfg_reg(V9_1610_MMC2_CMDDIR);
+                        omap_cfg_reg(V5_1610_MMC2_DATDIR0);
+                        omap_cfg_reg(W19_1610_MMC2_DATDIR1);
+                }
+
+                /* Feedback clock must be set on OMAP-1710 MMC2 */
+                if (cpu_is_omap1710())
+                        omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
+                                        MOD_CONF_CTRL_1);
+        }
+}
+
+void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
+                        int nr_controllers)
+{
+        int i;
+
+        for (i = 0; i < nr_controllers; i++) {
+                unsigned long base, size;
+                unsigned int irq = 0;
+
+                if (!mmc_data[i])
+                        continue;
+
+                omap1_mmc_mux(mmc_data[i], i);
+
+                switch (i) {
+                case 0:
+                        base = OMAP1_MMC1_BASE;
+                        irq = INT_MMC;
+                        break;
+                case 1:
+                        if (!cpu_is_omap16xx())
+                                return;
+                        base = OMAP1_MMC2_BASE;
+                        irq = INT_1610_MMC2;
+                        break;
+                default:
+                        continue;
+                }
+                size = OMAP1_MMC_SIZE;
+
+                omap_mmc_add(i, base, size, irq, mmc_data[i]);
+        };
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+
 #if defined(CONFIG_OMAP_STI)
 
 #define OMAP1_STI_BASE          0xfffea000