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Diffstat (limited to 'arch/arm/mach-omap1/clock_data.c')
-rw-r--r--arch/arm/mach-omap1/clock_data.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index ff2d5248df23..9d1a42a5afd8 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -25,6 +25,7 @@
25#include <plat/clock.h> 25#include <plat/clock.h>
26#include <plat/cpu.h> 26#include <plat/cpu.h>
27#include <plat/clkdev_omap.h> 27#include <plat/clkdev_omap.h>
28#include <plat/sram.h> /* for omap_sram_reprogram_clock() */
28#include <plat/usb.h> /* for OTG_BASE */ 29#include <plat/usb.h> /* for OTG_BASE */
29 30
30#include "clock.h" 31#include "clock.h"
@@ -944,8 +945,10 @@ void __init omap1_clk_late_init(void)
944 /* Find the highest supported frequency and enable it */ 945 /* Find the highest supported frequency and enable it */
945 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { 946 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
946 pr_err("System frequencies not set, using default. Check your config.\n"); 947 pr_err("System frequencies not set, using default. Check your config.\n");
947 omap_writew(0x2290, DPLL_CTL); 948 /*
948 omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL); 949 * Reprogramming the DPLL is tricky, it must be done from SRAM.
950 */
951 omap_sram_reprogram_clock(0x2290, 0x0005);
949 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; 952 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
950 } 953 }
951 propagate_rate(&ck_dpll1); 954 propagate_rate(&ck_dpll1);