diff options
Diffstat (limited to 'arch/arm/mach-omap1/clock_data.c')
-rw-r--r-- | arch/arm/mach-omap1/clock_data.c | 25 |
1 files changed, 9 insertions, 16 deletions
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index cea91cdf624d..8b1d14d1e38e 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-omap1/clock_data.c | 2 | * linux/arch/arm/mach-omap1/clock_data.c |
3 | * | 3 | * |
4 | * Copyright (C) 2004 - 2005, 2009 Nokia corporation | 4 | * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | 6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc |
7 | * | 7 | * |
@@ -31,7 +31,6 @@ | |||
31 | static struct clk dummy_ck = { | 31 | static struct clk dummy_ck = { |
32 | .name = "dummy", | 32 | .name = "dummy", |
33 | .ops = &clkops_dummy, | 33 | .ops = &clkops_dummy, |
34 | .flags = RATE_FIXED, | ||
35 | }; | 34 | }; |
36 | 35 | ||
37 | static struct clk ck_ref = { | 36 | static struct clk ck_ref = { |
@@ -389,8 +388,7 @@ static struct uart_clk uart1_16xx = { | |||
389 | /* Direct from ULPD, no real parent */ | 388 | /* Direct from ULPD, no real parent */ |
390 | .parent = &armper_ck.clk, | 389 | .parent = &armper_ck.clk, |
391 | .rate = 48000000, | 390 | .rate = 48000000, |
392 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | 391 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
393 | CLOCK_NO_IDLE_PARENT, | ||
394 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 392 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
395 | .enable_bit = 29, | 393 | .enable_bit = 29, |
396 | }, | 394 | }, |
@@ -430,8 +428,7 @@ static struct uart_clk uart3_16xx = { | |||
430 | /* Direct from ULPD, no real parent */ | 428 | /* Direct from ULPD, no real parent */ |
431 | .parent = &armper_ck.clk, | 429 | .parent = &armper_ck.clk, |
432 | .rate = 48000000, | 430 | .rate = 48000000, |
433 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | 431 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
434 | CLOCK_NO_IDLE_PARENT, | ||
435 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 432 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
436 | .enable_bit = 31, | 433 | .enable_bit = 31, |
437 | }, | 434 | }, |
@@ -443,7 +440,7 @@ static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ | |||
443 | .ops = &clkops_generic, | 440 | .ops = &clkops_generic, |
444 | /* Direct from ULPD, no parent */ | 441 | /* Direct from ULPD, no parent */ |
445 | .rate = 6000000, | 442 | .rate = 6000000, |
446 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | 443 | .flags = ENABLE_REG_32BIT, |
447 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), | 444 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), |
448 | .enable_bit = USB_MCLK_EN_BIT, | 445 | .enable_bit = USB_MCLK_EN_BIT, |
449 | }; | 446 | }; |
@@ -453,7 +450,7 @@ static struct clk usb_hhc_ck1510 = { | |||
453 | .ops = &clkops_generic, | 450 | .ops = &clkops_generic, |
454 | /* Direct from ULPD, no parent */ | 451 | /* Direct from ULPD, no parent */ |
455 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ | 452 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ |
456 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | 453 | .flags = ENABLE_REG_32BIT, |
457 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 454 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
458 | .enable_bit = USB_HOST_HHC_UHOST_EN, | 455 | .enable_bit = USB_HOST_HHC_UHOST_EN, |
459 | }; | 456 | }; |
@@ -464,7 +461,7 @@ static struct clk usb_hhc_ck16xx = { | |||
464 | /* Direct from ULPD, no parent */ | 461 | /* Direct from ULPD, no parent */ |
465 | .rate = 48000000, | 462 | .rate = 48000000, |
466 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | 463 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ |
467 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | 464 | .flags = ENABLE_REG_32BIT, |
468 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ | 465 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ |
469 | .enable_bit = 8 /* UHOST_EN */, | 466 | .enable_bit = 8 /* UHOST_EN */, |
470 | }; | 467 | }; |
@@ -474,7 +471,6 @@ static struct clk usb_dc_ck = { | |||
474 | .ops = &clkops_generic, | 471 | .ops = &clkops_generic, |
475 | /* Direct from ULPD, no parent */ | 472 | /* Direct from ULPD, no parent */ |
476 | .rate = 48000000, | 473 | .rate = 48000000, |
477 | .flags = RATE_FIXED, | ||
478 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 474 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
479 | .enable_bit = 4, | 475 | .enable_bit = 4, |
480 | }; | 476 | }; |
@@ -484,7 +480,6 @@ static struct clk usb_dc_ck7xx = { | |||
484 | .ops = &clkops_generic, | 480 | .ops = &clkops_generic, |
485 | /* Direct from ULPD, no parent */ | 481 | /* Direct from ULPD, no parent */ |
486 | .rate = 48000000, | 482 | .rate = 48000000, |
487 | .flags = RATE_FIXED, | ||
488 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 483 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
489 | .enable_bit = 8, | 484 | .enable_bit = 8, |
490 | }; | 485 | }; |
@@ -494,7 +489,6 @@ static struct clk mclk_1510 = { | |||
494 | .ops = &clkops_generic, | 489 | .ops = &clkops_generic, |
495 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 490 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
496 | .rate = 12000000, | 491 | .rate = 12000000, |
497 | .flags = RATE_FIXED, | ||
498 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 492 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
499 | .enable_bit = 6, | 493 | .enable_bit = 6, |
500 | }; | 494 | }; |
@@ -515,7 +509,6 @@ static struct clk bclk_1510 = { | |||
515 | .ops = &clkops_generic, | 509 | .ops = &clkops_generic, |
516 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 510 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
517 | .rate = 12000000, | 511 | .rate = 12000000, |
518 | .flags = RATE_FIXED, | ||
519 | }; | 512 | }; |
520 | 513 | ||
521 | static struct clk bclk_16xx = { | 514 | static struct clk bclk_16xx = { |
@@ -535,7 +528,7 @@ static struct clk mmc1_ck = { | |||
535 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 528 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
536 | .parent = &armper_ck.clk, | 529 | .parent = &armper_ck.clk, |
537 | .rate = 48000000, | 530 | .rate = 48000000, |
538 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 531 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
539 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 532 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
540 | .enable_bit = 23, | 533 | .enable_bit = 23, |
541 | }; | 534 | }; |
@@ -546,7 +539,7 @@ static struct clk mmc2_ck = { | |||
546 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 539 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
547 | .parent = &armper_ck.clk, | 540 | .parent = &armper_ck.clk, |
548 | .rate = 48000000, | 541 | .rate = 48000000, |
549 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 542 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
550 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | 543 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
551 | .enable_bit = 20, | 544 | .enable_bit = 20, |
552 | }; | 545 | }; |
@@ -557,7 +550,7 @@ static struct clk mmc3_ck = { | |||
557 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 550 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
558 | .parent = &armper_ck.clk, | 551 | .parent = &armper_ck.clk, |
559 | .rate = 48000000, | 552 | .rate = 48000000, |
560 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 553 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
561 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | 554 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
562 | .enable_bit = 12, | 555 | .enable_bit = 12, |
563 | }; | 556 | }; |