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-rw-r--r--arch/arm/mach-omap1/clock.h412
1 files changed, 128 insertions, 284 deletions
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index c1dcdf18d8dd..17f874271255 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -13,27 +13,22 @@
13#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H 13#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
14#define __ARCH_ARM_MACH_OMAP1_CLOCK_H 14#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
15 15
16static int omap1_clk_enable_generic(struct clk * clk); 16static unsigned long omap1_ckctl_recalc(struct clk *clk);
17static void omap1_clk_disable_generic(struct clk * clk); 17static unsigned long omap1_watchdog_recalc(struct clk *clk);
18static void omap1_ckctl_recalc(struct clk * clk);
19static void omap1_watchdog_recalc(struct clk * clk);
20static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); 18static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
21static void omap1_sossi_recalc(struct clk *clk); 19static unsigned long omap1_sossi_recalc(struct clk *clk);
22static void omap1_ckctl_recalc_dsp_domain(struct clk * clk); 20static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
23static int omap1_clk_enable_dsp_domain(struct clk * clk);
24static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); 21static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
25static void omap1_clk_disable_dsp_domain(struct clk * clk);
26static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); 22static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
27static void omap1_uart_recalc(struct clk * clk); 23static unsigned long omap1_uart_recalc(struct clk *clk);
28static int omap1_clk_enable_uart_functional(struct clk * clk);
29static void omap1_clk_disable_uart_functional(struct clk * clk);
30static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); 24static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
31static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); 25static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
32static void omap1_init_ext_clk(struct clk * clk); 26static void omap1_init_ext_clk(struct clk * clk);
33static int omap1_select_table_rate(struct clk * clk, unsigned long rate); 27static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
34static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); 28static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
35static int omap1_clk_enable(struct clk *clk); 29
36static void omap1_clk_disable(struct clk *clk); 30static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
31static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
37 32
38struct mpu_rate { 33struct mpu_rate {
39 unsigned long rate; 34 unsigned long rate;
@@ -152,101 +147,84 @@ static struct mpu_rate rate_table[] = {
152 147
153static struct clk ck_ref = { 148static struct clk ck_ref = {
154 .name = "ck_ref", 149 .name = "ck_ref",
150 .ops = &clkops_null,
155 .rate = 12000000, 151 .rate = 12000000,
156 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
157 CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
158 .enable = &omap1_clk_enable_generic,
159 .disable = &omap1_clk_disable_generic,
160}; 152};
161 153
162static struct clk ck_dpll1 = { 154static struct clk ck_dpll1 = {
163 .name = "ck_dpll1", 155 .name = "ck_dpll1",
156 .ops = &clkops_null,
164 .parent = &ck_ref, 157 .parent = &ck_ref,
165 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
166 CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED,
167 .enable = &omap1_clk_enable_generic,
168 .disable = &omap1_clk_disable_generic,
169}; 158};
170 159
171static struct arm_idlect1_clk ck_dpll1out = { 160static struct arm_idlect1_clk ck_dpll1out = {
172 .clk = { 161 .clk = {
173 .name = "ck_dpll1out", 162 .name = "ck_dpll1out",
163 .ops = &clkops_generic,
174 .parent = &ck_dpll1, 164 .parent = &ck_dpll1,
175 .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL | 165 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
176 ENABLE_REG_32BIT | RATE_PROPAGATES, 166 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
177 .enable_reg = (void __iomem *)ARM_IDLECT2,
178 .enable_bit = EN_CKOUT_ARM, 167 .enable_bit = EN_CKOUT_ARM,
179 .recalc = &followparent_recalc, 168 .recalc = &followparent_recalc,
180 .enable = &omap1_clk_enable_generic,
181 .disable = &omap1_clk_disable_generic,
182 }, 169 },
183 .idlect_shift = 12, 170 .idlect_shift = 12,
184}; 171};
185 172
186static struct clk sossi_ck = { 173static struct clk sossi_ck = {
187 .name = "ck_sossi", 174 .name = "ck_sossi",
175 .ops = &clkops_generic,
188 .parent = &ck_dpll1out.clk, 176 .parent = &ck_dpll1out.clk,
189 .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT | 177 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
190 ENABLE_REG_32BIT, 178 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
191 .enable_reg = (void __iomem *)MOD_CONF_CTRL_1,
192 .enable_bit = 16, 179 .enable_bit = 16,
193 .recalc = &omap1_sossi_recalc, 180 .recalc = &omap1_sossi_recalc,
194 .set_rate = &omap1_set_sossi_rate, 181 .set_rate = &omap1_set_sossi_rate,
195 .enable = &omap1_clk_enable_generic,
196 .disable = &omap1_clk_disable_generic,
197}; 182};
198 183
199static struct clk arm_ck = { 184static struct clk arm_ck = {
200 .name = "arm_ck", 185 .name = "arm_ck",
186 .ops = &clkops_null,
201 .parent = &ck_dpll1, 187 .parent = &ck_dpll1,
202 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
203 CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES |
204 ALWAYS_ENABLED,
205 .rate_offset = CKCTL_ARMDIV_OFFSET, 188 .rate_offset = CKCTL_ARMDIV_OFFSET,
206 .recalc = &omap1_ckctl_recalc, 189 .recalc = &omap1_ckctl_recalc,
207 .enable = &omap1_clk_enable_generic, 190 .round_rate = omap1_clk_round_rate_ckctl_arm,
208 .disable = &omap1_clk_disable_generic, 191 .set_rate = omap1_clk_set_rate_ckctl_arm,
209}; 192};
210 193
211static struct arm_idlect1_clk armper_ck = { 194static struct arm_idlect1_clk armper_ck = {
212 .clk = { 195 .clk = {
213 .name = "armper_ck", 196 .name = "armper_ck",
197 .ops = &clkops_generic,
214 .parent = &ck_dpll1, 198 .parent = &ck_dpll1,
215 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 199 .flags = CLOCK_IDLE_CONTROL,
216 CLOCK_IN_OMAP310 | RATE_CKCTL | 200 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
217 CLOCK_IDLE_CONTROL,
218 .enable_reg = (void __iomem *)ARM_IDLECT2,
219 .enable_bit = EN_PERCK, 201 .enable_bit = EN_PERCK,
220 .rate_offset = CKCTL_PERDIV_OFFSET, 202 .rate_offset = CKCTL_PERDIV_OFFSET,
221 .recalc = &omap1_ckctl_recalc, 203 .recalc = &omap1_ckctl_recalc,
222 .enable = &omap1_clk_enable_generic, 204 .round_rate = omap1_clk_round_rate_ckctl_arm,
223 .disable = &omap1_clk_disable_generic, 205 .set_rate = omap1_clk_set_rate_ckctl_arm,
224 }, 206 },
225 .idlect_shift = 2, 207 .idlect_shift = 2,
226}; 208};
227 209
228static struct clk arm_gpio_ck = { 210static struct clk arm_gpio_ck = {
229 .name = "arm_gpio_ck", 211 .name = "arm_gpio_ck",
212 .ops = &clkops_generic,
230 .parent = &ck_dpll1, 213 .parent = &ck_dpll1,
231 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, 214 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
232 .enable_reg = (void __iomem *)ARM_IDLECT2,
233 .enable_bit = EN_GPIOCK, 215 .enable_bit = EN_GPIOCK,
234 .recalc = &followparent_recalc, 216 .recalc = &followparent_recalc,
235 .enable = &omap1_clk_enable_generic,
236 .disable = &omap1_clk_disable_generic,
237}; 217};
238 218
239static struct arm_idlect1_clk armxor_ck = { 219static struct arm_idlect1_clk armxor_ck = {
240 .clk = { 220 .clk = {
241 .name = "armxor_ck", 221 .name = "armxor_ck",
222 .ops = &clkops_generic,
242 .parent = &ck_ref, 223 .parent = &ck_ref,
243 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 224 .flags = CLOCK_IDLE_CONTROL,
244 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, 225 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
245 .enable_reg = (void __iomem *)ARM_IDLECT2,
246 .enable_bit = EN_XORPCK, 226 .enable_bit = EN_XORPCK,
247 .recalc = &followparent_recalc, 227 .recalc = &followparent_recalc,
248 .enable = &omap1_clk_enable_generic,
249 .disable = &omap1_clk_disable_generic,
250 }, 228 },
251 .idlect_shift = 1, 229 .idlect_shift = 1,
252}; 230};
@@ -254,14 +232,12 @@ static struct arm_idlect1_clk armxor_ck = {
254static struct arm_idlect1_clk armtim_ck = { 232static struct arm_idlect1_clk armtim_ck = {
255 .clk = { 233 .clk = {
256 .name = "armtim_ck", 234 .name = "armtim_ck",
235 .ops = &clkops_generic,
257 .parent = &ck_ref, 236 .parent = &ck_ref,
258 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 237 .flags = CLOCK_IDLE_CONTROL,
259 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, 238 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
260 .enable_reg = (void __iomem *)ARM_IDLECT2,
261 .enable_bit = EN_TIMCK, 239 .enable_bit = EN_TIMCK,
262 .recalc = &followparent_recalc, 240 .recalc = &followparent_recalc,
263 .enable = &omap1_clk_enable_generic,
264 .disable = &omap1_clk_disable_generic,
265 }, 241 },
266 .idlect_shift = 9, 242 .idlect_shift = 9,
267}; 243};
@@ -269,201 +245,166 @@ static struct arm_idlect1_clk armtim_ck = {
269static struct arm_idlect1_clk armwdt_ck = { 245static struct arm_idlect1_clk armwdt_ck = {
270 .clk = { 246 .clk = {
271 .name = "armwdt_ck", 247 .name = "armwdt_ck",
248 .ops = &clkops_generic,
272 .parent = &ck_ref, 249 .parent = &ck_ref,
273 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 250 .flags = CLOCK_IDLE_CONTROL,
274 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, 251 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
275 .enable_reg = (void __iomem *)ARM_IDLECT2,
276 .enable_bit = EN_WDTCK, 252 .enable_bit = EN_WDTCK,
277 .recalc = &omap1_watchdog_recalc, 253 .recalc = &omap1_watchdog_recalc,
278 .enable = &omap1_clk_enable_generic,
279 .disable = &omap1_clk_disable_generic,
280 }, 254 },
281 .idlect_shift = 0, 255 .idlect_shift = 0,
282}; 256};
283 257
284static struct clk arminth_ck16xx = { 258static struct clk arminth_ck16xx = {
285 .name = "arminth_ck", 259 .name = "arminth_ck",
260 .ops = &clkops_null,
286 .parent = &arm_ck, 261 .parent = &arm_ck,
287 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
288 .recalc = &followparent_recalc, 262 .recalc = &followparent_recalc,
289 /* Note: On 16xx the frequency can be divided by 2 by programming 263 /* Note: On 16xx the frequency can be divided by 2 by programming
290 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 264 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
291 * 265 *
292 * 1510 version is in TC clocks. 266 * 1510 version is in TC clocks.
293 */ 267 */
294 .enable = &omap1_clk_enable_generic,
295 .disable = &omap1_clk_disable_generic,
296}; 268};
297 269
298static struct clk dsp_ck = { 270static struct clk dsp_ck = {
299 .name = "dsp_ck", 271 .name = "dsp_ck",
272 .ops = &clkops_generic,
300 .parent = &ck_dpll1, 273 .parent = &ck_dpll1,
301 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 274 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
302 RATE_CKCTL,
303 .enable_reg = (void __iomem *)ARM_CKCTL,
304 .enable_bit = EN_DSPCK, 275 .enable_bit = EN_DSPCK,
305 .rate_offset = CKCTL_DSPDIV_OFFSET, 276 .rate_offset = CKCTL_DSPDIV_OFFSET,
306 .recalc = &omap1_ckctl_recalc, 277 .recalc = &omap1_ckctl_recalc,
307 .enable = &omap1_clk_enable_generic, 278 .round_rate = omap1_clk_round_rate_ckctl_arm,
308 .disable = &omap1_clk_disable_generic, 279 .set_rate = omap1_clk_set_rate_ckctl_arm,
309}; 280};
310 281
311static struct clk dspmmu_ck = { 282static struct clk dspmmu_ck = {
312 .name = "dspmmu_ck", 283 .name = "dspmmu_ck",
284 .ops = &clkops_null,
313 .parent = &ck_dpll1, 285 .parent = &ck_dpll1,
314 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
315 RATE_CKCTL | ALWAYS_ENABLED,
316 .rate_offset = CKCTL_DSPMMUDIV_OFFSET, 286 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
317 .recalc = &omap1_ckctl_recalc, 287 .recalc = &omap1_ckctl_recalc,
318 .enable = &omap1_clk_enable_generic, 288 .round_rate = omap1_clk_round_rate_ckctl_arm,
319 .disable = &omap1_clk_disable_generic, 289 .set_rate = omap1_clk_set_rate_ckctl_arm,
320}; 290};
321 291
322static struct clk dspper_ck = { 292static struct clk dspper_ck = {
323 .name = "dspper_ck", 293 .name = "dspper_ck",
294 .ops = &clkops_dspck,
324 .parent = &ck_dpll1, 295 .parent = &ck_dpll1,
325 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
326 RATE_CKCTL | VIRTUAL_IO_ADDRESS,
327 .enable_reg = DSP_IDLECT2, 296 .enable_reg = DSP_IDLECT2,
328 .enable_bit = EN_PERCK, 297 .enable_bit = EN_PERCK,
329 .rate_offset = CKCTL_PERDIV_OFFSET, 298 .rate_offset = CKCTL_PERDIV_OFFSET,
330 .recalc = &omap1_ckctl_recalc_dsp_domain, 299 .recalc = &omap1_ckctl_recalc_dsp_domain,
300 .round_rate = omap1_clk_round_rate_ckctl_arm,
331 .set_rate = &omap1_clk_set_rate_dsp_domain, 301 .set_rate = &omap1_clk_set_rate_dsp_domain,
332 .enable = &omap1_clk_enable_dsp_domain,
333 .disable = &omap1_clk_disable_dsp_domain,
334}; 302};
335 303
336static struct clk dspxor_ck = { 304static struct clk dspxor_ck = {
337 .name = "dspxor_ck", 305 .name = "dspxor_ck",
306 .ops = &clkops_dspck,
338 .parent = &ck_ref, 307 .parent = &ck_ref,
339 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
340 VIRTUAL_IO_ADDRESS,
341 .enable_reg = DSP_IDLECT2, 308 .enable_reg = DSP_IDLECT2,
342 .enable_bit = EN_XORPCK, 309 .enable_bit = EN_XORPCK,
343 .recalc = &followparent_recalc, 310 .recalc = &followparent_recalc,
344 .enable = &omap1_clk_enable_dsp_domain,
345 .disable = &omap1_clk_disable_dsp_domain,
346}; 311};
347 312
348static struct clk dsptim_ck = { 313static struct clk dsptim_ck = {
349 .name = "dsptim_ck", 314 .name = "dsptim_ck",
315 .ops = &clkops_dspck,
350 .parent = &ck_ref, 316 .parent = &ck_ref,
351 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
352 VIRTUAL_IO_ADDRESS,
353 .enable_reg = DSP_IDLECT2, 317 .enable_reg = DSP_IDLECT2,
354 .enable_bit = EN_DSPTIMCK, 318 .enable_bit = EN_DSPTIMCK,
355 .recalc = &followparent_recalc, 319 .recalc = &followparent_recalc,
356 .enable = &omap1_clk_enable_dsp_domain,
357 .disable = &omap1_clk_disable_dsp_domain,
358}; 320};
359 321
360/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ 322/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
361static struct arm_idlect1_clk tc_ck = { 323static struct arm_idlect1_clk tc_ck = {
362 .clk = { 324 .clk = {
363 .name = "tc_ck", 325 .name = "tc_ck",
326 .ops = &clkops_null,
364 .parent = &ck_dpll1, 327 .parent = &ck_dpll1,
365 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 328 .flags = CLOCK_IDLE_CONTROL,
366 CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
367 RATE_CKCTL | RATE_PROPAGATES |
368 ALWAYS_ENABLED | CLOCK_IDLE_CONTROL,
369 .rate_offset = CKCTL_TCDIV_OFFSET, 329 .rate_offset = CKCTL_TCDIV_OFFSET,
370 .recalc = &omap1_ckctl_recalc, 330 .recalc = &omap1_ckctl_recalc,
371 .enable = &omap1_clk_enable_generic, 331 .round_rate = omap1_clk_round_rate_ckctl_arm,
372 .disable = &omap1_clk_disable_generic, 332 .set_rate = omap1_clk_set_rate_ckctl_arm,
373 }, 333 },
374 .idlect_shift = 6, 334 .idlect_shift = 6,
375}; 335};
376 336
377static struct clk arminth_ck1510 = { 337static struct clk arminth_ck1510 = {
378 .name = "arminth_ck", 338 .name = "arminth_ck",
339 .ops = &clkops_null,
379 .parent = &tc_ck.clk, 340 .parent = &tc_ck.clk,
380 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
381 ALWAYS_ENABLED,
382 .recalc = &followparent_recalc, 341 .recalc = &followparent_recalc,
383 /* Note: On 1510 the frequency follows TC_CK 342 /* Note: On 1510 the frequency follows TC_CK
384 * 343 *
385 * 16xx version is in MPU clocks. 344 * 16xx version is in MPU clocks.
386 */ 345 */
387 .enable = &omap1_clk_enable_generic,
388 .disable = &omap1_clk_disable_generic,
389}; 346};
390 347
391static struct clk tipb_ck = { 348static struct clk tipb_ck = {
392 /* No-idle controlled by "tc_ck" */ 349 /* No-idle controlled by "tc_ck" */
393 .name = "tipb_ck", 350 .name = "tipb_ck",
351 .ops = &clkops_null,
394 .parent = &tc_ck.clk, 352 .parent = &tc_ck.clk,
395 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
396 ALWAYS_ENABLED,
397 .recalc = &followparent_recalc, 353 .recalc = &followparent_recalc,
398 .enable = &omap1_clk_enable_generic,
399 .disable = &omap1_clk_disable_generic,
400}; 354};
401 355
402static struct clk l3_ocpi_ck = { 356static struct clk l3_ocpi_ck = {
403 /* No-idle controlled by "tc_ck" */ 357 /* No-idle controlled by "tc_ck" */
404 .name = "l3_ocpi_ck", 358 .name = "l3_ocpi_ck",
359 .ops = &clkops_generic,
405 .parent = &tc_ck.clk, 360 .parent = &tc_ck.clk,
406 .flags = CLOCK_IN_OMAP16XX, 361 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
407 .enable_reg = (void __iomem *)ARM_IDLECT3,
408 .enable_bit = EN_OCPI_CK, 362 .enable_bit = EN_OCPI_CK,
409 .recalc = &followparent_recalc, 363 .recalc = &followparent_recalc,
410 .enable = &omap1_clk_enable_generic,
411 .disable = &omap1_clk_disable_generic,
412}; 364};
413 365
414static struct clk tc1_ck = { 366static struct clk tc1_ck = {
415 .name = "tc1_ck", 367 .name = "tc1_ck",
368 .ops = &clkops_generic,
416 .parent = &tc_ck.clk, 369 .parent = &tc_ck.clk,
417 .flags = CLOCK_IN_OMAP16XX, 370 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
418 .enable_reg = (void __iomem *)ARM_IDLECT3,
419 .enable_bit = EN_TC1_CK, 371 .enable_bit = EN_TC1_CK,
420 .recalc = &followparent_recalc, 372 .recalc = &followparent_recalc,
421 .enable = &omap1_clk_enable_generic,
422 .disable = &omap1_clk_disable_generic,
423}; 373};
424 374
425static struct clk tc2_ck = { 375static struct clk tc2_ck = {
426 .name = "tc2_ck", 376 .name = "tc2_ck",
377 .ops = &clkops_generic,
427 .parent = &tc_ck.clk, 378 .parent = &tc_ck.clk,
428 .flags = CLOCK_IN_OMAP16XX, 379 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
429 .enable_reg = (void __iomem *)ARM_IDLECT3,
430 .enable_bit = EN_TC2_CK, 380 .enable_bit = EN_TC2_CK,
431 .recalc = &followparent_recalc, 381 .recalc = &followparent_recalc,
432 .enable = &omap1_clk_enable_generic,
433 .disable = &omap1_clk_disable_generic,
434}; 382};
435 383
436static struct clk dma_ck = { 384static struct clk dma_ck = {
437 /* No-idle controlled by "tc_ck" */ 385 /* No-idle controlled by "tc_ck" */
438 .name = "dma_ck", 386 .name = "dma_ck",
387 .ops = &clkops_null,
439 .parent = &tc_ck.clk, 388 .parent = &tc_ck.clk,
440 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
441 CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
442 .recalc = &followparent_recalc, 389 .recalc = &followparent_recalc,
443 .enable = &omap1_clk_enable_generic,
444 .disable = &omap1_clk_disable_generic,
445}; 390};
446 391
447static struct clk dma_lcdfree_ck = { 392static struct clk dma_lcdfree_ck = {
448 .name = "dma_lcdfree_ck", 393 .name = "dma_lcdfree_ck",
394 .ops = &clkops_null,
449 .parent = &tc_ck.clk, 395 .parent = &tc_ck.clk,
450 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
451 .recalc = &followparent_recalc, 396 .recalc = &followparent_recalc,
452 .enable = &omap1_clk_enable_generic,
453 .disable = &omap1_clk_disable_generic,
454}; 397};
455 398
456static struct arm_idlect1_clk api_ck = { 399static struct arm_idlect1_clk api_ck = {
457 .clk = { 400 .clk = {
458 .name = "api_ck", 401 .name = "api_ck",
402 .ops = &clkops_generic,
459 .parent = &tc_ck.clk, 403 .parent = &tc_ck.clk,
460 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 404 .flags = CLOCK_IDLE_CONTROL,
461 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, 405 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
462 .enable_reg = (void __iomem *)ARM_IDLECT2,
463 .enable_bit = EN_APICK, 406 .enable_bit = EN_APICK,
464 .recalc = &followparent_recalc, 407 .recalc = &followparent_recalc,
465 .enable = &omap1_clk_enable_generic,
466 .disable = &omap1_clk_disable_generic,
467 }, 408 },
468 .idlect_shift = 8, 409 .idlect_shift = 8,
469}; 410};
@@ -471,276 +412,238 @@ static struct arm_idlect1_clk api_ck = {
471static struct arm_idlect1_clk lb_ck = { 412static struct arm_idlect1_clk lb_ck = {
472 .clk = { 413 .clk = {
473 .name = "lb_ck", 414 .name = "lb_ck",
415 .ops = &clkops_generic,
474 .parent = &tc_ck.clk, 416 .parent = &tc_ck.clk,
475 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 417 .flags = CLOCK_IDLE_CONTROL,
476 CLOCK_IDLE_CONTROL, 418 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
477 .enable_reg = (void __iomem *)ARM_IDLECT2,
478 .enable_bit = EN_LBCK, 419 .enable_bit = EN_LBCK,
479 .recalc = &followparent_recalc, 420 .recalc = &followparent_recalc,
480 .enable = &omap1_clk_enable_generic,
481 .disable = &omap1_clk_disable_generic,
482 }, 421 },
483 .idlect_shift = 4, 422 .idlect_shift = 4,
484}; 423};
485 424
486static struct clk rhea1_ck = { 425static struct clk rhea1_ck = {
487 .name = "rhea1_ck", 426 .name = "rhea1_ck",
427 .ops = &clkops_null,
488 .parent = &tc_ck.clk, 428 .parent = &tc_ck.clk,
489 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
490 .recalc = &followparent_recalc, 429 .recalc = &followparent_recalc,
491 .enable = &omap1_clk_enable_generic,
492 .disable = &omap1_clk_disable_generic,
493}; 430};
494 431
495static struct clk rhea2_ck = { 432static struct clk rhea2_ck = {
496 .name = "rhea2_ck", 433 .name = "rhea2_ck",
434 .ops = &clkops_null,
497 .parent = &tc_ck.clk, 435 .parent = &tc_ck.clk,
498 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
499 .recalc = &followparent_recalc, 436 .recalc = &followparent_recalc,
500 .enable = &omap1_clk_enable_generic,
501 .disable = &omap1_clk_disable_generic,
502}; 437};
503 438
504static struct clk lcd_ck_16xx = { 439static struct clk lcd_ck_16xx = {
505 .name = "lcd_ck", 440 .name = "lcd_ck",
441 .ops = &clkops_generic,
506 .parent = &ck_dpll1, 442 .parent = &ck_dpll1,
507 .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL, 443 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
508 .enable_reg = (void __iomem *)ARM_IDLECT2,
509 .enable_bit = EN_LCDCK, 444 .enable_bit = EN_LCDCK,
510 .rate_offset = CKCTL_LCDDIV_OFFSET, 445 .rate_offset = CKCTL_LCDDIV_OFFSET,
511 .recalc = &omap1_ckctl_recalc, 446 .recalc = &omap1_ckctl_recalc,
512 .enable = &omap1_clk_enable_generic, 447 .round_rate = omap1_clk_round_rate_ckctl_arm,
513 .disable = &omap1_clk_disable_generic, 448 .set_rate = omap1_clk_set_rate_ckctl_arm,
514}; 449};
515 450
516static struct arm_idlect1_clk lcd_ck_1510 = { 451static struct arm_idlect1_clk lcd_ck_1510 = {
517 .clk = { 452 .clk = {
518 .name = "lcd_ck", 453 .name = "lcd_ck",
454 .ops = &clkops_generic,
519 .parent = &ck_dpll1, 455 .parent = &ck_dpll1,
520 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 456 .flags = CLOCK_IDLE_CONTROL,
521 RATE_CKCTL | CLOCK_IDLE_CONTROL, 457 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
522 .enable_reg = (void __iomem *)ARM_IDLECT2,
523 .enable_bit = EN_LCDCK, 458 .enable_bit = EN_LCDCK,
524 .rate_offset = CKCTL_LCDDIV_OFFSET, 459 .rate_offset = CKCTL_LCDDIV_OFFSET,
525 .recalc = &omap1_ckctl_recalc, 460 .recalc = &omap1_ckctl_recalc,
526 .enable = &omap1_clk_enable_generic, 461 .round_rate = omap1_clk_round_rate_ckctl_arm,
527 .disable = &omap1_clk_disable_generic, 462 .set_rate = omap1_clk_set_rate_ckctl_arm,
528 }, 463 },
529 .idlect_shift = 3, 464 .idlect_shift = 3,
530}; 465};
531 466
532static struct clk uart1_1510 = { 467static struct clk uart1_1510 = {
533 .name = "uart1_ck", 468 .name = "uart1_ck",
469 .ops = &clkops_null,
534 /* Direct from ULPD, no real parent */ 470 /* Direct from ULPD, no real parent */
535 .parent = &armper_ck.clk, 471 .parent = &armper_ck.clk,
536 .rate = 12000000, 472 .rate = 12000000,
537 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 473 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
538 ENABLE_REG_32BIT | ALWAYS_ENABLED | 474 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
539 CLOCK_NO_IDLE_PARENT,
540 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
541 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ 475 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
542 .set_rate = &omap1_set_uart_rate, 476 .set_rate = &omap1_set_uart_rate,
543 .recalc = &omap1_uart_recalc, 477 .recalc = &omap1_uart_recalc,
544 .enable = &omap1_clk_enable_generic,
545 .disable = &omap1_clk_disable_generic,
546}; 478};
547 479
548static struct uart_clk uart1_16xx = { 480static struct uart_clk uart1_16xx = {
549 .clk = { 481 .clk = {
550 .name = "uart1_ck", 482 .name = "uart1_ck",
483 .ops = &clkops_uart,
551 /* Direct from ULPD, no real parent */ 484 /* Direct from ULPD, no real parent */
552 .parent = &armper_ck.clk, 485 .parent = &armper_ck.clk,
553 .rate = 48000000, 486 .rate = 48000000,
554 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | 487 .flags = RATE_FIXED | ENABLE_REG_32BIT |
555 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 488 CLOCK_NO_IDLE_PARENT,
556 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 489 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
557 .enable_bit = 29, 490 .enable_bit = 29,
558 .enable = &omap1_clk_enable_uart_functional,
559 .disable = &omap1_clk_disable_uart_functional,
560 }, 491 },
561 .sysc_addr = 0xfffb0054, 492 .sysc_addr = 0xfffb0054,
562}; 493};
563 494
564static struct clk uart2_ck = { 495static struct clk uart2_ck = {
565 .name = "uart2_ck", 496 .name = "uart2_ck",
497 .ops = &clkops_null,
566 /* Direct from ULPD, no real parent */ 498 /* Direct from ULPD, no real parent */
567 .parent = &armper_ck.clk, 499 .parent = &armper_ck.clk,
568 .rate = 12000000, 500 .rate = 12000000,
569 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 501 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
570 CLOCK_IN_OMAP310 | ENABLE_REG_32BIT | 502 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
571 ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
572 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
573 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ 503 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
574 .set_rate = &omap1_set_uart_rate, 504 .set_rate = &omap1_set_uart_rate,
575 .recalc = &omap1_uart_recalc, 505 .recalc = &omap1_uart_recalc,
576 .enable = &omap1_clk_enable_generic,
577 .disable = &omap1_clk_disable_generic,
578}; 506};
579 507
580static struct clk uart3_1510 = { 508static struct clk uart3_1510 = {
581 .name = "uart3_ck", 509 .name = "uart3_ck",
510 .ops = &clkops_null,
582 /* Direct from ULPD, no real parent */ 511 /* Direct from ULPD, no real parent */
583 .parent = &armper_ck.clk, 512 .parent = &armper_ck.clk,
584 .rate = 12000000, 513 .rate = 12000000,
585 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 514 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
586 ENABLE_REG_32BIT | ALWAYS_ENABLED | 515 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
587 CLOCK_NO_IDLE_PARENT,
588 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
589 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ 516 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
590 .set_rate = &omap1_set_uart_rate, 517 .set_rate = &omap1_set_uart_rate,
591 .recalc = &omap1_uart_recalc, 518 .recalc = &omap1_uart_recalc,
592 .enable = &omap1_clk_enable_generic,
593 .disable = &omap1_clk_disable_generic,
594}; 519};
595 520
596static struct uart_clk uart3_16xx = { 521static struct uart_clk uart3_16xx = {
597 .clk = { 522 .clk = {
598 .name = "uart3_ck", 523 .name = "uart3_ck",
524 .ops = &clkops_uart,
599 /* Direct from ULPD, no real parent */ 525 /* Direct from ULPD, no real parent */
600 .parent = &armper_ck.clk, 526 .parent = &armper_ck.clk,
601 .rate = 48000000, 527 .rate = 48000000,
602 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | 528 .flags = RATE_FIXED | ENABLE_REG_32BIT |
603 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 529 CLOCK_NO_IDLE_PARENT,
604 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, 530 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
605 .enable_bit = 31, 531 .enable_bit = 31,
606 .enable = &omap1_clk_enable_uart_functional,
607 .disable = &omap1_clk_disable_uart_functional,
608 }, 532 },
609 .sysc_addr = 0xfffb9854, 533 .sysc_addr = 0xfffb9854,
610}; 534};
611 535
612static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ 536static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
613 .name = "usb_clko", 537 .name = "usb_clko",
538 .ops = &clkops_generic,
614 /* Direct from ULPD, no parent */ 539 /* Direct from ULPD, no parent */
615 .rate = 6000000, 540 .rate = 6000000,
616 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 541 .flags = RATE_FIXED | ENABLE_REG_32BIT,
617 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT, 542 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
618 .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL,
619 .enable_bit = USB_MCLK_EN_BIT, 543 .enable_bit = USB_MCLK_EN_BIT,
620 .enable = &omap1_clk_enable_generic,
621 .disable = &omap1_clk_disable_generic,
622}; 544};
623 545
624static struct clk usb_hhc_ck1510 = { 546static struct clk usb_hhc_ck1510 = {
625 .name = "usb_hhc_ck", 547 .name = "usb_hhc_ck",
548 .ops = &clkops_generic,
626 /* Direct from ULPD, no parent */ 549 /* Direct from ULPD, no parent */
627 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ 550 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
628 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | 551 .flags = RATE_FIXED | ENABLE_REG_32BIT,
629 RATE_FIXED | ENABLE_REG_32BIT, 552 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
630 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
631 .enable_bit = USB_HOST_HHC_UHOST_EN, 553 .enable_bit = USB_HOST_HHC_UHOST_EN,
632 .enable = &omap1_clk_enable_generic,
633 .disable = &omap1_clk_disable_generic,
634}; 554};
635 555
636static struct clk usb_hhc_ck16xx = { 556static struct clk usb_hhc_ck16xx = {
637 .name = "usb_hhc_ck", 557 .name = "usb_hhc_ck",
558 .ops = &clkops_generic,
638 /* Direct from ULPD, no parent */ 559 /* Direct from ULPD, no parent */
639 .rate = 48000000, 560 .rate = 48000000,
640 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ 561 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
641 .flags = CLOCK_IN_OMAP16XX | 562 .flags = RATE_FIXED | ENABLE_REG_32BIT,
642 RATE_FIXED | ENABLE_REG_32BIT, 563 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
643 .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
644 .enable_bit = 8 /* UHOST_EN */, 564 .enable_bit = 8 /* UHOST_EN */,
645 .enable = &omap1_clk_enable_generic,
646 .disable = &omap1_clk_disable_generic,
647}; 565};
648 566
649static struct clk usb_dc_ck = { 567static struct clk usb_dc_ck = {
650 .name = "usb_dc_ck", 568 .name = "usb_dc_ck",
569 .ops = &clkops_generic,
651 /* Direct from ULPD, no parent */ 570 /* Direct from ULPD, no parent */
652 .rate = 48000000, 571 .rate = 48000000,
653 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED, 572 .flags = RATE_FIXED,
654 .enable_reg = (void __iomem *)SOFT_REQ_REG, 573 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
655 .enable_bit = 4, 574 .enable_bit = 4,
656 .enable = &omap1_clk_enable_generic,
657 .disable = &omap1_clk_disable_generic,
658}; 575};
659 576
660static struct clk mclk_1510 = { 577static struct clk mclk_1510 = {
661 .name = "mclk", 578 .name = "mclk",
579 .ops = &clkops_generic,
662 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 580 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
663 .rate = 12000000, 581 .rate = 12000000,
664 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED, 582 .flags = RATE_FIXED,
665 .enable_reg = (void __iomem *)SOFT_REQ_REG, 583 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
666 .enable_bit = 6, 584 .enable_bit = 6,
667 .enable = &omap1_clk_enable_generic,
668 .disable = &omap1_clk_disable_generic,
669}; 585};
670 586
671static struct clk mclk_16xx = { 587static struct clk mclk_16xx = {
672 .name = "mclk", 588 .name = "mclk",
589 .ops = &clkops_generic,
673 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 590 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
674 .flags = CLOCK_IN_OMAP16XX, 591 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
675 .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
676 .enable_bit = COM_ULPD_PLL_CLK_REQ, 592 .enable_bit = COM_ULPD_PLL_CLK_REQ,
677 .set_rate = &omap1_set_ext_clk_rate, 593 .set_rate = &omap1_set_ext_clk_rate,
678 .round_rate = &omap1_round_ext_clk_rate, 594 .round_rate = &omap1_round_ext_clk_rate,
679 .init = &omap1_init_ext_clk, 595 .init = &omap1_init_ext_clk,
680 .enable = &omap1_clk_enable_generic,
681 .disable = &omap1_clk_disable_generic,
682}; 596};
683 597
684static struct clk bclk_1510 = { 598static struct clk bclk_1510 = {
685 .name = "bclk", 599 .name = "bclk",
600 .ops = &clkops_generic,
686 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 601 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
687 .rate = 12000000, 602 .rate = 12000000,
688 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED, 603 .flags = RATE_FIXED,
689 .enable = &omap1_clk_enable_generic,
690 .disable = &omap1_clk_disable_generic,
691}; 604};
692 605
693static struct clk bclk_16xx = { 606static struct clk bclk_16xx = {
694 .name = "bclk", 607 .name = "bclk",
608 .ops = &clkops_generic,
695 /* Direct from ULPD, no parent. May be enabled by ext hardware. */ 609 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
696 .flags = CLOCK_IN_OMAP16XX, 610 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
697 .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
698 .enable_bit = SWD_ULPD_PLL_CLK_REQ, 611 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
699 .set_rate = &omap1_set_ext_clk_rate, 612 .set_rate = &omap1_set_ext_clk_rate,
700 .round_rate = &omap1_round_ext_clk_rate, 613 .round_rate = &omap1_round_ext_clk_rate,
701 .init = &omap1_init_ext_clk, 614 .init = &omap1_init_ext_clk,
702 .enable = &omap1_clk_enable_generic,
703 .disable = &omap1_clk_disable_generic,
704}; 615};
705 616
706static struct clk mmc1_ck = { 617static struct clk mmc1_ck = {
707 .name = "mmc_ck", 618 .name = "mmc_ck",
619 .ops = &clkops_generic,
708 /* Functional clock is direct from ULPD, interface clock is ARMPER */ 620 /* Functional clock is direct from ULPD, interface clock is ARMPER */
709 .parent = &armper_ck.clk, 621 .parent = &armper_ck.clk,
710 .rate = 48000000, 622 .rate = 48000000,
711 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 623 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
712 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT | 624 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
713 CLOCK_NO_IDLE_PARENT,
714 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
715 .enable_bit = 23, 625 .enable_bit = 23,
716 .enable = &omap1_clk_enable_generic,
717 .disable = &omap1_clk_disable_generic,
718}; 626};
719 627
720static struct clk mmc2_ck = { 628static struct clk mmc2_ck = {
721 .name = "mmc_ck", 629 .name = "mmc_ck",
722 .id = 1, 630 .id = 1,
631 .ops = &clkops_generic,
723 /* Functional clock is direct from ULPD, interface clock is ARMPER */ 632 /* Functional clock is direct from ULPD, interface clock is ARMPER */
724 .parent = &armper_ck.clk, 633 .parent = &armper_ck.clk,
725 .rate = 48000000, 634 .rate = 48000000,
726 .flags = CLOCK_IN_OMAP16XX | 635 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
727 RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, 636 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
728 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
729 .enable_bit = 20, 637 .enable_bit = 20,
730 .enable = &omap1_clk_enable_generic,
731 .disable = &omap1_clk_disable_generic,
732}; 638};
733 639
734static struct clk virtual_ck_mpu = { 640static struct clk virtual_ck_mpu = {
735 .name = "mpu", 641 .name = "mpu",
736 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 642 .ops = &clkops_null,
737 CLOCK_IN_OMAP310 | VIRTUAL_CLOCK | ALWAYS_ENABLED,
738 .parent = &arm_ck, /* Is smarter alias for */ 643 .parent = &arm_ck, /* Is smarter alias for */
739 .recalc = &followparent_recalc, 644 .recalc = &followparent_recalc,
740 .set_rate = &omap1_select_table_rate, 645 .set_rate = &omap1_select_table_rate,
741 .round_rate = &omap1_round_to_table_rate, 646 .round_rate = &omap1_round_to_table_rate,
742 .enable = &omap1_clk_enable_generic,
743 .disable = &omap1_clk_disable_generic,
744}; 647};
745 648
746/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK 649/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
@@ -748,78 +651,19 @@ remains active during MPU idle whenever this is enabled */
748static struct clk i2c_fck = { 651static struct clk i2c_fck = {
749 .name = "i2c_fck", 652 .name = "i2c_fck",
750 .id = 1, 653 .id = 1,
751 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | 654 .ops = &clkops_null,
752 VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT | 655 .flags = CLOCK_NO_IDLE_PARENT,
753 ALWAYS_ENABLED,
754 .parent = &armxor_ck.clk, 656 .parent = &armxor_ck.clk,
755 .recalc = &followparent_recalc, 657 .recalc = &followparent_recalc,
756 .enable = &omap1_clk_enable_generic,
757 .disable = &omap1_clk_disable_generic,
758}; 658};
759 659
760static struct clk i2c_ick = { 660static struct clk i2c_ick = {
761 .name = "i2c_ick", 661 .name = "i2c_ick",
762 .id = 1, 662 .id = 1,
763 .flags = CLOCK_IN_OMAP16XX | 663 .ops = &clkops_null,
764 VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT | 664 .flags = CLOCK_NO_IDLE_PARENT,
765 ALWAYS_ENABLED,
766 .parent = &armper_ck.clk, 665 .parent = &armper_ck.clk,
767 .recalc = &followparent_recalc, 666 .recalc = &followparent_recalc,
768 .enable = &omap1_clk_enable_generic,
769 .disable = &omap1_clk_disable_generic,
770};
771
772static struct clk * onchip_clks[] = {
773 /* non-ULPD clocks */
774 &ck_ref,
775 &ck_dpll1,
776 /* CK_GEN1 clocks */
777 &ck_dpll1out.clk,
778 &sossi_ck,
779 &arm_ck,
780 &armper_ck.clk,
781 &arm_gpio_ck,
782 &armxor_ck.clk,
783 &armtim_ck.clk,
784 &armwdt_ck.clk,
785 &arminth_ck1510, &arminth_ck16xx,
786 /* CK_GEN2 clocks */
787 &dsp_ck,
788 &dspmmu_ck,
789 &dspper_ck,
790 &dspxor_ck,
791 &dsptim_ck,
792 /* CK_GEN3 clocks */
793 &tc_ck.clk,
794 &tipb_ck,
795 &l3_ocpi_ck,
796 &tc1_ck,
797 &tc2_ck,
798 &dma_ck,
799 &dma_lcdfree_ck,
800 &api_ck.clk,
801 &lb_ck.clk,
802 &rhea1_ck,
803 &rhea2_ck,
804 &lcd_ck_16xx,
805 &lcd_ck_1510.clk,
806 /* ULPD clocks */
807 &uart1_1510,
808 &uart1_16xx.clk,
809 &uart2_ck,
810 &uart3_1510,
811 &uart3_16xx.clk,
812 &usb_clko,
813 &usb_hhc_ck1510, &usb_hhc_ck16xx,
814 &usb_dc_ck,
815 &mclk_1510, &mclk_16xx,
816 &bclk_1510, &bclk_16xx,
817 &mmc1_ck,
818 &mmc2_ck,
819 /* Virtual clocks */
820 &virtual_ck_mpu,
821 &i2c_fck,
822 &i2c_ick,
823}; 667};
824 668
825#endif 669#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 17:32:21 -0500