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-rw-r--r--arch/arm/mach-omap1/clock.h667
1 files changed, 37 insertions, 630 deletions
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index 70195cad7610..a4190afb8614 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/mach-omap1/clock.h 2 * linux/arch/arm/mach-omap1/clock.h
3 * 3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation 4 * Copyright (C) 2004 - 2005, 2009 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc 6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 * 7 *
@@ -13,30 +13,36 @@
13#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H 13#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
14#define __ARCH_ARM_MACH_OMAP1_CLOCK_H 14#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
15 15
16static unsigned long omap1_ckctl_recalc(struct clk *clk); 16#include <linux/clk.h>
17static unsigned long omap1_watchdog_recalc(struct clk *clk); 17
18static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); 18#include <plat/clock.h>
19static unsigned long omap1_sossi_recalc(struct clk *clk); 19
20static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); 20extern int __init omap1_clk_init(void);
21static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); 21extern int omap1_clk_enable(struct clk *clk);
22static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); 22extern void omap1_clk_disable(struct clk *clk);
23static unsigned long omap1_uart_recalc(struct clk *clk); 23extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
24static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); 24extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
25static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); 25extern unsigned long omap1_ckctl_recalc(struct clk *clk);
26static void omap1_init_ext_clk(struct clk * clk); 26extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
27static int omap1_select_table_rate(struct clk * clk, unsigned long rate); 27extern unsigned long omap1_sossi_recalc(struct clk *clk);
28static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); 28extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
29 29extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
30static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); 30extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
31static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); 31extern unsigned long omap1_uart_recalc(struct clk *clk);
32 32extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
33struct mpu_rate { 33extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
34 unsigned long rate; 34extern void omap1_init_ext_clk(struct clk *clk);
35 unsigned long xtal; 35extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
36 unsigned long pll_rate; 36extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
37 __u16 ckctl_val; 37extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
38 __u16 dpllctl_val; 38extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
39}; 39extern unsigned long omap1_watchdog_recalc(struct clk *clk);
40
41#ifdef CONFIG_OMAP_RESET_CLOCKS
42extern void __init omap1_clk_disable_unused(struct clk *clk);
43#else
44#define omap1_clk_disable_unused NULL
45#endif
40 46
41struct uart_clk { 47struct uart_clk {
42 struct clk clk; 48 struct clk clk;
@@ -96,611 +102,12 @@ struct arm_idlect1_clk {
96#define SOFT_REQ_REG 0xfffe0834 102#define SOFT_REQ_REG 0xfffe0834
97#define SOFT_REQ_REG2 0xfffe0880 103#define SOFT_REQ_REG2 0xfffe0880
98 104
99/*------------------------------------------------------------------------- 105extern __u32 arm_idlect1_mask;
100 * Omap1 MPU rate table 106extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
101 *-------------------------------------------------------------------------*/
102static struct mpu_rate rate_table[] = {
103 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
104 * NOTE: Comment order here is different from bits in CKCTL value:
105 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
106 */
107#if defined(CONFIG_OMAP_ARM_216MHZ)
108 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
109#endif
110#if defined(CONFIG_OMAP_ARM_195MHZ)
111 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
112#endif
113#if defined(CONFIG_OMAP_ARM_192MHZ)
114 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
115 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
116 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
117 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
118 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
119#endif
120#if defined(CONFIG_OMAP_ARM_182MHZ)
121 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
122#endif
123#if defined(CONFIG_OMAP_ARM_168MHZ)
124 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
125#endif
126#if defined(CONFIG_OMAP_ARM_150MHZ)
127 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
128#endif
129#if defined(CONFIG_OMAP_ARM_120MHZ)
130 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
131#endif
132#if defined(CONFIG_OMAP_ARM_96MHZ)
133 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
134#endif
135#if defined(CONFIG_OMAP_ARM_60MHZ)
136 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
137#endif
138#if defined(CONFIG_OMAP_ARM_30MHZ)
139 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
140#endif
141 { 0, 0, 0, 0, 0 },
142};
143
144/*-------------------------------------------------------------------------
145 * Omap1 clocks
146 *-------------------------------------------------------------------------*/
147 107
148static struct clk ck_ref = { 108extern const struct clkops clkops_dspck;
149 .name = "ck_ref", 109extern const struct clkops clkops_dummy;
150 .ops = &clkops_null, 110extern const struct clkops clkops_uart;
151 .rate = 12000000, 111extern const struct clkops clkops_generic;
152};
153
154static struct clk ck_dpll1 = {
155 .name = "ck_dpll1",
156 .ops = &clkops_null,
157 .parent = &ck_ref,
158};
159
160/*
161 * FIXME: This clock seems to be necessary but no-one has asked for its
162 * activation. [ FIX: SoSSI, SSR ]
163 */
164static struct arm_idlect1_clk ck_dpll1out = {
165 .clk = {
166 .name = "ck_dpll1out",
167 .ops = &clkops_generic,
168 .parent = &ck_dpll1,
169 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
170 ENABLE_ON_INIT,
171 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
172 .enable_bit = EN_CKOUT_ARM,
173 .recalc = &followparent_recalc,
174 },
175 .idlect_shift = 12,
176};
177
178static struct clk sossi_ck = {
179 .name = "ck_sossi",
180 .ops = &clkops_generic,
181 .parent = &ck_dpll1out.clk,
182 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
183 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
184 .enable_bit = 16,
185 .recalc = &omap1_sossi_recalc,
186 .set_rate = &omap1_set_sossi_rate,
187};
188
189static struct clk arm_ck = {
190 .name = "arm_ck",
191 .ops = &clkops_null,
192 .parent = &ck_dpll1,
193 .rate_offset = CKCTL_ARMDIV_OFFSET,
194 .recalc = &omap1_ckctl_recalc,
195 .round_rate = omap1_clk_round_rate_ckctl_arm,
196 .set_rate = omap1_clk_set_rate_ckctl_arm,
197};
198
199static struct arm_idlect1_clk armper_ck = {
200 .clk = {
201 .name = "armper_ck",
202 .ops = &clkops_generic,
203 .parent = &ck_dpll1,
204 .flags = CLOCK_IDLE_CONTROL,
205 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
206 .enable_bit = EN_PERCK,
207 .rate_offset = CKCTL_PERDIV_OFFSET,
208 .recalc = &omap1_ckctl_recalc,
209 .round_rate = omap1_clk_round_rate_ckctl_arm,
210 .set_rate = omap1_clk_set_rate_ckctl_arm,
211 },
212 .idlect_shift = 2,
213};
214
215/*
216 * FIXME: This clock seems to be necessary but no-one has asked for its
217 * activation. [ GPIO code for 1510 ]
218 */
219static struct clk arm_gpio_ck = {
220 .name = "arm_gpio_ck",
221 .ops = &clkops_generic,
222 .parent = &ck_dpll1,
223 .flags = ENABLE_ON_INIT,
224 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
225 .enable_bit = EN_GPIOCK,
226 .recalc = &followparent_recalc,
227};
228
229static struct arm_idlect1_clk armxor_ck = {
230 .clk = {
231 .name = "armxor_ck",
232 .ops = &clkops_generic,
233 .parent = &ck_ref,
234 .flags = CLOCK_IDLE_CONTROL,
235 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
236 .enable_bit = EN_XORPCK,
237 .recalc = &followparent_recalc,
238 },
239 .idlect_shift = 1,
240};
241
242static struct arm_idlect1_clk armtim_ck = {
243 .clk = {
244 .name = "armtim_ck",
245 .ops = &clkops_generic,
246 .parent = &ck_ref,
247 .flags = CLOCK_IDLE_CONTROL,
248 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
249 .enable_bit = EN_TIMCK,
250 .recalc = &followparent_recalc,
251 },
252 .idlect_shift = 9,
253};
254
255static struct arm_idlect1_clk armwdt_ck = {
256 .clk = {
257 .name = "armwdt_ck",
258 .ops = &clkops_generic,
259 .parent = &ck_ref,
260 .flags = CLOCK_IDLE_CONTROL,
261 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
262 .enable_bit = EN_WDTCK,
263 .recalc = &omap1_watchdog_recalc,
264 },
265 .idlect_shift = 0,
266};
267
268static struct clk arminth_ck16xx = {
269 .name = "arminth_ck",
270 .ops = &clkops_null,
271 .parent = &arm_ck,
272 .recalc = &followparent_recalc,
273 /* Note: On 16xx the frequency can be divided by 2 by programming
274 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
275 *
276 * 1510 version is in TC clocks.
277 */
278};
279
280static struct clk dsp_ck = {
281 .name = "dsp_ck",
282 .ops = &clkops_generic,
283 .parent = &ck_dpll1,
284 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
285 .enable_bit = EN_DSPCK,
286 .rate_offset = CKCTL_DSPDIV_OFFSET,
287 .recalc = &omap1_ckctl_recalc,
288 .round_rate = omap1_clk_round_rate_ckctl_arm,
289 .set_rate = omap1_clk_set_rate_ckctl_arm,
290};
291
292static struct clk dspmmu_ck = {
293 .name = "dspmmu_ck",
294 .ops = &clkops_null,
295 .parent = &ck_dpll1,
296 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
297 .recalc = &omap1_ckctl_recalc,
298 .round_rate = omap1_clk_round_rate_ckctl_arm,
299 .set_rate = omap1_clk_set_rate_ckctl_arm,
300};
301
302static struct clk dspper_ck = {
303 .name = "dspper_ck",
304 .ops = &clkops_dspck,
305 .parent = &ck_dpll1,
306 .enable_reg = DSP_IDLECT2,
307 .enable_bit = EN_PERCK,
308 .rate_offset = CKCTL_PERDIV_OFFSET,
309 .recalc = &omap1_ckctl_recalc_dsp_domain,
310 .round_rate = omap1_clk_round_rate_ckctl_arm,
311 .set_rate = &omap1_clk_set_rate_dsp_domain,
312};
313
314static struct clk dspxor_ck = {
315 .name = "dspxor_ck",
316 .ops = &clkops_dspck,
317 .parent = &ck_ref,
318 .enable_reg = DSP_IDLECT2,
319 .enable_bit = EN_XORPCK,
320 .recalc = &followparent_recalc,
321};
322
323static struct clk dsptim_ck = {
324 .name = "dsptim_ck",
325 .ops = &clkops_dspck,
326 .parent = &ck_ref,
327 .enable_reg = DSP_IDLECT2,
328 .enable_bit = EN_DSPTIMCK,
329 .recalc = &followparent_recalc,
330};
331
332/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
333static struct arm_idlect1_clk tc_ck = {
334 .clk = {
335 .name = "tc_ck",
336 .ops = &clkops_null,
337 .parent = &ck_dpll1,
338 .flags = CLOCK_IDLE_CONTROL,
339 .rate_offset = CKCTL_TCDIV_OFFSET,
340 .recalc = &omap1_ckctl_recalc,
341 .round_rate = omap1_clk_round_rate_ckctl_arm,
342 .set_rate = omap1_clk_set_rate_ckctl_arm,
343 },
344 .idlect_shift = 6,
345};
346
347static struct clk arminth_ck1510 = {
348 .name = "arminth_ck",
349 .ops = &clkops_null,
350 .parent = &tc_ck.clk,
351 .recalc = &followparent_recalc,
352 /* Note: On 1510 the frequency follows TC_CK
353 *
354 * 16xx version is in MPU clocks.
355 */
356};
357
358static struct clk tipb_ck = {
359 /* No-idle controlled by "tc_ck" */
360 .name = "tipb_ck",
361 .ops = &clkops_null,
362 .parent = &tc_ck.clk,
363 .recalc = &followparent_recalc,
364};
365
366static struct clk l3_ocpi_ck = {
367 /* No-idle controlled by "tc_ck" */
368 .name = "l3_ocpi_ck",
369 .ops = &clkops_generic,
370 .parent = &tc_ck.clk,
371 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
372 .enable_bit = EN_OCPI_CK,
373 .recalc = &followparent_recalc,
374};
375
376static struct clk tc1_ck = {
377 .name = "tc1_ck",
378 .ops = &clkops_generic,
379 .parent = &tc_ck.clk,
380 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
381 .enable_bit = EN_TC1_CK,
382 .recalc = &followparent_recalc,
383};
384
385/*
386 * FIXME: This clock seems to be necessary but no-one has asked for its
387 * activation. [ pm.c (SRAM), CCP, Camera ]
388 */
389static struct clk tc2_ck = {
390 .name = "tc2_ck",
391 .ops = &clkops_generic,
392 .parent = &tc_ck.clk,
393 .flags = ENABLE_ON_INIT,
394 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
395 .enable_bit = EN_TC2_CK,
396 .recalc = &followparent_recalc,
397};
398
399static struct clk dma_ck = {
400 /* No-idle controlled by "tc_ck" */
401 .name = "dma_ck",
402 .ops = &clkops_null,
403 .parent = &tc_ck.clk,
404 .recalc = &followparent_recalc,
405};
406
407static struct clk dma_lcdfree_ck = {
408 .name = "dma_lcdfree_ck",
409 .ops = &clkops_null,
410 .parent = &tc_ck.clk,
411 .recalc = &followparent_recalc,
412};
413
414static struct arm_idlect1_clk api_ck = {
415 .clk = {
416 .name = "api_ck",
417 .ops = &clkops_generic,
418 .parent = &tc_ck.clk,
419 .flags = CLOCK_IDLE_CONTROL,
420 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
421 .enable_bit = EN_APICK,
422 .recalc = &followparent_recalc,
423 },
424 .idlect_shift = 8,
425};
426
427static struct arm_idlect1_clk lb_ck = {
428 .clk = {
429 .name = "lb_ck",
430 .ops = &clkops_generic,
431 .parent = &tc_ck.clk,
432 .flags = CLOCK_IDLE_CONTROL,
433 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
434 .enable_bit = EN_LBCK,
435 .recalc = &followparent_recalc,
436 },
437 .idlect_shift = 4,
438};
439
440static struct clk rhea1_ck = {
441 .name = "rhea1_ck",
442 .ops = &clkops_null,
443 .parent = &tc_ck.clk,
444 .recalc = &followparent_recalc,
445};
446
447static struct clk rhea2_ck = {
448 .name = "rhea2_ck",
449 .ops = &clkops_null,
450 .parent = &tc_ck.clk,
451 .recalc = &followparent_recalc,
452};
453
454static struct clk lcd_ck_16xx = {
455 .name = "lcd_ck",
456 .ops = &clkops_generic,
457 .parent = &ck_dpll1,
458 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
459 .enable_bit = EN_LCDCK,
460 .rate_offset = CKCTL_LCDDIV_OFFSET,
461 .recalc = &omap1_ckctl_recalc,
462 .round_rate = omap1_clk_round_rate_ckctl_arm,
463 .set_rate = omap1_clk_set_rate_ckctl_arm,
464};
465
466static struct arm_idlect1_clk lcd_ck_1510 = {
467 .clk = {
468 .name = "lcd_ck",
469 .ops = &clkops_generic,
470 .parent = &ck_dpll1,
471 .flags = CLOCK_IDLE_CONTROL,
472 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
473 .enable_bit = EN_LCDCK,
474 .rate_offset = CKCTL_LCDDIV_OFFSET,
475 .recalc = &omap1_ckctl_recalc,
476 .round_rate = omap1_clk_round_rate_ckctl_arm,
477 .set_rate = omap1_clk_set_rate_ckctl_arm,
478 },
479 .idlect_shift = 3,
480};
481
482static struct clk uart1_1510 = {
483 .name = "uart1_ck",
484 .ops = &clkops_null,
485 /* Direct from ULPD, no real parent */
486 .parent = &armper_ck.clk,
487 .rate = 12000000,
488 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
489 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
490 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
491 .set_rate = &omap1_set_uart_rate,
492 .recalc = &omap1_uart_recalc,
493};
494
495static struct uart_clk uart1_16xx = {
496 .clk = {
497 .name = "uart1_ck",
498 .ops = &clkops_uart,
499 /* Direct from ULPD, no real parent */
500 .parent = &armper_ck.clk,
501 .rate = 48000000,
502 .flags = RATE_FIXED | ENABLE_REG_32BIT |
503 CLOCK_NO_IDLE_PARENT,
504 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
505 .enable_bit = 29,
506 },
507 .sysc_addr = 0xfffb0054,
508};
509
510static struct clk uart2_ck = {
511 .name = "uart2_ck",
512 .ops = &clkops_null,
513 /* Direct from ULPD, no real parent */
514 .parent = &armper_ck.clk,
515 .rate = 12000000,
516 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
517 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
518 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
519 .set_rate = &omap1_set_uart_rate,
520 .recalc = &omap1_uart_recalc,
521};
522
523static struct clk uart3_1510 = {
524 .name = "uart3_ck",
525 .ops = &clkops_null,
526 /* Direct from ULPD, no real parent */
527 .parent = &armper_ck.clk,
528 .rate = 12000000,
529 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
530 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
531 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
532 .set_rate = &omap1_set_uart_rate,
533 .recalc = &omap1_uart_recalc,
534};
535
536static struct uart_clk uart3_16xx = {
537 .clk = {
538 .name = "uart3_ck",
539 .ops = &clkops_uart,
540 /* Direct from ULPD, no real parent */
541 .parent = &armper_ck.clk,
542 .rate = 48000000,
543 .flags = RATE_FIXED | ENABLE_REG_32BIT |
544 CLOCK_NO_IDLE_PARENT,
545 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
546 .enable_bit = 31,
547 },
548 .sysc_addr = 0xfffb9854,
549};
550
551static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
552 .name = "usb_clko",
553 .ops = &clkops_generic,
554 /* Direct from ULPD, no parent */
555 .rate = 6000000,
556 .flags = RATE_FIXED | ENABLE_REG_32BIT,
557 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
558 .enable_bit = USB_MCLK_EN_BIT,
559};
560
561static struct clk usb_hhc_ck1510 = {
562 .name = "usb_hhc_ck",
563 .ops = &clkops_generic,
564 /* Direct from ULPD, no parent */
565 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
566 .flags = RATE_FIXED | ENABLE_REG_32BIT,
567 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
568 .enable_bit = USB_HOST_HHC_UHOST_EN,
569};
570
571static struct clk usb_hhc_ck16xx = {
572 .name = "usb_hhc_ck",
573 .ops = &clkops_generic,
574 /* Direct from ULPD, no parent */
575 .rate = 48000000,
576 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
577 .flags = RATE_FIXED | ENABLE_REG_32BIT,
578 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
579 .enable_bit = 8 /* UHOST_EN */,
580};
581
582static struct clk usb_dc_ck = {
583 .name = "usb_dc_ck",
584 .ops = &clkops_generic,
585 /* Direct from ULPD, no parent */
586 .rate = 48000000,
587 .flags = RATE_FIXED,
588 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
589 .enable_bit = 4,
590};
591
592static struct clk usb_dc_ck7xx = {
593 .name = "usb_dc_ck",
594 .ops = &clkops_generic,
595 /* Direct from ULPD, no parent */
596 .rate = 48000000,
597 .flags = RATE_FIXED,
598 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
599 .enable_bit = 8,
600};
601
602static struct clk mclk_1510 = {
603 .name = "mclk",
604 .ops = &clkops_generic,
605 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
606 .rate = 12000000,
607 .flags = RATE_FIXED,
608 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
609 .enable_bit = 6,
610};
611
612static struct clk mclk_16xx = {
613 .name = "mclk",
614 .ops = &clkops_generic,
615 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
616 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
617 .enable_bit = COM_ULPD_PLL_CLK_REQ,
618 .set_rate = &omap1_set_ext_clk_rate,
619 .round_rate = &omap1_round_ext_clk_rate,
620 .init = &omap1_init_ext_clk,
621};
622
623static struct clk bclk_1510 = {
624 .name = "bclk",
625 .ops = &clkops_generic,
626 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
627 .rate = 12000000,
628 .flags = RATE_FIXED,
629};
630
631static struct clk bclk_16xx = {
632 .name = "bclk",
633 .ops = &clkops_generic,
634 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
635 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
636 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
637 .set_rate = &omap1_set_ext_clk_rate,
638 .round_rate = &omap1_round_ext_clk_rate,
639 .init = &omap1_init_ext_clk,
640};
641
642static struct clk mmc1_ck = {
643 .name = "mmc_ck",
644 .ops = &clkops_generic,
645 /* Functional clock is direct from ULPD, interface clock is ARMPER */
646 .parent = &armper_ck.clk,
647 .rate = 48000000,
648 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
649 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
650 .enable_bit = 23,
651};
652
653static struct clk mmc2_ck = {
654 .name = "mmc_ck",
655 .id = 1,
656 .ops = &clkops_generic,
657 /* Functional clock is direct from ULPD, interface clock is ARMPER */
658 .parent = &armper_ck.clk,
659 .rate = 48000000,
660 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
661 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
662 .enable_bit = 20,
663};
664
665static struct clk mmc3_ck = {
666 .name = "mmc_ck",
667 .id = 2,
668 .ops = &clkops_generic,
669 /* Functional clock is direct from ULPD, interface clock is ARMPER */
670 .parent = &armper_ck.clk,
671 .rate = 48000000,
672 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
673 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
674 .enable_bit = 12,
675};
676
677static struct clk virtual_ck_mpu = {
678 .name = "mpu",
679 .ops = &clkops_null,
680 .parent = &arm_ck, /* Is smarter alias for */
681 .recalc = &followparent_recalc,
682 .set_rate = &omap1_select_table_rate,
683 .round_rate = &omap1_round_to_table_rate,
684};
685
686/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
687remains active during MPU idle whenever this is enabled */
688static struct clk i2c_fck = {
689 .name = "i2c_fck",
690 .id = 1,
691 .ops = &clkops_null,
692 .flags = CLOCK_NO_IDLE_PARENT,
693 .parent = &armxor_ck.clk,
694 .recalc = &followparent_recalc,
695};
696
697static struct clk i2c_ick = {
698 .name = "i2c_ick",
699 .id = 1,
700 .ops = &clkops_null,
701 .flags = CLOCK_NO_IDLE_PARENT,
702 .parent = &armper_ck.clk,
703 .recalc = &followparent_recalc,
704};
705 112
706#endif 113#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 03:41:26 -0500