aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap1/clock.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-omap1/clock.c')
-rw-r--r--arch/arm/mach-omap1/clock.c501
1 files changed, 112 insertions, 389 deletions
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 42cbe203da36..2ba9ab953731 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/mach-omap1/clock.c 2 * linux/arch/arm/mach-omap1/clock.c
3 * 3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation 4 * Copyright (C) 2004 - 2005, 2009 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * 6 *
7 * Modified to use omap shared clock framework by 7 * Modified to use omap shared clock framework by
@@ -26,12 +26,17 @@
26#include <plat/usb.h> 26#include <plat/usb.h>
27#include <plat/clock.h> 27#include <plat/clock.h>
28#include <plat/sram.h> 28#include <plat/sram.h>
29 29#include <plat/clkdev_omap.h>
30static const struct clkops clkops_generic;
31static const struct clkops clkops_uart;
32static const struct clkops clkops_dspck;
33 30
34#include "clock.h" 31#include "clock.h"
32#include "opp.h"
33
34__u32 arm_idlect1_mask;
35struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
36
37/*-------------------------------------------------------------------------
38 * Omap1 specific clock functions
39 *-------------------------------------------------------------------------*/
35 40
36static int clk_omap1_dummy_enable(struct clk *clk) 41static int clk_omap1_dummy_enable(struct clk *clk)
37{ 42{
@@ -42,134 +47,24 @@ static void clk_omap1_dummy_disable(struct clk *clk)
42{ 47{
43} 48}
44 49
45static const struct clkops clkops_dummy = { 50const struct clkops clkops_dummy = {
46 .enable = clk_omap1_dummy_enable, 51 .enable = clk_omap1_dummy_enable,
47 .disable = clk_omap1_dummy_disable, 52 .disable = clk_omap1_dummy_disable,
48};
49
50static struct clk dummy_ck = {
51 .name = "dummy",
52 .ops = &clkops_dummy,
53 .flags = RATE_FIXED,
54};
55
56struct omap_clk {
57 u32 cpu;
58 struct clk_lookup lk;
59}; 53};
60 54
61#define CLK(dev, con, ck, cp) \ 55/* XXX can be replaced with a fixed_divisor_recalc */
62 { \ 56unsigned long omap1_watchdog_recalc(struct clk *clk)
63 .cpu = cp, \
64 .lk = { \
65 .dev_id = dev, \
66 .con_id = con, \
67 .clk = ck, \
68 }, \
69 }
70
71#define CK_310 (1 << 0)
72#define CK_7XX (1 << 1)
73#define CK_1510 (1 << 2)
74#define CK_16XX (1 << 3)
75
76static struct omap_clk omap_clks[] = {
77 /* non-ULPD clocks */
78 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
79 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310),
80 /* CK_GEN1 clocks */
81 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
82 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
83 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
84 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
85 CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310),
86 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
87 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
88 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
89 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
90 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
91 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
92 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
93 /* CK_GEN2 clocks */
94 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
95 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
96 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
97 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
98 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
99 /* CK_GEN3 clocks */
100 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
101 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
102 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
103 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
104 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
105 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
106 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
107 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310),
108 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
109 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
110 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
111 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
112 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
113 /* ULPD clocks */
114 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
115 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
116 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
117 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
118 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
119 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
120 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
121 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
122 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX),
123 CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX),
124 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
125 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
126 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
127 CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
128 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
129 CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
130 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
131 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
132 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
133 /* Virtual clocks */
134 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
135 CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310),
136 CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX),
137 CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310),
138 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
139 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
140 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
141 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
142 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
143 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
144 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
145 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
146 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
147 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
148};
149
150static int omap1_clk_enable_generic(struct clk * clk);
151static int omap1_clk_enable(struct clk *clk);
152static void omap1_clk_disable_generic(struct clk * clk);
153static void omap1_clk_disable(struct clk *clk);
154
155__u32 arm_idlect1_mask;
156
157/*-------------------------------------------------------------------------
158 * Omap1 specific clock functions
159 *-------------------------------------------------------------------------*/
160
161static unsigned long omap1_watchdog_recalc(struct clk *clk)
162{ 57{
163 return clk->parent->rate / 14; 58 return clk->parent->rate / 14;
164} 59}
165 60
166static unsigned long omap1_uart_recalc(struct clk *clk) 61unsigned long omap1_uart_recalc(struct clk *clk)
167{ 62{
168 unsigned int val = __raw_readl(clk->enable_reg); 63 unsigned int val = __raw_readl(clk->enable_reg);
169 return val & clk->enable_bit ? 48000000 : 12000000; 64 return val & clk->enable_bit ? 48000000 : 12000000;
170} 65}
171 66
172static unsigned long omap1_sossi_recalc(struct clk *clk) 67unsigned long omap1_sossi_recalc(struct clk *clk)
173{ 68{
174 u32 div = omap_readl(MOD_CONF_CTRL_1); 69 u32 div = omap_readl(MOD_CONF_CTRL_1);
175 70
@@ -179,64 +74,6 @@ static unsigned long omap1_sossi_recalc(struct clk *clk)
179 return clk->parent->rate / div; 74 return clk->parent->rate / div;
180} 75}
181 76
182static int omap1_clk_enable_dsp_domain(struct clk *clk)
183{
184 int retval;
185
186 retval = omap1_clk_enable(&api_ck.clk);
187 if (!retval) {
188 retval = omap1_clk_enable_generic(clk);
189 omap1_clk_disable(&api_ck.clk);
190 }
191
192 return retval;
193}
194
195static void omap1_clk_disable_dsp_domain(struct clk *clk)
196{
197 if (omap1_clk_enable(&api_ck.clk) == 0) {
198 omap1_clk_disable_generic(clk);
199 omap1_clk_disable(&api_ck.clk);
200 }
201}
202
203static const struct clkops clkops_dspck = {
204 .enable = &omap1_clk_enable_dsp_domain,
205 .disable = &omap1_clk_disable_dsp_domain,
206};
207
208static int omap1_clk_enable_uart_functional(struct clk *clk)
209{
210 int ret;
211 struct uart_clk *uclk;
212
213 ret = omap1_clk_enable_generic(clk);
214 if (ret == 0) {
215 /* Set smart idle acknowledgement mode */
216 uclk = (struct uart_clk *)clk;
217 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
218 uclk->sysc_addr);
219 }
220
221 return ret;
222}
223
224static void omap1_clk_disable_uart_functional(struct clk *clk)
225{
226 struct uart_clk *uclk;
227
228 /* Set force idle acknowledgement mode */
229 uclk = (struct uart_clk *)clk;
230 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
231
232 omap1_clk_disable_generic(clk);
233}
234
235static const struct clkops clkops_uart = {
236 .enable = &omap1_clk_enable_uart_functional,
237 .disable = &omap1_clk_disable_uart_functional,
238};
239
240static void omap1_clk_allow_idle(struct clk *clk) 77static void omap1_clk_allow_idle(struct clk *clk)
241{ 78{
242 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; 79 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
@@ -344,7 +181,7 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
344 return dsor_exp; 181 return dsor_exp;
345} 182}
346 183
347static unsigned long omap1_ckctl_recalc(struct clk *clk) 184unsigned long omap1_ckctl_recalc(struct clk *clk)
348{ 185{
349 /* Calculate divisor encoded as 2-bit exponent */ 186 /* Calculate divisor encoded as 2-bit exponent */
350 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); 187 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
@@ -352,7 +189,7 @@ static unsigned long omap1_ckctl_recalc(struct clk *clk)
352 return clk->parent->rate / dsor; 189 return clk->parent->rate / dsor;
353} 190}
354 191
355static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) 192unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
356{ 193{
357 int dsor; 194 int dsor;
358 195
@@ -363,28 +200,29 @@ static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
363 * Note that DSP_CKCTL virt addr = phys addr, so 200 * Note that DSP_CKCTL virt addr = phys addr, so
364 * we must use __raw_readw() instead of omap_readw(). 201 * we must use __raw_readw() instead of omap_readw().
365 */ 202 */
366 omap1_clk_enable(&api_ck.clk); 203 omap1_clk_enable(api_ck_p);
367 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); 204 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
368 omap1_clk_disable(&api_ck.clk); 205 omap1_clk_disable(api_ck_p);
369 206
370 return clk->parent->rate / dsor; 207 return clk->parent->rate / dsor;
371} 208}
372 209
373/* MPU virtual clock functions */ 210/* MPU virtual clock functions */
374static int omap1_select_table_rate(struct clk * clk, unsigned long rate) 211int omap1_select_table_rate(struct clk *clk, unsigned long rate)
375{ 212{
376 /* Find the highest supported frequency <= rate and switch to it */ 213 /* Find the highest supported frequency <= rate and switch to it */
377 struct mpu_rate * ptr; 214 struct mpu_rate * ptr;
215 unsigned long dpll1_rate, ref_rate;
378 216
379 if (clk != &virtual_ck_mpu) 217 dpll1_rate = clk_get_rate(ck_dpll1_p);
380 return -EINVAL; 218 ref_rate = clk_get_rate(ck_ref_p);
381 219
382 for (ptr = rate_table; ptr->rate; ptr++) { 220 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
383 if (ptr->xtal != ck_ref.rate) 221 if (ptr->xtal != ref_rate)
384 continue; 222 continue;
385 223
386 /* DPLL1 cannot be reprogrammed without risking system crash */ 224 /* DPLL1 cannot be reprogrammed without risking system crash */
387 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate) 225 if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
388 continue; 226 continue;
389 227
390 /* Can check only after xtal frequency check */ 228 /* Can check only after xtal frequency check */
@@ -405,11 +243,13 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
405 else 243 else
406 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); 244 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
407 245
408 ck_dpll1.rate = ptr->pll_rate; 246 /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
247 ck_dpll1_p->rate = ptr->pll_rate;
248
409 return 0; 249 return 0;
410} 250}
411 251
412static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) 252int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
413{ 253{
414 int dsor_exp; 254 int dsor_exp;
415 u16 regval; 255 u16 regval;
@@ -429,7 +269,7 @@ static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
429 return 0; 269 return 0;
430} 270}
431 271
432static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) 272long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
433{ 273{
434 int dsor_exp = calc_dsor_exp(clk, rate); 274 int dsor_exp = calc_dsor_exp(clk, rate);
435 if (dsor_exp < 0) 275 if (dsor_exp < 0)
@@ -439,7 +279,7 @@ static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
439 return clk->parent->rate / (1 << dsor_exp); 279 return clk->parent->rate / (1 << dsor_exp);
440} 280}
441 281
442static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) 282int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
443{ 283{
444 int dsor_exp; 284 int dsor_exp;
445 u16 regval; 285 u16 regval;
@@ -459,19 +299,19 @@ static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
459 return 0; 299 return 0;
460} 300}
461 301
462static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) 302long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
463{ 303{
464 /* Find the highest supported frequency <= rate */ 304 /* Find the highest supported frequency <= rate */
465 struct mpu_rate * ptr; 305 struct mpu_rate * ptr;
466 long highest_rate; 306 long highest_rate;
307 unsigned long ref_rate;
467 308
468 if (clk != &virtual_ck_mpu) 309 ref_rate = clk_get_rate(ck_ref_p);
469 return -EINVAL;
470 310
471 highest_rate = -EINVAL; 311 highest_rate = -EINVAL;
472 312
473 for (ptr = rate_table; ptr->rate; ptr++) { 313 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
474 if (ptr->xtal != ck_ref.rate) 314 if (ptr->xtal != ref_rate)
475 continue; 315 continue;
476 316
477 highest_rate = ptr->rate; 317 highest_rate = ptr->rate;
@@ -506,8 +346,8 @@ static unsigned calc_ext_dsor(unsigned long rate)
506 return dsor; 346 return dsor;
507} 347}
508 348
509/* Only needed on 1510 */ 349/* XXX Only needed on 1510 */
510static int omap1_set_uart_rate(struct clk * clk, unsigned long rate) 350int omap1_set_uart_rate(struct clk *clk, unsigned long rate)
511{ 351{
512 unsigned int val; 352 unsigned int val;
513 353
@@ -525,7 +365,7 @@ static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
525} 365}
526 366
527/* External clock (MCLK & BCLK) functions */ 367/* External clock (MCLK & BCLK) functions */
528static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) 368int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
529{ 369{
530 unsigned dsor; 370 unsigned dsor;
531 __u16 ratio_bits; 371 __u16 ratio_bits;
@@ -543,7 +383,7 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
543 return 0; 383 return 0;
544} 384}
545 385
546static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) 386int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
547{ 387{
548 u32 l; 388 u32 l;
549 int div; 389 int div;
@@ -566,12 +406,12 @@ static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
566 return 0; 406 return 0;
567} 407}
568 408
569static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate) 409long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate)
570{ 410{
571 return 96000000 / calc_ext_dsor(rate); 411 return 96000000 / calc_ext_dsor(rate);
572} 412}
573 413
574static void omap1_init_ext_clk(struct clk * clk) 414void omap1_init_ext_clk(struct clk *clk)
575{ 415{
576 unsigned dsor; 416 unsigned dsor;
577 __u16 ratio_bits; 417 __u16 ratio_bits;
@@ -589,7 +429,7 @@ static void omap1_init_ext_clk(struct clk * clk)
589 clk-> rate = 96000000 / dsor; 429 clk-> rate = 96000000 / dsor;
590} 430}
591 431
592static int omap1_clk_enable(struct clk *clk) 432int omap1_clk_enable(struct clk *clk)
593{ 433{
594 int ret = 0; 434 int ret = 0;
595 435
@@ -617,7 +457,7 @@ err:
617 return ret; 457 return ret;
618} 458}
619 459
620static void omap1_clk_disable(struct clk *clk) 460void omap1_clk_disable(struct clk *clk)
621{ 461{
622 if (clk->usecount > 0 && !(--clk->usecount)) { 462 if (clk->usecount > 0 && !(--clk->usecount)) {
623 clk->ops->disable(clk); 463 clk->ops->disable(clk);
@@ -672,12 +512,70 @@ static void omap1_clk_disable_generic(struct clk *clk)
672 } 512 }
673} 513}
674 514
675static const struct clkops clkops_generic = { 515const struct clkops clkops_generic = {
676 .enable = &omap1_clk_enable_generic, 516 .enable = omap1_clk_enable_generic,
677 .disable = &omap1_clk_disable_generic, 517 .disable = omap1_clk_disable_generic,
518};
519
520static int omap1_clk_enable_dsp_domain(struct clk *clk)
521{
522 int retval;
523
524 retval = omap1_clk_enable(api_ck_p);
525 if (!retval) {
526 retval = omap1_clk_enable_generic(clk);
527 omap1_clk_disable(api_ck_p);
528 }
529
530 return retval;
531}
532
533static void omap1_clk_disable_dsp_domain(struct clk *clk)
534{
535 if (omap1_clk_enable(api_ck_p) == 0) {
536 omap1_clk_disable_generic(clk);
537 omap1_clk_disable(api_ck_p);
538 }
539}
540
541const struct clkops clkops_dspck = {
542 .enable = omap1_clk_enable_dsp_domain,
543 .disable = omap1_clk_disable_dsp_domain,
544};
545
546static int omap1_clk_enable_uart_functional(struct clk *clk)
547{
548 int ret;
549 struct uart_clk *uclk;
550
551 ret = omap1_clk_enable_generic(clk);
552 if (ret == 0) {
553 /* Set smart idle acknowledgement mode */
554 uclk = (struct uart_clk *)clk;
555 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
556 uclk->sysc_addr);
557 }
558
559 return ret;
560}
561
562static void omap1_clk_disable_uart_functional(struct clk *clk)
563{
564 struct uart_clk *uclk;
565
566 /* Set force idle acknowledgement mode */
567 uclk = (struct uart_clk *)clk;
568 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
569
570 omap1_clk_disable_generic(clk);
571}
572
573const struct clkops clkops_uart = {
574 .enable = omap1_clk_enable_uart_functional,
575 .disable = omap1_clk_disable_uart_functional,
678}; 576};
679 577
680static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) 578long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
681{ 579{
682 if (clk->flags & RATE_FIXED) 580 if (clk->flags & RATE_FIXED)
683 return clk->rate; 581 return clk->rate;
@@ -688,7 +586,7 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
688 return clk->rate; 586 return clk->rate;
689} 587}
690 588
691static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) 589int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
692{ 590{
693 int ret = -EINVAL; 591 int ret = -EINVAL;
694 592
@@ -703,7 +601,7 @@ static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
703 601
704#ifdef CONFIG_OMAP_RESET_CLOCKS 602#ifdef CONFIG_OMAP_RESET_CLOCKS
705 603
706static void __init omap1_clk_disable_unused(struct clk *clk) 604void __init omap1_clk_disable_unused(struct clk *clk)
707{ 605{
708 __u32 regval32; 606 __u32 regval32;
709 607
@@ -724,184 +622,9 @@ static void __init omap1_clk_disable_unused(struct clk *clk)
724 if ((regval32 & (1 << clk->enable_bit)) == 0) 622 if ((regval32 & (1 << clk->enable_bit)) == 0)
725 return; 623 return;
726 624
727 /* FIXME: This clock seems to be necessary but no-one
728 * has asked for its activation. */
729 if (clk == &tc2_ck /* FIX: pm.c (SRAM), CCP, Camera */
730 || clk == &ck_dpll1out.clk /* FIX: SoSSI, SSR */
731 || clk == &arm_gpio_ck /* FIX: GPIO code for 1510 */
732 ) {
733 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
734 clk->name);
735 return;
736 }
737
738 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); 625 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
739 clk->ops->disable(clk); 626 clk->ops->disable(clk);
740 printk(" done\n"); 627 printk(" done\n");
741} 628}
742 629
743#else
744#define omap1_clk_disable_unused NULL
745#endif 630#endif
746
747static struct clk_functions omap1_clk_functions = {
748 .clk_enable = omap1_clk_enable,
749 .clk_disable = omap1_clk_disable,
750 .clk_round_rate = omap1_clk_round_rate,
751 .clk_set_rate = omap1_clk_set_rate,
752 .clk_disable_unused = omap1_clk_disable_unused,
753};
754
755int __init omap1_clk_init(void)
756{
757 struct omap_clk *c;
758 const struct omap_clock_config *info;
759 int crystal_type = 0; /* Default 12 MHz */
760 u32 reg, cpu_mask;
761
762#ifdef CONFIG_DEBUG_LL
763 /* Resets some clocks that may be left on from bootloader,
764 * but leaves serial clocks on.
765 */
766 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
767#endif
768
769 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
770 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
771 omap_writew(reg, SOFT_REQ_REG);
772 if (!cpu_is_omap15xx())
773 omap_writew(0, SOFT_REQ_REG2);
774
775 clk_init(&omap1_clk_functions);
776
777 /* By default all idlect1 clocks are allowed to idle */
778 arm_idlect1_mask = ~0;
779
780 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
781 clk_preinit(c->lk.clk);
782
783 cpu_mask = 0;
784 if (cpu_is_omap16xx())
785 cpu_mask |= CK_16XX;
786 if (cpu_is_omap1510())
787 cpu_mask |= CK_1510;
788 if (cpu_is_omap7xx())
789 cpu_mask |= CK_7XX;
790 if (cpu_is_omap310())
791 cpu_mask |= CK_310;
792
793 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
794 if (c->cpu & cpu_mask) {
795 clkdev_add(&c->lk);
796 clk_register(c->lk.clk);
797 }
798
799 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
800 if (info != NULL) {
801 if (!cpu_is_omap15xx())
802 crystal_type = info->system_clock_type;
803 }
804
805#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
806 ck_ref.rate = 13000000;
807#elif defined(CONFIG_ARCH_OMAP16XX)
808 if (crystal_type == 2)
809 ck_ref.rate = 19200000;
810#endif
811
812 printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
813 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
814 omap_readw(ARM_CKCTL));
815
816 /* We want to be in syncronous scalable mode */
817 omap_writew(0x1000, ARM_SYSST);
818
819#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
820 /* Use values set by bootloader. Determine PLL rate and recalculate
821 * dependent clocks as if kernel had changed PLL or divisors.
822 */
823 {
824 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
825
826 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
827 if (pll_ctl_val & 0x10) {
828 /* PLL enabled, apply multiplier and divisor */
829 if (pll_ctl_val & 0xf80)
830 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
831 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
832 } else {
833 /* PLL disabled, apply bypass divisor */
834 switch (pll_ctl_val & 0xc) {
835 case 0:
836 break;
837 case 0x4:
838 ck_dpll1.rate /= 2;
839 break;
840 default:
841 ck_dpll1.rate /= 4;
842 break;
843 }
844 }
845 }
846#else
847 /* Find the highest supported frequency and enable it */
848 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
849 printk(KERN_ERR "System frequencies not set. Check your config.\n");
850 /* Guess sane values (60MHz) */
851 omap_writew(0x2290, DPLL_CTL);
852 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
853 ck_dpll1.rate = 60000000;
854 }
855#endif
856 propagate_rate(&ck_dpll1);
857 /* Cache rates for clocks connected to ck_ref (not dpll1) */
858 propagate_rate(&ck_ref);
859 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
860 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
861 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
862 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
863 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
864
865#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
866 /* Select slicer output as OMAP input clock */
867 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
868#endif
869
870 /* Amstrad Delta wants BCLK high when inactive */
871 if (machine_is_ams_delta())
872 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
873 (1 << SDW_MCLK_INV_BIT),
874 ULPD_CLOCK_CTRL);
875
876 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
877 /* (on 730, bit 13 must not be cleared) */
878 if (cpu_is_omap7xx())
879 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
880 else
881 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
882
883 /* Put DSP/MPUI into reset until needed */
884 omap_writew(0, ARM_RSTCT1);
885 omap_writew(1, ARM_RSTCT2);
886 omap_writew(0x400, ARM_IDLECT1);
887
888 /*
889 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
890 * of the ARM_IDLECT2 register must be set to zero. The power-on
891 * default value of this bit is one.
892 */
893 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
894
895 /*
896 * Only enable those clocks we will need, let the drivers
897 * enable other clocks as necessary
898 */
899 clk_enable(&armper_ck.clk);
900 clk_enable(&armxor_ck.clk);
901 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
902
903 if (cpu_is_omap15xx())
904 clk_enable(&arm_gpio_ck);
905
906 return 0;
907}
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 13:48:13 -0400