1 files changed, 6 insertions, 8 deletions

diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 84ef70476b51..0c50df05d135 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -197,11 +197,10 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
         ref_rate = ck_ref_p->rate;
 
         for (ptr = omap1_rate_table; ptr->rate; ptr++) {
-                if (ptr->xtal != ref_rate)
+                if (!(ptr->flags & cpu_mask))
                         continue;
 
-                /* DPLL1 cannot be reprogrammed without risking system crash */
-                if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
+                if (ptr->xtal != ref_rate)
                         continue;
 
                 /* Can check only after xtal frequency check */
@@ -215,12 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
         /*
          * In most cases we should not need to reprogram DPLL.
          * Reprogramming the DPLL is tricky, it must be done from SRAM.
-         * (on 730, bit 13 must always be 1)
          */
-        if (cpu_is_omap7xx())
-                omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
-        else
-                omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
+        omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 
         /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
         ck_dpll1_p->rate = ptr->pll_rate;
@@ -290,6 +285,9 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
         highest_rate = -EINVAL;
 
         for (ptr = omap1_rate_table; ptr->rate; ptr++) {
+                if (!(ptr->flags & cpu_mask))
+                        continue;
+
                 if (ptr->xtal != ref_rate)
                         continue;