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Diffstat (limited to 'arch/arm/mach-ns9xxx/board-a9m9750dev.c')
-rw-r--r--arch/arm/mach-ns9xxx/board-a9m9750dev.c49
1 files changed, 31 insertions, 18 deletions
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
index 7fa3fb1f08ef..0f65177f9e5f 100644
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
@@ -45,7 +45,13 @@ static void a9m9750dev_fpga_ack_irq(unsigned int irq)
45 45
46static void a9m9750dev_fpga_mask_irq(unsigned int irq) 46static void a9m9750dev_fpga_mask_irq(unsigned int irq)
47{ 47{
48 FPGA_IER &= ~(1 << (irq - FPGA_IRQ(0))); 48 u8 ier;
49
50 ier = __raw_readb(FPGA_IER);
51
52 ier &= ~(1 << (irq - FPGA_IRQ(0)));
53
54 __raw_writeb(ier, FPGA_IER);
49} 55}
50 56
51static void a9m9750dev_fpga_maskack_irq(unsigned int irq) 57static void a9m9750dev_fpga_maskack_irq(unsigned int irq)
@@ -56,7 +62,13 @@ static void a9m9750dev_fpga_maskack_irq(unsigned int irq)
56 62
57static void a9m9750dev_fpga_unmask_irq(unsigned int irq) 63static void a9m9750dev_fpga_unmask_irq(unsigned int irq)
58{ 64{
59 FPGA_IER |= 1 << (irq - FPGA_IRQ(0)); 65 u8 ier;
66
67 ier = __raw_readb(FPGA_IER);
68
69 ier |= 1 << (irq - FPGA_IRQ(0));
70
71 __raw_writeb(ier, FPGA_IER);
60} 72}
61 73
62static struct irq_chip a9m9750dev_fpga_chip = { 74static struct irq_chip a9m9750dev_fpga_chip = {
@@ -69,7 +81,7 @@ static struct irq_chip a9m9750dev_fpga_chip = {
69static void a9m9750dev_fpga_demux_handler(unsigned int irq, 81static void a9m9750dev_fpga_demux_handler(unsigned int irq,
70 struct irq_desc *desc) 82 struct irq_desc *desc)
71{ 83{
72 int stat = FPGA_ISR; 84 u8 stat = __raw_readb(FPGA_ISR);
73 85
74 desc->chip->mask_ack(irq); 86 desc->chip->mask_ack(irq);
75 87
@@ -89,7 +101,7 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq,
89 101
90void __init board_a9m9750dev_init_irq(void) 102void __init board_a9m9750dev_init_irq(void)
91{ 103{
92 u32 reg; 104 u32 eic;
93 int i; 105 int i;
94 106
95 if (gpio_request(11, "board a9m9750dev extirq2") == 0) 107 if (gpio_request(11, "board a9m9750dev extirq2") == 0)
@@ -105,10 +117,10 @@ void __init board_a9m9750dev_init_irq(void)
105 } 117 }
106 118
107 /* IRQ_EXT2: level sensitive + active low */ 119 /* IRQ_EXT2: level sensitive + active low */
108 reg = SYS_EIC(2); 120 eic = __raw_readl(SYS_EIC(2));
109 REGSET(reg, SYS_EIC, PLTY, AL); 121 REGSET(eic, SYS_EIC, PLTY, AL);
110 REGSET(reg, SYS_EIC, LVEDG, LEVEL); 122 REGSET(eic, SYS_EIC, LVEDG, LEVEL);
111 SYS_EIC(2) = reg; 123 __raw_writel(eic, SYS_EIC(2));
112 124
113 set_irq_chained_handler(IRQ_EXT2, 125 set_irq_chained_handler(IRQ_EXT2,
114 a9m9750dev_fpga_demux_handler); 126 a9m9750dev_fpga_demux_handler);
@@ -172,17 +184,18 @@ void __init board_a9m9750dev_init_machine(void)
172 u32 reg; 184 u32 reg;
173 185
174 /* setup static CS0: memory base ... */ 186 /* setup static CS0: memory base ... */
175 REGSETIM(SYS_SMCSSMB(0), SYS_SMCSSMB, CSxB, 187 reg = __raw_readl(SYS_SMCSSMB(0));
176 NS9XXX_CSxSTAT_PHYS(0) >> 12); 188 REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12);
189 __raw_writel(reg, SYS_SMCSSMB(0));
177 190
178 /* ... and mask */ 191 /* ... and mask */
179 reg = SYS_SMCSSMM(0); 192 reg = __raw_readl(SYS_SMCSSMM(0));
180 REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff); 193 REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff);
181 REGSET(reg, SYS_SMCSSMM, CSEx, EN); 194 REGSET(reg, SYS_SMCSSMM, CSEx, EN);
182 SYS_SMCSSMM(0) = reg; 195 __raw_writel(reg, SYS_SMCSSMM(0));
183 196
184 /* setup static CS0: memory configuration */ 197 /* setup static CS0: memory configuration */
185 reg = MEM_SMC(0); 198 reg = __raw_readl(MEM_SMC(0));
186 REGSET(reg, MEM_SMC, PSMC, OFF); 199 REGSET(reg, MEM_SMC, PSMC, OFF);
187 REGSET(reg, MEM_SMC, BSMC, OFF); 200 REGSET(reg, MEM_SMC, BSMC, OFF);
188 REGSET(reg, MEM_SMC, EW, OFF); 201 REGSET(reg, MEM_SMC, EW, OFF);
@@ -190,13 +203,13 @@ void __init board_a9m9750dev_init_machine(void)
190 REGSET(reg, MEM_SMC, PC, AL); 203 REGSET(reg, MEM_SMC, PC, AL);
191 REGSET(reg, MEM_SMC, PM, DIS); 204 REGSET(reg, MEM_SMC, PM, DIS);
192 REGSET(reg, MEM_SMC, MW, 8); 205 REGSET(reg, MEM_SMC, MW, 8);
193 MEM_SMC(0) = reg; 206 __raw_writel(reg, MEM_SMC(0));
194 207
195 /* setup static CS0: timing */ 208 /* setup static CS0: timing */
196 MEM_SMWED(0) = 0x2; 209 __raw_writel(0x2, MEM_SMWED(0));
197 MEM_SMOED(0) = 0x2; 210 __raw_writel(0x2, MEM_SMOED(0));
198 MEM_SMRD(0) = 0x6; 211 __raw_writel(0x6, MEM_SMRD(0));
199 MEM_SMWD(0) = 0x6; 212 __raw_writel(0x6, MEM_SMWD(0));
200 213
201 platform_add_devices(board_a9m9750dev_devices, 214 platform_add_devices(board_a9m9750dev_devices,
202 ARRAY_SIZE(board_a9m9750dev_devices)); 215 ARRAY_SIZE(board_a9m9750dev_devices));