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Diffstat (limited to 'arch/arm/mach-ns9xxx/board-a9m9750dev.c')
-rw-r--r--arch/arm/mach-ns9xxx/board-a9m9750dev.c199
1 files changed, 199 insertions, 0 deletions
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
new file mode 100644
index 000000000000..25289884a607
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
@@ -0,0 +1,199 @@
1/*
2 * arch/arm/mach-ns9xxx/board-a9m9750dev.c
3 *
4 * Copyright (C) 2006,2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 */
11#include <linux/platform_device.h>
12#include <linux/serial_8250.h>
13#include <linux/irq.h>
14
15#include <asm/mach/map.h>
16
17#include <asm/arch-ns9xxx/board.h>
18#include <asm/arch-ns9xxx/regs-sys.h>
19#include <asm/arch-ns9xxx/regs-mem.h>
20#include <asm/arch-ns9xxx/regs-bbu.h>
21#include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
22
23#include "board-a9m9750dev.h"
24
25static struct map_desc board_a9m9750dev_io_desc[] __initdata = {
26 { /* FPGA on CS0 */
27 .virtual = io_p2v(NS9XXX_CSxSTAT_PHYS(0)),
28 .pfn = __phys_to_pfn(NS9XXX_CSxSTAT_PHYS(0)),
29 .length = NS9XXX_CS0STAT_LENGTH,
30 .type = MT_DEVICE,
31 },
32};
33
34void __init board_a9m9750dev_map_io(void)
35{
36 iotable_init(board_a9m9750dev_io_desc,
37 ARRAY_SIZE(board_a9m9750dev_io_desc));
38}
39
40static void a9m9750dev_fpga_ack_irq(unsigned int irq)
41{
42 /* nothing */
43}
44
45static void a9m9750dev_fpga_mask_irq(unsigned int irq)
46{
47 FPGA_IER &= ~(1 << (irq - FPGA_IRQ(0)));
48}
49
50static void a9m9750dev_fpga_maskack_irq(unsigned int irq)
51{
52 a9m9750dev_fpga_mask_irq(irq);
53 a9m9750dev_fpga_ack_irq(irq);
54}
55
56static void a9m9750dev_fpga_unmask_irq(unsigned int irq)
57{
58 FPGA_IER |= 1 << (irq - FPGA_IRQ(0));
59}
60
61static struct irq_chip a9m9750dev_fpga_chip = {
62 .ack = a9m9750dev_fpga_ack_irq,
63 .mask = a9m9750dev_fpga_mask_irq,
64 .mask_ack = a9m9750dev_fpga_maskack_irq,
65 .unmask = a9m9750dev_fpga_unmask_irq,
66};
67
68static void a9m9750dev_fpga_demux_handler(unsigned int irq,
69 struct irq_desc *desc)
70{
71 int stat = FPGA_ISR;
72
73 while (stat != 0) {
74 int irqno = fls(stat) - 1;
75
76 stat &= ~(1 << irqno);
77
78 desc = irq_desc + FPGA_IRQ(irqno);
79
80 desc_handle_irq(irqno, desc);
81 }
82}
83
84void __init board_a9m9750dev_init_irq(void)
85{
86 u32 reg;
87 int i;
88
89 /*
90 * configure gpio for IRQ_EXT2
91 * use GPIO 11, because GPIO 32 is used for the LCD
92 */
93 /* XXX: proper GPIO handling */
94 BBU_GC(2) &= ~0x2000;
95
96 for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
97 set_irq_chip(i, &a9m9750dev_fpga_chip);
98 set_irq_handler(i, handle_level_irq);
99 set_irq_flags(i, IRQF_VALID);
100 }
101
102 /* IRQ_EXT2: level sensitive + active low */
103 reg = SYS_EIC(2);
104 REGSET(reg, SYS_EIC, PLTY, AL);
105 REGSET(reg, SYS_EIC, LVEDG, LEVEL);
106 SYS_EIC(2) = reg;
107
108 set_irq_chained_handler(IRQ_EXT2,
109 a9m9750dev_fpga_demux_handler);
110}
111
112static struct plat_serial8250_port board_a9m9750dev_serial8250_port[] = {
113 {
114 .iobase = FPGA_UARTA_BASE,
115 .membase = (unsigned char*)FPGA_UARTA_BASE,
116 .mapbase = FPGA_UARTA_BASE,
117 .irq = IRQ_FPGA_UARTA,
118 .iotype = UPIO_MEM,
119 .uartclk = 18432000,
120 .regshift = 0,
121 .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
122 }, {
123 .iobase = FPGA_UARTB_BASE,
124 .membase = (unsigned char*)FPGA_UARTB_BASE,
125 .mapbase = FPGA_UARTB_BASE,
126 .irq = IRQ_FPGA_UARTB,
127 .iotype = UPIO_MEM,
128 .uartclk = 18432000,
129 .regshift = 0,
130 .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
131 }, {
132 .iobase = FPGA_UARTC_BASE,
133 .membase = (unsigned char*)FPGA_UARTC_BASE,
134 .mapbase = FPGA_UARTC_BASE,
135 .irq = IRQ_FPGA_UARTC,
136 .iotype = UPIO_MEM,
137 .uartclk = 18432000,
138 .regshift = 0,
139 .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
140 }, {
141 .iobase = FPGA_UARTD_BASE,
142 .membase = (unsigned char*)FPGA_UARTD_BASE,
143 .mapbase = FPGA_UARTD_BASE,
144 .irq = IRQ_FPGA_UARTD,
145 .iotype = UPIO_MEM,
146 .uartclk = 18432000,
147 .regshift = 0,
148 .flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
149 }, {
150 /* end marker */
151 },
152};
153
154static struct platform_device board_a9m9750dev_serial_device = {
155 .name = "serial8250",
156 .dev = {
157 .platform_data = board_a9m9750dev_serial8250_port,
158 },
159};
160
161static struct platform_device *board_a9m9750dev_devices[] __initdata = {
162 &board_a9m9750dev_serial_device,
163};
164
165void __init board_a9m9750dev_init_machine(void)
166{
167 u32 reg;
168
169 /* setup static CS0: memory base ... */
170 REGSETIM(SYS_SMCSSMB(0), SYS_SMCSSMB, CSxB,
171 NS9XXX_CSxSTAT_PHYS(0) >> 12);
172
173 /* ... and mask */
174 reg = SYS_SMCSSMM(0);
175 REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff);
176 REGSET(reg, SYS_SMCSSMM, CSEx, EN);
177 SYS_SMCSSMM(0) = reg;
178
179 /* setup static CS0: memory configuration */
180 reg = MEM_SMC(0);
181 REGSET(reg, MEM_SMC, WSMC, OFF);
182 REGSET(reg, MEM_SMC, BSMC, OFF);
183 REGSET(reg, MEM_SMC, EW, OFF);
184 REGSET(reg, MEM_SMC, PB, 1);
185 REGSET(reg, MEM_SMC, PC, AL);
186 REGSET(reg, MEM_SMC, PM, DIS);
187 REGSET(reg, MEM_SMC, MW, 8);
188 MEM_SMC(0) = reg;
189
190 /* setup static CS0: timing */
191 MEM_SMWED(0) = 0x2;
192 MEM_SMOED(0) = 0x2;
193 MEM_SMRD(0) = 0x6;
194 MEM_SMWD(0) = 0x6;
195
196 platform_add_devices(board_a9m9750dev_devices,
197 ARRAY_SIZE(board_a9m9750dev_devices));
198}
199
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