diff options
Diffstat (limited to 'arch/arm/mach-ns9xxx/board-a9m9750dev.c')
-rw-r--r-- | arch/arm/mach-ns9xxx/board-a9m9750dev.c | 156 |
1 files changed, 0 insertions, 156 deletions
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c deleted file mode 100644 index e27687d53504..000000000000 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ /dev/null | |||
@@ -1,156 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-ns9xxx/board-a9m9750dev.c | ||
3 | * | ||
4 | * Copyright (C) 2006,2007 by Digi International Inc. | ||
5 | * All rights reserved. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License version 2 as published by | ||
9 | * the Free Software Foundation. | ||
10 | */ | ||
11 | #include <linux/irq.h> | ||
12 | |||
13 | #include <asm/mach/map.h> | ||
14 | #include <asm/gpio.h> | ||
15 | |||
16 | #include <mach/board.h> | ||
17 | #include <mach/processor-ns9360.h> | ||
18 | #include <mach/regs-sys-ns9360.h> | ||
19 | #include <mach/regs-mem.h> | ||
20 | #include <mach/regs-bbu.h> | ||
21 | #include <mach/regs-board-a9m9750dev.h> | ||
22 | |||
23 | #include "board-a9m9750dev.h" | ||
24 | |||
25 | static struct map_desc board_a9m9750dev_io_desc[] __initdata = { | ||
26 | { /* FPGA on CS0 */ | ||
27 | .virtual = io_p2v(NS9XXX_CSxSTAT_PHYS(0)), | ||
28 | .pfn = __phys_to_pfn(NS9XXX_CSxSTAT_PHYS(0)), | ||
29 | .length = NS9XXX_CS0STAT_LENGTH, | ||
30 | .type = MT_DEVICE, | ||
31 | }, | ||
32 | }; | ||
33 | |||
34 | void __init board_a9m9750dev_map_io(void) | ||
35 | { | ||
36 | iotable_init(board_a9m9750dev_io_desc, | ||
37 | ARRAY_SIZE(board_a9m9750dev_io_desc)); | ||
38 | } | ||
39 | |||
40 | static void a9m9750dev_fpga_ack_irq(struct irq_data *d) | ||
41 | { | ||
42 | /* nothing */ | ||
43 | } | ||
44 | |||
45 | static void a9m9750dev_fpga_mask_irq(struct irq_data *d) | ||
46 | { | ||
47 | u8 ier; | ||
48 | |||
49 | ier = __raw_readb(FPGA_IER); | ||
50 | |||
51 | ier &= ~(1 << (d->irq - FPGA_IRQ(0))); | ||
52 | |||
53 | __raw_writeb(ier, FPGA_IER); | ||
54 | } | ||
55 | |||
56 | static void a9m9750dev_fpga_maskack_irq(struct irq_data *d) | ||
57 | { | ||
58 | a9m9750dev_fpga_mask_irq(d); | ||
59 | a9m9750dev_fpga_ack_irq(d); | ||
60 | } | ||
61 | |||
62 | static void a9m9750dev_fpga_unmask_irq(struct irq_data *d) | ||
63 | { | ||
64 | u8 ier; | ||
65 | |||
66 | ier = __raw_readb(FPGA_IER); | ||
67 | |||
68 | ier |= 1 << (d->irq - FPGA_IRQ(0)); | ||
69 | |||
70 | __raw_writeb(ier, FPGA_IER); | ||
71 | } | ||
72 | |||
73 | static struct irq_chip a9m9750dev_fpga_chip = { | ||
74 | .irq_ack = a9m9750dev_fpga_ack_irq, | ||
75 | .irq_mask = a9m9750dev_fpga_mask_irq, | ||
76 | .irq_mask_ack = a9m9750dev_fpga_maskack_irq, | ||
77 | .irq_unmask = a9m9750dev_fpga_unmask_irq, | ||
78 | }; | ||
79 | |||
80 | static void a9m9750dev_fpga_demux_handler(unsigned int irq, | ||
81 | struct irq_desc *desc) | ||
82 | { | ||
83 | u8 stat = __raw_readb(FPGA_ISR); | ||
84 | |||
85 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | ||
86 | |||
87 | while (stat != 0) { | ||
88 | int irqno = fls(stat) - 1; | ||
89 | |||
90 | stat &= ~(1 << irqno); | ||
91 | |||
92 | generic_handle_irq(FPGA_IRQ(irqno)); | ||
93 | } | ||
94 | |||
95 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | ||
96 | } | ||
97 | |||
98 | void __init board_a9m9750dev_init_irq(void) | ||
99 | { | ||
100 | u32 eic; | ||
101 | int i; | ||
102 | |||
103 | if (gpio_request(11, "board a9m9750dev extirq2") == 0) | ||
104 | ns9360_gpio_configure(11, 0, 1); | ||
105 | else | ||
106 | printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n", | ||
107 | __func__); | ||
108 | |||
109 | for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { | ||
110 | irq_set_chip_and_handler(i, &a9m9750dev_fpga_chip, | ||
111 | handle_level_irq); | ||
112 | set_irq_flags(i, IRQF_VALID); | ||
113 | } | ||
114 | |||
115 | /* IRQ_NS9XXX_EXT2: level sensitive + active low */ | ||
116 | eic = __raw_readl(SYS_EIC(2)); | ||
117 | REGSET(eic, SYS_EIC, PLTY, AL); | ||
118 | REGSET(eic, SYS_EIC, LVEDG, LEVEL); | ||
119 | __raw_writel(eic, SYS_EIC(2)); | ||
120 | |||
121 | irq_set_chained_handler(IRQ_NS9XXX_EXT2, | ||
122 | a9m9750dev_fpga_demux_handler); | ||
123 | } | ||
124 | |||
125 | void __init board_a9m9750dev_init_machine(void) | ||
126 | { | ||
127 | u32 reg; | ||
128 | |||
129 | /* setup static CS0: memory base ... */ | ||
130 | reg = __raw_readl(SYS_SMCSSMB(0)); | ||
131 | REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12); | ||
132 | __raw_writel(reg, SYS_SMCSSMB(0)); | ||
133 | |||
134 | /* ... and mask */ | ||
135 | reg = __raw_readl(SYS_SMCSSMM(0)); | ||
136 | REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff); | ||
137 | REGSET(reg, SYS_SMCSSMM, CSEx, EN); | ||
138 | __raw_writel(reg, SYS_SMCSSMM(0)); | ||
139 | |||
140 | /* setup static CS0: memory configuration */ | ||
141 | reg = __raw_readl(MEM_SMC(0)); | ||
142 | REGSET(reg, MEM_SMC, PSMC, OFF); | ||
143 | REGSET(reg, MEM_SMC, BSMC, OFF); | ||
144 | REGSET(reg, MEM_SMC, EW, OFF); | ||
145 | REGSET(reg, MEM_SMC, PB, 1); | ||
146 | REGSET(reg, MEM_SMC, PC, AL); | ||
147 | REGSET(reg, MEM_SMC, PM, DIS); | ||
148 | REGSET(reg, MEM_SMC, MW, 8); | ||
149 | __raw_writel(reg, MEM_SMC(0)); | ||
150 | |||
151 | /* setup static CS0: timing */ | ||
152 | __raw_writel(0x2, MEM_SMWED(0)); | ||
153 | __raw_writel(0x2, MEM_SMOED(0)); | ||
154 | __raw_writel(0x6, MEM_SMRD(0)); | ||
155 | __raw_writel(0x6, MEM_SMWD(0)); | ||
156 | } | ||