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1 files changed, 455 insertions, 0 deletions
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
new file mode 100644
index 000000000000..dbc04747b691
--- /dev/null
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
@@ -0,0 +1,455 @@
1/*
2 * Freescale CLKCTRL Register Definitions
3 *
4 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
5 * Copyright 2008-2010 Freescale Semiconductor, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 * This file is created by xml file. Don't Edit it.
22 *
23 * Xml Revision: 1.48
24 * Template revision: 26195
25 */
26
27#ifndef __REGS_CLKCTRL_MX23_H__
28#define __REGS_CLKCTRL_MX23_H__
29
30
31#define HW_CLKCTRL_PLLCTRL0 (0x00000000)
32#define HW_CLKCTRL_PLLCTRL0_SET (0x00000004)
33#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
34#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
35
36#define BP_CLKCTRL_PLLCTRL0_RSRVD6 30
37#define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xC0000000
38#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \
39 (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6)
40#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28
41#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000
42#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \
43 (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL)
44#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0
45#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1
46#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2
47#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
48#define BP_CLKCTRL_PLLCTRL0_RSRVD5 26
49#define BM_CLKCTRL_PLLCTRL0_RSRVD5 0x0C000000
50#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) \
51 (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5)
52#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24
53#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000
54#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \
55 (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL)
56#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0
57#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1
58#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2
59#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
60#define BP_CLKCTRL_PLLCTRL0_RSRVD4 22
61#define BM_CLKCTRL_PLLCTRL0_RSRVD4 0x00C00000
62#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) \
63 (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4)
64#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20
65#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000
66#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \
67 (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL)
68#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0
69#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1
70#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2
71#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
72#define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x00080000
73#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
74#define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x00020000
75#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000
76#define BP_CLKCTRL_PLLCTRL0_RSRVD1 0
77#define BM_CLKCTRL_PLLCTRL0_RSRVD1 0x0000FFFF
78#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) \
79 (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1)
80
81#define HW_CLKCTRL_PLLCTRL1 (0x00000010)
82
83#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000
84#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000
85#define BP_CLKCTRL_PLLCTRL1_RSRVD1 16
86#define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3FFF0000
87#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) \
88 (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1)
89#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0
90#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF
91#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \
92 (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT)
93
94#define HW_CLKCTRL_CPU (0x00000020)
95#define HW_CLKCTRL_CPU_SET (0x00000024)
96#define HW_CLKCTRL_CPU_CLR (0x00000028)
97#define HW_CLKCTRL_CPU_TOG (0x0000002c)
98
99#define BP_CLKCTRL_CPU_RSRVD5 30
100#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
101#define BF_CLKCTRL_CPU_RSRVD5(v) \
102 (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
103#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
104#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
105#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
106#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
107#define BP_CLKCTRL_CPU_DIV_XTAL 16
108#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
109#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
110 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
111#define BP_CLKCTRL_CPU_RSRVD3 13
112#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
113#define BF_CLKCTRL_CPU_RSRVD3(v) \
114 (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
115#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
116#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
117#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
118#define BP_CLKCTRL_CPU_RSRVD1 6
119#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
120#define BF_CLKCTRL_CPU_RSRVD1(v) \
121 (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
122#define BP_CLKCTRL_CPU_DIV_CPU 0
123#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
124#define BF_CLKCTRL_CPU_DIV_CPU(v) \
125 (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
126
127#define HW_CLKCTRL_HBUS (0x00000030)
128#define HW_CLKCTRL_HBUS_SET (0x00000034)
129#define HW_CLKCTRL_HBUS_CLR (0x00000038)
130#define HW_CLKCTRL_HBUS_TOG (0x0000003c)
131
132#define BP_CLKCTRL_HBUS_RSRVD4 30
133#define BM_CLKCTRL_HBUS_RSRVD4 0xC0000000
134#define BF_CLKCTRL_HBUS_RSRVD4(v) \
135 (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4)
136#define BM_CLKCTRL_HBUS_BUSY 0x20000000
137#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000
138#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000
139#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
140#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
141#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
142#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
143#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
144#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
145#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000
146#define BM_CLKCTRL_HBUS_RSRVD2 0x00080000
147#define BP_CLKCTRL_HBUS_SLOW_DIV 16
148#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
149#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
150 (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
151#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
152#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
153#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
154#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
155#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
156#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
157#define BP_CLKCTRL_HBUS_RSRVD1 6
158#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
159#define BF_CLKCTRL_HBUS_RSRVD1(v) \
160 (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
161#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
162#define BP_CLKCTRL_HBUS_DIV 0
163#define BM_CLKCTRL_HBUS_DIV 0x0000001F
164#define BF_CLKCTRL_HBUS_DIV(v) \
165 (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
166
167#define HW_CLKCTRL_XBUS (0x00000040)
168
169#define BM_CLKCTRL_XBUS_BUSY 0x80000000
170#define BP_CLKCTRL_XBUS_RSRVD1 11
171#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF800
172#define BF_CLKCTRL_XBUS_RSRVD1(v) \
173 (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1)
174#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
175#define BP_CLKCTRL_XBUS_DIV 0
176#define BM_CLKCTRL_XBUS_DIV 0x000003FF
177#define BF_CLKCTRL_XBUS_DIV(v) \
178 (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
179
180#define HW_CLKCTRL_XTAL (0x00000050)
181#define HW_CLKCTRL_XTAL_SET (0x00000054)
182#define HW_CLKCTRL_XTAL_CLR (0x00000058)
183#define HW_CLKCTRL_XTAL_TOG (0x0000005c)
184
185#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31
186#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
187#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30
188#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000
189#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
190#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
191#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
192#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000
193#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
194#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
195#define BP_CLKCTRL_XTAL_RSRVD1 2
196#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
197#define BF_CLKCTRL_XTAL_RSRVD1(v) \
198 (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
199#define BP_CLKCTRL_XTAL_DIV_UART 0
200#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
201#define BF_CLKCTRL_XTAL_DIV_UART(v) \
202 (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
203
204#define HW_CLKCTRL_PIX (0x00000060)
205
206#define BP_CLKCTRL_PIX_CLKGATE 31
207#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
208#define BM_CLKCTRL_PIX_RSRVD2 0x40000000
209#define BM_CLKCTRL_PIX_BUSY 0x20000000
210#define BP_CLKCTRL_PIX_RSRVD1 13
211#define BM_CLKCTRL_PIX_RSRVD1 0x1FFFE000
212#define BF_CLKCTRL_PIX_RSRVD1(v) \
213 (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1)
214#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000
215#define BP_CLKCTRL_PIX_DIV 0
216#define BM_CLKCTRL_PIX_DIV 0x00000FFF
217#define BF_CLKCTRL_PIX_DIV(v) \
218 (((v) << 0) & BM_CLKCTRL_PIX_DIV)
219
220#define HW_CLKCTRL_SSP (0x00000070)
221
222#define BP_CLKCTRL_SSP_CLKGATE 31
223#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
224#define BM_CLKCTRL_SSP_RSRVD2 0x40000000
225#define BM_CLKCTRL_SSP_BUSY 0x20000000
226#define BP_CLKCTRL_SSP_RSRVD1 10
227#define BM_CLKCTRL_SSP_RSRVD1 0x1FFFFC00
228#define BF_CLKCTRL_SSP_RSRVD1(v) \
229 (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1)
230#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200
231#define BP_CLKCTRL_SSP_DIV 0
232#define BM_CLKCTRL_SSP_DIV 0x000001FF
233#define BF_CLKCTRL_SSP_DIV(v) \
234 (((v) << 0) & BM_CLKCTRL_SSP_DIV)
235
236#define HW_CLKCTRL_GPMI (0x00000080)
237
238#define BP_CLKCTRL_GPMI_CLKGATE 31
239#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
240#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
241#define BM_CLKCTRL_GPMI_BUSY 0x20000000
242#define BP_CLKCTRL_GPMI_RSRVD1 11
243#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
244#define BF_CLKCTRL_GPMI_RSRVD1(v) \
245 (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
246#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
247#define BP_CLKCTRL_GPMI_DIV 0
248#define BM_CLKCTRL_GPMI_DIV 0x000003FF
249#define BF_CLKCTRL_GPMI_DIV(v) \
250 (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
251
252#define HW_CLKCTRL_SPDIF (0x00000090)
253
254#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
255#define BP_CLKCTRL_SPDIF_RSRVD 0
256#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
257#define BF_CLKCTRL_SPDIF_RSRVD(v) \
258 (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
259
260#define HW_CLKCTRL_EMI (0x000000a0)
261
262#define BP_CLKCTRL_EMI_CLKGATE 31
263#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
264#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000
265#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
266#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
267#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
268#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
269#define BP_CLKCTRL_EMI_RSRVD3 18
270#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
271#define BF_CLKCTRL_EMI_RSRVD3(v) \
272 (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
273#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
274#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
275#define BP_CLKCTRL_EMI_RSRVD2 12
276#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
277#define BF_CLKCTRL_EMI_RSRVD2(v) \
278 (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
279#define BP_CLKCTRL_EMI_DIV_XTAL 8
280#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
281#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
282 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
283#define BP_CLKCTRL_EMI_RSRVD1 6
284#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
285#define BF_CLKCTRL_EMI_RSRVD1(v) \
286 (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
287#define BP_CLKCTRL_EMI_DIV_EMI 0
288#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
289#define BF_CLKCTRL_EMI_DIV_EMI(v) \
290 (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
291
292#define HW_CLKCTRL_IR (0x000000b0)
293
294#define BM_CLKCTRL_IR_CLKGATE 0x80000000
295#define BM_CLKCTRL_IR_RSRVD3 0x40000000
296#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000
297#define BM_CLKCTRL_IR_IR_BUSY 0x10000000
298#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
299#define BP_CLKCTRL_IR_RSRVD2 25
300#define BM_CLKCTRL_IR_RSRVD2 0x06000000
301#define BF_CLKCTRL_IR_RSRVD2(v) \
302 (((v) << 25) & BM_CLKCTRL_IR_RSRVD2)
303#define BP_CLKCTRL_IR_IROV_DIV 16
304#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000
305#define BF_CLKCTRL_IR_IROV_DIV(v) \
306 (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
307#define BP_CLKCTRL_IR_RSRVD1 10
308#define BM_CLKCTRL_IR_RSRVD1 0x0000FC00
309#define BF_CLKCTRL_IR_RSRVD1(v) \
310 (((v) << 10) & BM_CLKCTRL_IR_RSRVD1)
311#define BP_CLKCTRL_IR_IR_DIV 0
312#define BM_CLKCTRL_IR_IR_DIV 0x000003FF
313#define BF_CLKCTRL_IR_IR_DIV(v) \
314 (((v) << 0) & BM_CLKCTRL_IR_IR_DIV)
315
316#define HW_CLKCTRL_SAIF (0x000000c0)
317
318#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
319#define BM_CLKCTRL_SAIF_RSRVD2 0x40000000
320#define BM_CLKCTRL_SAIF_BUSY 0x20000000
321#define BP_CLKCTRL_SAIF_RSRVD1 17
322#define BM_CLKCTRL_SAIF_RSRVD1 0x1FFE0000
323#define BF_CLKCTRL_SAIF_RSRVD1(v) \
324 (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1)
325#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000
326#define BP_CLKCTRL_SAIF_DIV 0
327#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF
328#define BF_CLKCTRL_SAIF_DIV(v) \
329 (((v) << 0) & BM_CLKCTRL_SAIF_DIV)
330
331#define HW_CLKCTRL_TV (0x000000d0)
332
333#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000
334#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000
335#define BP_CLKCTRL_TV_RSRVD 0
336#define BM_CLKCTRL_TV_RSRVD 0x3FFFFFFF
337#define BF_CLKCTRL_TV_RSRVD(v) \
338 (((v) << 0) & BM_CLKCTRL_TV_RSRVD)
339
340#define HW_CLKCTRL_ETM (0x000000e0)
341
342#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
343#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
344#define BM_CLKCTRL_ETM_BUSY 0x20000000
345#define BP_CLKCTRL_ETM_RSRVD1 7
346#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF80
347#define BF_CLKCTRL_ETM_RSRVD1(v) \
348 (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1)
349#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040
350#define BP_CLKCTRL_ETM_DIV 0
351#define BM_CLKCTRL_ETM_DIV 0x0000003F
352#define BF_CLKCTRL_ETM_DIV(v) \
353 (((v) << 0) & BM_CLKCTRL_ETM_DIV)
354
355#define HW_CLKCTRL_FRAC (0x000000f0)
356#define HW_CLKCTRL_FRAC_SET (0x000000f4)
357#define HW_CLKCTRL_FRAC_CLR (0x000000f8)
358#define HW_CLKCTRL_FRAC_TOG (0x000000fc)
359
360#define BP_CLKCTRL_FRAC_CLKGATEIO 31
361#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000
362#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000
363#define BP_CLKCTRL_FRAC_IOFRAC 24
364#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000
365#define BF_CLKCTRL_FRAC_IOFRAC(v) \
366 (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC)
367#define BP_CLKCTRL_FRAC_CLKGATEPIX 23
368#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
369#define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000
370#define BP_CLKCTRL_FRAC_PIXFRAC 16
371#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
372#define BF_CLKCTRL_FRAC_PIXFRAC(v) \
373 (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC)
374#define BP_CLKCTRL_FRAC_CLKGATEEMI 15
375#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000
376#define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000
377#define BP_CLKCTRL_FRAC_EMIFRAC 8
378#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
379#define BF_CLKCTRL_FRAC_EMIFRAC(v) \
380 (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC)
381#define BP_CLKCTRL_FRAC_CLKGATECPU 7
382#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080
383#define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040
384#define BP_CLKCTRL_FRAC_CPUFRAC 0
385#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F
386#define BF_CLKCTRL_FRAC_CPUFRAC(v) \
387 (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC)
388
389#define HW_CLKCTRL_FRAC1 (0x00000100)
390#define HW_CLKCTRL_FRAC1_SET (0x00000104)
391#define HW_CLKCTRL_FRAC1_CLR (0x00000108)
392#define HW_CLKCTRL_FRAC1_TOG (0x0000010c)
393
394#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000
395#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000
396#define BP_CLKCTRL_FRAC1_RSRVD1 0
397#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF
398#define BF_CLKCTRL_FRAC1_RSRVD1(v) \
399 (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1)
400
401#define HW_CLKCTRL_CLKSEQ (0x00000110)
402#define HW_CLKCTRL_CLKSEQ_SET (0x00000114)
403#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118)
404#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c)
405
406#define BP_CLKCTRL_CLKSEQ_RSRVD1 9
407#define BM_CLKCTRL_CLKSEQ_RSRVD1 0xFFFFFE00
408#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
409 (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1)
410#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
411#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
412#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
413#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
414#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
415#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
416#define BM_CLKCTRL_CLKSEQ_RSRVD0 0x00000004
417#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
418#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
419
420#define HW_CLKCTRL_RESET (0x00000120)
421
422#define BP_CLKCTRL_RESET_RSRVD 2
423#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFFC
424#define BF_CLKCTRL_RESET_RSRVD(v) \
425 (((v) << 2) & BM_CLKCTRL_RESET_RSRVD)
426#define BM_CLKCTRL_RESET_CHIP 0x00000002
427#define BM_CLKCTRL_RESET_DIG 0x00000001
428
429#define HW_CLKCTRL_STATUS (0x00000130)
430
431#define BP_CLKCTRL_STATUS_CPU_LIMIT 30
432#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
433#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
434 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
435#define BP_CLKCTRL_STATUS_RSRVD 0
436#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
437#define BF_CLKCTRL_STATUS_RSRVD(v) \
438 (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
439
440#define HW_CLKCTRL_VERSION (0x00000140)
441
442#define BP_CLKCTRL_VERSION_MAJOR 24
443#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000
444#define BF_CLKCTRL_VERSION_MAJOR(v) \
445 (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
446#define BP_CLKCTRL_VERSION_MINOR 16
447#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000
448#define BF_CLKCTRL_VERSION_MINOR(v) \
449 (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
450#define BP_CLKCTRL_VERSION_STEP 0
451#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
452#define BF_CLKCTRL_VERSION_STEP(v) \
453 (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
454
455#endif /* __REGS_CLKCTRL_MX23_H__ */