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diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
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1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_MX23_H__
20#define __MACH_MX23_H__
21
22#include <mach/mxs.h>
23
24/*
25 * OCRAM
26 */
27#define MX23_OCRAM_BASE_ADDR 0x00000000
28#define MX23_OCRAM_SIZE SZ_32K
29
30/*
31 * IO
32 */
33#define MX23_IO_BASE_ADDR 0x80000000
34#define MX23_IO_SIZE SZ_1M
35
36#define MX23_ICOLL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x000000)
37#define MX23_APBH_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x004000)
38#define MX23_BCH_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00a000)
39#define MX23_GPMI_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00c000)
40#define MX23_SSP1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x010000)
41#define MX23_PINCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x018000)
42#define MX23_DIGCTL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x01c000)
43#define MX23_ETM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x020000)
44#define MX23_APBX_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x024000)
45#define MX23_DCP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x028000)
46#define MX23_PXP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02a000)
47#define MX23_OCOTP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02c000)
48#define MX23_AXI_AHB0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02e000)
49#define MX23_LCDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x030000)
50#define MX23_SSP2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x034000)
51#define MX23_TVENC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x038000)
52#define MX23_CLKCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x040000)
53#define MX23_SAIF0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x042000)
54#define MX23_POWER_BASE_ADDR (MX23_IO_BASE_ADDR + 0x044000)
55#define MX23_SAIF1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x046000)
56#define MX23_AUDIOOUT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x048000)
57#define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000)
58#define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000)
59#define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000)
60#define MX23_I2C0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000)
61#define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000)
62#define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000)
63#define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000)
64#define MX23_AUART1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06c000)
65#define MX23_AUART2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06e000)
66#define MX23_DUART_BASE_ADDR (MX23_IO_BASE_ADDR + 0x070000)
67#define MX23_USBPHY_BASE_ADDR (MX23_IO_BASE_ADDR + 0x07c000)
68#define MX23_USBCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x080000)
69#define MX23_DRAM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x0e0000)
70
71#define MX23_IO_P2V(x) MXS_IO_P2V(x)
72#define MX23_IO_ADDRESS(x) IOMEM(MX23_IO_P2V(x))
73
74/*
75 * IRQ
76 */
77#define MX23_INT_DUART 0
78#define MX23_INT_COMMS_RX 1
79#define MX23_INT_COMMS_TX 1
80#define MX23_INT_SSP2_ERROR 2
81#define MX23_INT_VDD5V 3
82#define MX23_INT_HEADPHONE_SHORT 4
83#define MX23_INT_DAC_DMA 5
84#define MX23_INT_DAC_ERROR 6
85#define MX23_INT_ADC_DMA 7
86#define MX23_INT_ADC_ERROR 8
87#define MX23_INT_SPDIF_DMA 9
88#define MX23_INT_SAIF2_DMA 9
89#define MX23_INT_SPDIF_ERROR 10
90#define MX23_INT_SAIF1_IRQ 10
91#define MX23_INT_SAIF2_IRQ 10
92#define MX23_INT_USB_CTRL 11
93#define MX23_INT_USB_WAKEUP 12
94#define MX23_INT_GPMI_DMA 13
95#define MX23_INT_SSP1_DMA 14
96#define MX23_INT_SSP_ERROR 15
97#define MX23_INT_GPIO0 16
98#define MX23_INT_GPIO1 17
99#define MX23_INT_GPIO2 18
100#define MX23_INT_SAIF1_DMA 19
101#define MX23_INT_SSP2_DMA 20
102#define MX23_INT_ECC8_IRQ 21
103#define MX23_INT_RTC_ALARM 22
104#define MX23_INT_UARTAPP_TX_DMA 23
105#define MX23_INT_UARTAPP_INTERNAL 24
106#define MX23_INT_UARTAPP_RX_DMA 25
107#define MX23_INT_I2C_DMA 26
108#define MX23_INT_I2C_ERROR 27
109#define MX23_INT_TIMER0 28
110#define MX23_INT_TIMER1 29
111#define MX23_INT_TIMER2 30
112#define MX23_INT_TIMER3 31
113#define MX23_INT_BATT_BRNOUT 32
114#define MX23_INT_VDDD_BRNOUT 33
115#define MX23_INT_VDDIO_BRNOUT 34
116#define MX23_INT_VDD18_BRNOUT 35
117#define MX23_INT_TOUCH_DETECT 36
118#define MX23_INT_LRADC_CH0 37
119#define MX23_INT_LRADC_CH1 38
120#define MX23_INT_LRADC_CH2 39
121#define MX23_INT_LRADC_CH3 40
122#define MX23_INT_LRADC_CH4 41
123#define MX23_INT_LRADC_CH5 42
124#define MX23_INT_LRADC_CH6 43
125#define MX23_INT_LRADC_CH7 44
126#define MX23_INT_LCDIF_DMA 45
127#define MX23_INT_LCDIF_ERROR 46
128#define MX23_INT_DIGCTL_DEBUG_TRAP 47
129#define MX23_INT_RTC_1MSEC 48
130#define MX23_INT_DRI_DMA 49
131#define MX23_INT_DRI_ATTENTION 50
132#define MX23_INT_GPMI_ATTENTION 51
133#define MX23_INT_IR 52
134#define MX23_INT_DCP_VMI 53
135#define MX23_INT_DCP 54
136#define MX23_INT_BCH 56
137#define MX23_INT_PXP 57
138#define MX23_INT_UARTAPP2_TX_DMA 58
139#define MX23_INT_UARTAPP2_INTERNAL 59
140#define MX23_INT_UARTAPP2_RX_DMA 60
141#define MX23_INT_VDAC_DETECT 61
142#define MX23_INT_VDD5V_DROOP 64
143#define MX23_INT_DCDC4P2_BO 65
144
145#endif /* __MACH_MX23_H__ */