diff options
Diffstat (limited to 'arch/arm/mach-mxs/clock-mx28.c')
-rw-r--r-- | arch/arm/mach-mxs/clock-mx28.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 5e489a2b2023..1ad97fed1e94 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c | |||
@@ -618,6 +618,8 @@ static struct clk_lookup lookups[] = { | |||
618 | _REGISTER_CLOCK("pll2", NULL, pll2_clk) | 618 | _REGISTER_CLOCK("pll2", NULL, pll2_clk) |
619 | _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk) | 619 | _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk) |
620 | _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk) | 620 | _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk) |
621 | _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk) | ||
622 | _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk) | ||
621 | _REGISTER_CLOCK("flexcan.0", NULL, can0_clk) | 623 | _REGISTER_CLOCK("flexcan.0", NULL, can0_clk) |
622 | _REGISTER_CLOCK("flexcan.1", NULL, can1_clk) | 624 | _REGISTER_CLOCK("flexcan.1", NULL, can1_clk) |
623 | _REGISTER_CLOCK(NULL, "usb0", usb0_clk) | 625 | _REGISTER_CLOCK(NULL, "usb0", usb0_clk) |
@@ -737,6 +739,15 @@ static int clk_misc_init(void) | |||
737 | reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; | 739 | reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; |
738 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); | 740 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); |
739 | 741 | ||
742 | /* | ||
743 | * 480 MHz seems too high to be ssp clock source directly, | ||
744 | * so set frac0 to get a 288 MHz ref_io0. | ||
745 | */ | ||
746 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0); | ||
747 | reg &= ~BM_CLKCTRL_FRAC0_IO0FRAC; | ||
748 | reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC; | ||
749 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0); | ||
750 | |||
740 | return 0; | 751 | return 0; |
741 | } | 752 | } |
742 | 753 | ||
@@ -744,6 +755,13 @@ int __init mx28_clocks_init(void) | |||
744 | { | 755 | { |
745 | clk_misc_init(); | 756 | clk_misc_init(); |
746 | 757 | ||
758 | /* | ||
759 | * source ssp clock from ref_io0 than ref_xtal, | ||
760 | * as ref_xtal only provides 24 MHz as maximum. | ||
761 | */ | ||
762 | clk_set_parent(&ssp0_clk, &ref_io0_clk); | ||
763 | clk_set_parent(&ssp1_clk, &ref_io0_clk); | ||
764 | |||
747 | clk_enable(&cpu_clk); | 765 | clk_enable(&cpu_clk); |
748 | clk_enable(&hbus_clk); | 766 | clk_enable(&hbus_clk); |
749 | clk_enable(&xbus_clk); | 767 | clk_enable(&xbus_clk); |