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-rw-r--r--arch/arm/mach-mxc91231/Kconfig11
-rw-r--r--arch/arm/mach-mxc91231/Makefile2
-rw-r--r--arch/arm/mach-mxc91231/Makefile.boot3
-rw-r--r--arch/arm/mach-mxc91231/clock.c642
-rw-r--r--arch/arm/mach-mxc91231/crm_regs.h399
-rw-r--r--arch/arm/mach-mxc91231/devices.c251
-rw-r--r--arch/arm/mach-mxc91231/devices.h13
-rw-r--r--arch/arm/mach-mxc91231/iomux.c177
-rw-r--r--arch/arm/mach-mxc91231/magx-zn5.c63
-rw-r--r--arch/arm/mach-mxc91231/mm.c94
-rw-r--r--arch/arm/mach-mxc91231/system.c51
11 files changed, 1706 insertions, 0 deletions
diff --git a/arch/arm/mach-mxc91231/Kconfig b/arch/arm/mach-mxc91231/Kconfig
new file mode 100644
index 000000000000..8e5fa38ebb67
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Kconfig
@@ -0,0 +1,11 @@
1if ARCH_MXC91231
2
3comment "MXC91231 platforms:"
4
5config MACH_MAGX_ZN5
6 bool "Support Motorola Zn5 GSM phone"
7 default n
8 help
9 Include support for Motorola Zn5 GSM phone.
10
11endif
diff --git a/arch/arm/mach-mxc91231/Makefile b/arch/arm/mach-mxc91231/Makefile
new file mode 100644
index 000000000000..011d5e197125
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Makefile
@@ -0,0 +1,2 @@
1obj-y := mm.o clock.o devices.o system.o iomux.o
2obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o
diff --git a/arch/arm/mach-mxc91231/Makefile.boot b/arch/arm/mach-mxc91231/Makefile.boot
new file mode 100644
index 000000000000..9939a19d99a1
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x90008000
2params_phys-y := 0x90000100
3initrd_phys-y := 0x90800000
diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c
new file mode 100644
index 000000000000..ecfa37fef8ad
--- /dev/null
+++ b/arch/arm/mach-mxc91231/clock.c
@@ -0,0 +1,642 @@
1#include <linux/clk.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/io.h>
5
6#include <mach/clock.h>
7#include <mach/hardware.h>
8#include <mach/common.h>
9
10#include <asm/clkdev.h>
11#include <asm/bug.h>
12#include <asm/div64.h>
13
14#include "crm_regs.h"
15
16#define CRM_SMALL_DIVIDER(base, name) \
17 crm_small_divider(base, \
18 base ## _ ## name ## _OFFSET, \
19 base ## _ ## name ## _MASK)
20#define CRM_1DIVIDER(base, name) \
21 crm_divider(base, \
22 base ## _ ## name ## _OFFSET, \
23 base ## _ ## name ## _MASK, 1)
24#define CRM_16DIVIDER(base, name) \
25 crm_divider(base, \
26 base ## _ ## name ## _OFFSET, \
27 base ## _ ## name ## _MASK, 16)
28
29static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask)
30{
31 static const u32 crm_small_dividers[] = {
32 2, 3, 4, 5, 6, 8, 10, 12
33 };
34 u8 idx;
35
36 idx = (__raw_readl(reg) & mask) >> offset;
37 if (idx > 7)
38 return 1;
39
40 return crm_small_dividers[idx];
41}
42
43static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z)
44{
45 u32 div;
46 div = (__raw_readl(reg) & mask) >> offset;
47 return div ? div : z;
48}
49
50static int _clk_1bit_enable(struct clk *clk)
51{
52 u32 reg;
53
54 reg = __raw_readl(clk->enable_reg);
55 reg |= 1 << clk->enable_shift;
56 __raw_writel(reg, clk->enable_reg);
57
58 return 0;
59}
60
61static void _clk_1bit_disable(struct clk *clk)
62{
63 u32 reg;
64
65 reg = __raw_readl(clk->enable_reg);
66 reg &= ~(1 << clk->enable_shift);
67 __raw_writel(reg, clk->enable_reg);
68}
69
70static int _clk_3bit_enable(struct clk *clk)
71{
72 u32 reg;
73
74 reg = __raw_readl(clk->enable_reg);
75 reg |= 0x7 << clk->enable_shift;
76 __raw_writel(reg, clk->enable_reg);
77
78 return 0;
79}
80
81static void _clk_3bit_disable(struct clk *clk)
82{
83 u32 reg;
84
85 reg = __raw_readl(clk->enable_reg);
86 reg &= ~(0x7 << clk->enable_shift);
87 __raw_writel(reg, clk->enable_reg);
88}
89
90static unsigned long ckih_rate;
91
92static unsigned long clk_ckih_get_rate(struct clk *clk)
93{
94 return ckih_rate;
95}
96
97static struct clk ckih_clk = {
98 .get_rate = clk_ckih_get_rate,
99};
100
101static unsigned long clk_ckih_x2_get_rate(struct clk *clk)
102{
103 return 2 * clk_get_rate(clk->parent);
104}
105
106static struct clk ckih_x2_clk = {
107 .parent = &ckih_clk,
108 .get_rate = clk_ckih_x2_get_rate,
109};
110
111static unsigned long clk_ckil_get_rate(struct clk *clk)
112{
113 return CKIL_CLK_FREQ;
114}
115
116static struct clk ckil_clk = {
117 .get_rate = clk_ckil_get_rate,
118};
119
120/* plls stuff */
121static struct clk mcu_pll_clk;
122static struct clk dsp_pll_clk;
123static struct clk usb_pll_clk;
124
125static struct clk *pll_clk(u8 sel)
126{
127 switch (sel) {
128 case 0:
129 return &mcu_pll_clk;
130 case 1:
131 return &dsp_pll_clk;
132 case 2:
133 return &usb_pll_clk;
134 }
135 BUG();
136}
137
138static void __iomem *pll_base(struct clk *clk)
139{
140 if (clk == &mcu_pll_clk)
141 return MXC_PLL0_BASE;
142 else if (clk == &dsp_pll_clk)
143 return MXC_PLL1_BASE;
144 else if (clk == &usb_pll_clk)
145 return MXC_PLL2_BASE;
146 BUG();
147}
148
149static unsigned long clk_pll_get_rate(struct clk *clk)
150{
151 const void __iomem *pllbase;
152 unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi;
153 long mfn, mfn_abs, mfd, pdf;
154 s64 temp;
155 pllbase = pll_base(clk);
156
157 pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
158 if (pll_hfsm == 0) {
159 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
160 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
161 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
162 } else {
163 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
164 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
165 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
166 }
167
168 pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
169 mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK;
170 mfi = (mfi <= 5) ? 5 : mfi;
171 mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
172 mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
173 mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);
174
175 if (mfn < 0)
176 mfn_abs = -mfn;
177 else
178 mfn_abs = mfn;
179
180/* XXX: actually this asumes that ckih is fed to pll, but spec says
181 * that ckih_x2 is also possible. need to check this out.
182 */
183 ref_clk = clk_get_rate(&ckih_clk);
184
185 ref_clk *= 2;
186 ref_clk /= pdf + 1;
187
188 temp = (u64) ref_clk * mfn_abs;
189 do_div(temp, mfd);
190 if (mfn < 0)
191 temp = -temp;
192 temp += ref_clk * mfi;
193
194 return temp;
195}
196
197static int clk_pll_enable(struct clk *clk)
198{
199 void __iomem *ctl;
200 u32 reg;
201
202 ctl = pll_base(clk);
203 reg = __raw_readl(ctl);
204 reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
205 __raw_writel(reg, ctl);
206 do {
207 reg = __raw_readl(ctl);
208 } while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
209 return 0;
210}
211
212static void clk_pll_disable(struct clk *clk)
213{
214 void __iomem *ctl;
215 u32 reg;
216
217 ctl = pll_base(clk);
218 reg = __raw_readl(ctl);
219 reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
220 __raw_writel(reg, ctl);
221}
222
223static struct clk mcu_pll_clk = {
224 .parent = &ckih_clk,
225 .get_rate = clk_pll_get_rate,
226 .enable = clk_pll_enable,
227 .disable = clk_pll_disable,
228};
229
230static struct clk dsp_pll_clk = {
231 .parent = &ckih_clk,
232 .get_rate = clk_pll_get_rate,
233 .enable = clk_pll_enable,
234 .disable = clk_pll_disable,
235};
236
237static struct clk usb_pll_clk = {
238 .parent = &ckih_clk,
239 .get_rate = clk_pll_get_rate,
240 .enable = clk_pll_enable,
241 .disable = clk_pll_disable,
242};
243/* plls stuff end */
244
245/* ap_ref_clk stuff */
246static struct clk ap_ref_clk;
247
248static unsigned long clk_ap_ref_get_rate(struct clk *clk)
249{
250 u32 ascsr, acsr;
251 u8 ap_pat_ref_div_2, ap_isel, acs, ads;
252
253 ascsr = __raw_readl(MXC_CRMAP_ASCSR);
254 acsr = __raw_readl(MXC_CRMAP_ACSR);
255
256 /* 0 for ckih, 1 for ckih*2 */
257 ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL;
258 /* reg divider */
259 ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1;
260 /* undocumented, 1 for disabling divider */
261 ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1;
262 /* 0 for pat_ref, 1 for divider out */
263 acs = acsr & MXC_CRMAP_ACSR_ACS;
264
265 if (acs & !ads)
266 /* use divided clock */
267 return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1);
268
269 return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1);
270}
271
272static struct clk ap_ref_clk = {
273 .parent = &ckih_clk,
274 .get_rate = clk_ap_ref_get_rate,
275};
276/* ap_ref_clk stuff end */
277
278/* ap_pre_dfs_clk stuff */
279static struct clk ap_pre_dfs_clk;
280
281static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk)
282{
283 u32 acsr, ascsr;
284
285 acsr = __raw_readl(MXC_CRMAP_ACSR);
286 ascsr = __raw_readl(MXC_CRMAP_ASCSR);
287
288 if (acsr & MXC_CRMAP_ACSR_ACS) {
289 u8 sel;
290 sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >>
291 MXC_CRMAP_ASCSR_APSEL_OFFSET;
292 return clk_get_rate(pll_clk(sel)) /
293 CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV);
294 }
295 return clk_get_rate(&ap_ref_clk);
296}
297
298static struct clk ap_pre_dfs_clk = {
299 .get_rate = clk_ap_pre_dfs_get_rate,
300};
301/* ap_pre_dfs_clk stuff end */
302
303/* usb_clk stuff */
304static struct clk usb_clk;
305
306static struct clk *clk_usb_parent(struct clk *clk)
307{
308 u32 acsr, ascsr;
309
310 acsr = __raw_readl(MXC_CRMAP_ACSR);
311 ascsr = __raw_readl(MXC_CRMAP_ASCSR);
312
313 if (acsr & MXC_CRMAP_ACSR_ACS) {
314 u8 sel;
315 sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >>
316 MXC_CRMAP_ASCSR_USBSEL_OFFSET;
317 return pll_clk(sel);
318 }
319 return &ap_ref_clk;
320}
321
322static unsigned long clk_usb_get_rate(struct clk *clk)
323{
324 return clk_get_rate(clk->parent) /
325 CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV);
326}
327
328static struct clk usb_clk = {
329 .enable_reg = MXC_CRMAP_ACDER2,
330 .enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET,
331 .get_rate = clk_usb_get_rate,
332 .enable = _clk_1bit_enable,
333 .disable = _clk_1bit_disable,
334};
335/* usb_clk stuff end */
336
337static unsigned long clk_ipg_get_rate(struct clk *clk)
338{
339 return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV);
340}
341
342static unsigned long clk_ahb_get_rate(struct clk *clk)
343{
344 return clk_get_rate(clk->parent) /
345 CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV);
346}
347
348static struct clk ipg_clk = {
349 .parent = &ap_pre_dfs_clk,
350 .get_rate = clk_ipg_get_rate,
351};
352
353static struct clk ahb_clk = {
354 .parent = &ap_pre_dfs_clk,
355 .get_rate = clk_ahb_get_rate,
356};
357
358/* perclk_clk stuff */
359static struct clk perclk_clk;
360
361static unsigned long clk_perclk_get_rate(struct clk *clk)
362{
363 u32 acder2;
364
365 acder2 = __raw_readl(MXC_CRMAP_ACDER2);
366 if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK)
367 return 2 * clk_get_rate(clk->parent);
368
369 return clk_get_rate(clk->parent);
370}
371
372static struct clk perclk_clk = {
373 .parent = &ckih_clk,
374 .get_rate = clk_perclk_get_rate,
375};
376/* perclk_clk stuff end */
377
378/* uart_clk stuff */
379static struct clk uart_clk[];
380
381static unsigned long clk_uart_get_rate(struct clk *clk)
382{
383 u32 div;
384
385 switch (clk->id) {
386 case 0:
387 case 1:
388 div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV);
389 break;
390 case 2:
391 div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV);
392 break;
393 default:
394 BUG();
395 }
396 return clk_get_rate(clk->parent) / div;
397}
398
399static struct clk uart_clk[] = {
400 {
401 .id = 0,
402 .parent = &perclk_clk,
403 .enable_reg = MXC_CRMAP_APRA,
404 .enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET,
405 .get_rate = clk_uart_get_rate,
406 .enable = _clk_1bit_enable,
407 .disable = _clk_1bit_disable,
408 }, {
409 .id = 1,
410 .parent = &perclk_clk,
411 .enable_reg = MXC_CRMAP_APRA,
412 .enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET,
413 .get_rate = clk_uart_get_rate,
414 .enable = _clk_1bit_enable,
415 .disable = _clk_1bit_disable,
416 }, {
417 .id = 2,
418 .parent = &perclk_clk,
419 .enable_reg = MXC_CRMAP_APRA,
420 .enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET,
421 .get_rate = clk_uart_get_rate,
422 .enable = _clk_1bit_enable,
423 .disable = _clk_1bit_disable,
424 },
425};
426/* uart_clk stuff end */
427
428/* sdhc_clk stuff */
429static struct clk nfc_clk;
430
431static unsigned long clk_nfc_get_rate(struct clk *clk)
432{
433 return clk_get_rate(clk->parent) /
434 CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV);
435}
436
437static struct clk nfc_clk = {
438 .parent = &ahb_clk,
439 .enable_reg = MXC_CRMAP_ACDER2,
440 .enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET,
441 .get_rate = clk_nfc_get_rate,
442 .enable = _clk_1bit_enable,
443 .disable = _clk_1bit_disable,
444};
445/* sdhc_clk stuff end */
446
447/* sdhc_clk stuff */
448static struct clk sdhc_clk[];
449
450static struct clk *clk_sdhc_parent(struct clk *clk)
451{
452 u32 aprb;
453 u8 sel;
454 u32 mask;
455 int offset;
456
457 aprb = __raw_readl(MXC_CRMAP_APRB);
458
459 switch (clk->id) {
460 case 0:
461 mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK;
462 offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET;
463 break;
464 case 1:
465 mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK;
466 offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET;
467 break;
468 default:
469 BUG();
470 }
471 sel = (aprb & mask) >> offset;
472
473 switch (sel) {
474 case 0:
475 return &ckih_clk;
476 case 1:
477 return &ckih_x2_clk;
478 }
479 return &usb_clk;
480}
481
482static unsigned long clk_sdhc_get_rate(struct clk *clk)
483{
484 u32 div;
485
486 switch (clk->id) {
487 case 0:
488 div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV);
489 break;
490 case 1:
491 div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV);
492 break;
493 default:
494 BUG();
495 }
496
497 return clk_get_rate(clk->parent) / div;
498}
499
500static int clk_sdhc_enable(struct clk *clk)
501{
502 u32 amlpmre1, aprb;
503
504 amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
505 aprb = __raw_readl(MXC_CRMAP_APRB);
506 switch (clk->id) {
507 case 0:
508 amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
509 aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
510 break;
511 case 1:
512 amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
513 aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
514 break;
515 }
516 __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
517 __raw_writel(aprb, MXC_CRMAP_APRB);
518 return 0;
519}
520
521static void clk_sdhc_disable(struct clk *clk)
522{
523 u32 amlpmre1, aprb;
524
525 amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
526 aprb = __raw_readl(MXC_CRMAP_APRB);
527 switch (clk->id) {
528 case 0:
529 amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
530 aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
531 break;
532 case 1:
533 amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
534 aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
535 break;
536 }
537 __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
538 __raw_writel(aprb, MXC_CRMAP_APRB);
539}
540
541static struct clk sdhc_clk[] = {
542 {
543 .id = 0,
544 .get_rate = clk_sdhc_get_rate,
545 .enable = clk_sdhc_enable,
546 .disable = clk_sdhc_disable,
547 }, {
548 .id = 1,
549 .get_rate = clk_sdhc_get_rate,
550 .enable = clk_sdhc_enable,
551 .disable = clk_sdhc_disable,
552 },
553};
554/* sdhc_clk stuff end */
555
556/* wdog_clk stuff */
557static struct clk wdog_clk[] = {
558 {
559 .id = 0,
560 .parent = &ipg_clk,
561 .enable_reg = MXC_CRMAP_AMLPMRD,
562 .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET,
563 .enable = _clk_3bit_enable,
564 .disable = _clk_3bit_disable,
565 }, {
566 .id = 1,
567 .parent = &ipg_clk,
568 .enable_reg = MXC_CRMAP_AMLPMRD,
569 .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET,
570 .enable = _clk_3bit_enable,
571 .disable = _clk_3bit_disable,
572 },
573};
574/* wdog_clk stuff end */
575
576/* gpt_clk stuff */
577static struct clk gpt_clk = {
578 .parent = &ipg_clk,
579 .enable_reg = MXC_CRMAP_AMLPMRC,
580 .enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET,
581 .enable = _clk_3bit_enable,
582 .disable = _clk_3bit_disable,
583};
584/* gpt_clk stuff end */
585
586/* cspi_clk stuff */
587static struct clk cspi_clk[] = {
588 {
589 .id = 0,
590 .parent = &ipg_clk,
591 .enable_reg = MXC_CRMAP_AMLPMRE2,
592 .enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET,
593 .enable = _clk_3bit_enable,
594 .disable = _clk_3bit_disable,
595 }, {
596 .id = 1,
597 .parent = &ipg_clk,
598 .enable_reg = MXC_CRMAP_AMLPMRE1,
599 .enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET,
600 .enable = _clk_3bit_enable,
601 .disable = _clk_3bit_disable,
602 },
603};
604/* cspi_clk stuff end */
605
606#define _REGISTER_CLOCK(d, n, c) \
607 { \
608 .dev_id = d, \
609 .con_id = n, \
610 .clk = &c, \
611 },
612
613static struct clk_lookup lookups[] = {
614 _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
615 _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
616 _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
617 _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0])
618 _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1])
619 _REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0])
620 _REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0])
621 _REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1])
622};
623
624int __init mxc91231_clocks_init(unsigned long fref)
625{
626 void __iomem *gpt_base;
627 int i;
628
629 ckih_rate = fref;
630
631 usb_clk.parent = clk_usb_parent(&usb_clk);
632 sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
633 sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
634
635 for (i = 0; i < ARRAY_SIZE(lookups); i++)
636 clkdev_add(&lookups[i]);
637
638 gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
639 mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
640
641 return 0;
642}
diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
new file mode 100644
index 000000000000..ce4f59058189
--- /dev/null
+++ b/arch/arm/mach-mxc91231/crm_regs.h
@@ -0,0 +1,399 @@
1/*
2 * Copyright 2006 Freescale Semiconductor, Inc.
3 * Copyright 2006-2007 Motorola, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
22#define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
23
24#define CKIL_CLK_FREQ 32768
25
26#define MXC_CRM_AP_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR)
27#define MXC_CRM_COM_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR)
28#define MXC_DSM_BASE MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR)
29#define MXC_PLL0_BASE MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR)
30#define MXC_PLL1_BASE MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR)
31#define MXC_PLL2_BASE MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR)
32#define MXC_CLKCTL_BASE MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR)
33
34/* PLL Register Offsets */
35#define MXC_PLL_DP_CTL 0x00
36#define MXC_PLL_DP_CONFIG 0x04
37#define MXC_PLL_DP_OP 0x08
38#define MXC_PLL_DP_MFD 0x0C
39#define MXC_PLL_DP_MFN 0x10
40#define MXC_PLL_DP_HFS_OP 0x1C
41#define MXC_PLL_DP_HFS_MFD 0x20
42#define MXC_PLL_DP_HFS_MFN 0x24
43
44/* PLL Register Bit definitions */
45#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
46#define MXC_PLL_DP_CTL_ADE 0x800
47#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
48#define MXC_PLL_DP_CTL_HFSM 0x80
49#define MXC_PLL_DP_CTL_PRE 0x40
50#define MXC_PLL_DP_CTL_UPEN 0x20
51#define MXC_PLL_DP_CTL_RST 0x10
52#define MXC_PLL_DP_CTL_RCP 0x8
53#define MXC_PLL_DP_CTL_PLM 0x4
54#define MXC_PLL_DP_CTL_BRM0 0x2
55#define MXC_PLL_DP_CTL_LRF 0x1
56
57#define MXC_PLL_DP_OP_MFI_OFFSET 4
58#define MXC_PLL_DP_OP_MFI_MASK 0xF
59#define MXC_PLL_DP_OP_PDF_OFFSET 0
60#define MXC_PLL_DP_OP_PDF_MASK 0xF
61
62#define MXC_PLL_DP_MFD_OFFSET 0
63#define MXC_PLL_DP_MFD_MASK 0x7FFFFFF
64
65#define MXC_PLL_DP_MFN_OFFSET 0
66#define MXC_PLL_DP_MFN_MASK 0x7FFFFFF
67
68/* CRM AP Register Offsets */
69#define MXC_CRMAP_ASCSR (MXC_CRM_AP_BASE + 0x00)
70#define MXC_CRMAP_ACDR (MXC_CRM_AP_BASE + 0x04)
71#define MXC_CRMAP_ACDER1 (MXC_CRM_AP_BASE + 0x08)
72#define MXC_CRMAP_ACDER2 (MXC_CRM_AP_BASE + 0x0C)
73#define MXC_CRMAP_ACGCR (MXC_CRM_AP_BASE + 0x10)
74#define MXC_CRMAP_ACCGCR (MXC_CRM_AP_BASE + 0x14)
75#define MXC_CRMAP_AMLPMRA (MXC_CRM_AP_BASE + 0x18)
76#define MXC_CRMAP_AMLPMRB (MXC_CRM_AP_BASE + 0x1C)
77#define MXC_CRMAP_AMLPMRC (MXC_CRM_AP_BASE + 0x20)
78#define MXC_CRMAP_AMLPMRD (MXC_CRM_AP_BASE + 0x24)
79#define MXC_CRMAP_AMLPMRE1 (MXC_CRM_AP_BASE + 0x28)
80#define MXC_CRMAP_AMLPMRE2 (MXC_CRM_AP_BASE + 0x2C)
81#define MXC_CRMAP_AMLPMRF (MXC_CRM_AP_BASE + 0x30)
82#define MXC_CRMAP_AMLPMRG (MXC_CRM_AP_BASE + 0x34)
83#define MXC_CRMAP_APGCR (MXC_CRM_AP_BASE + 0x38)
84#define MXC_CRMAP_ACSR (MXC_CRM_AP_BASE + 0x3C)
85#define MXC_CRMAP_ADCR (MXC_CRM_AP_BASE + 0x40)
86#define MXC_CRMAP_ACR (MXC_CRM_AP_BASE + 0x44)
87#define MXC_CRMAP_AMCR (MXC_CRM_AP_BASE + 0x48)
88#define MXC_CRMAP_APCR (MXC_CRM_AP_BASE + 0x4C)
89#define MXC_CRMAP_AMORA (MXC_CRM_AP_BASE + 0x50)
90#define MXC_CRMAP_AMORB (MXC_CRM_AP_BASE + 0x54)
91#define MXC_CRMAP_AGPR (MXC_CRM_AP_BASE + 0x58)
92#define MXC_CRMAP_APRA (MXC_CRM_AP_BASE + 0x5C)
93#define MXC_CRMAP_APRB (MXC_CRM_AP_BASE + 0x60)
94#define MXC_CRMAP_APOR (MXC_CRM_AP_BASE + 0x64)
95#define MXC_CRMAP_ADFMR (MXC_CRM_AP_BASE + 0x68)
96
97/* CRM AP Register Bit definitions */
98#define MXC_CRMAP_ASCSR_CRS 0x10000
99#define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET 15
100#define MXC_CRMAP_ASCSR_AP_PATREF_DIV2 0x8000
101#define MXC_CRMAP_ASCSR_USBSEL_OFFSET 13
102#define MXC_CRMAP_ASCSR_USBSEL_MASK (0x3 << 13)
103#define MXC_CRMAP_ASCSR_CSISEL_OFFSET 11
104#define MXC_CRMAP_ASCSR_CSISEL_MASK (0x3 << 11)
105#define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET 7
106#define MXC_CRMAP_ASCSR_SSI2SEL_MASK (0x3 << 7)
107#define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET 5
108#define MXC_CRMAP_ASCSR_SSI1SEL_MASK (0x3 << 5)
109#define MXC_CRMAP_ASCSR_APSEL_OFFSET 3
110#define MXC_CRMAP_ASCSR_APSEL_MASK (0x3 << 3)
111#define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET 2
112#define MXC_CRMAP_ASCSR_AP_PATREF_DIV1 0x4
113#define MXC_CRMAP_ASCSR_APISEL 0x1
114
115#define MXC_CRMAP_ACDR_ARMDIV_OFFSET 8
116#define MXC_CRMAP_ACDR_ARMDIV_MASK (0xF << 8)
117#define MXC_CRMAP_ACDR_AHBDIV_OFFSET 4
118#define MXC_CRMAP_ACDR_AHBDIV_MASK (0xF << 4)
119#define MXC_CRMAP_ACDR_IPDIV_OFFSET 0
120#define MXC_CRMAP_ACDR_IPDIV_MASK 0xF
121
122#define MXC_CRMAP_ACDER1_CSIEN_OFFSET 30
123#define MXC_CRMAP_ACDER1_CSIDIV_OFFSET 24
124#define MXC_CRMAP_ACDER1_CSIDIV_MASK (0x3F << 24)
125#define MXC_CRMAP_ACDER1_SSI2EN_OFFSET 14
126#define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET 8
127#define MXC_CRMAP_ACDER1_SSI2DIV_MASK (0x3F << 8)
128#define MXC_CRMAP_ACDER1_SSI1EN_OFFSET 6
129#define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET 0
130#define MXC_CRMAP_ACDER1_SSI1DIV_MASK 0x3F
131
132#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET 24
133#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK (0x7 << 24)
134#define MXC_CRMAP_ACDER2_NFCEN_OFFSET 20
135#define MXC_CRMAP_ACDER2_NFCDIV_OFFSET 16
136#define MXC_CRMAP_ACDER2_NFCDIV_MASK (0xF << 16)
137#define MXC_CRMAP_ACDER2_USBEN_OFFSET 12
138#define MXC_CRMAP_ACDER2_USBDIV_OFFSET 8
139#define MXC_CRMAP_ACDER2_USBDIV_MASK (0xF << 8)
140#define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET 5
141#define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK (0x3 << 5)
142#define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET 0
143#define MXC_CRMAP_ACDER2_BAUDDIV_MASK 0xF
144
145#define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET 22
146#define MXC_CRMAP_AMLPMRA_MLPMA7_MASK (0x7 << 22)
147#define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET 19
148#define MXC_CRMAP_AMLPMRA_MLPMA6_MASK (0x7 << 19)
149#define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET 12
150#define MXC_CRMAP_AMLPMRA_MLPMA4_MASK (0x7 << 12)
151#define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET 9
152#define MXC_CRMAP_AMLPMRA_MLPMA3_MASK (0x7 << 9)
153#define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET 6
154#define MXC_CRMAP_AMLPMRA_MLPMA2_MASK (0x7 << 6)
155#define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET 3
156#define MXC_CRMAP_AMLPMRA_MLPMA1_MASK (0x7 << 3)
157
158#define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET 0
159#define MXC_CRMAP_AMLPMRB_MLPMB0_MASK 0x7
160
161#define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET 28
162#define MXC_CRMAP_AMLPMRC_MLPMC9_MASK (0x7 << 28)
163#define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET 22
164#define MXC_CRMAP_AMLPMRC_MLPMC7_MASK (0x7 << 22)
165#define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET 16
166#define MXC_CRMAP_AMLPMRC_MLPMC5_MASK (0x7 << 16)
167#define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET 12
168#define MXC_CRMAP_AMLPMRC_MLPMC4_MASK (0x7 << 12)
169#define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET 9
170#define MXC_CRMAP_AMLPMRC_MLPMC3_MASK (0x7 << 9)
171#define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET 6
172#define MXC_CRMAP_AMLPMRC_MLPMC2_MASK (0x7 << 6)
173#define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET 3
174#define MXC_CRMAP_AMLPMRC_MLPMC1_MASK (0x7 << 3)
175#define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET 0
176#define MXC_CRMAP_AMLPMRC_MLPMC0_MASK 0x7
177
178#define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET 22
179#define MXC_CRMAP_AMLPMRD_MLPMD7_MASK (0x7 << 22)
180#define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET 12
181#define MXC_CRMAP_AMLPMRD_MLPMD4_MASK (0x7 << 12)
182#define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET 9
183#define MXC_CRMAP_AMLPMRD_MLPMD3_MASK (0x7 << 9)
184#define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET 6
185#define MXC_CRMAP_AMLPMRD_MLPMD2_MASK (0x7 << 6)
186#define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET 0
187#define MXC_CRMAP_AMLPMRD_MLPMD0_MASK 0x7
188
189#define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET 28
190#define MXC_CRMAP_AMLPMRE1_MLPME9_MASK (0x7 << 28)
191#define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET 25
192#define MXC_CRMAP_AMLPMRE1_MLPME8_MASK (0x7 << 25)
193#define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET 22
194#define MXC_CRMAP_AMLPMRE1_MLPME7_MASK (0x7 << 22)
195#define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET 19
196#define MXC_CRMAP_AMLPMRE1_MLPME6_MASK (0x7 << 19)
197#define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET 16
198#define MXC_CRMAP_AMLPMRE1_MLPME5_MASK (0x7 << 16)
199#define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET 12
200#define MXC_CRMAP_AMLPMRE1_MLPME4_MASK (0x7 << 12)
201#define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET 9
202#define MXC_CRMAP_AMLPMRE1_MLPME3_MASK (0x7 << 9)
203#define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET 6
204#define MXC_CRMAP_AMLPMRE1_MLPME2_MASK (0x7 << 6)
205#define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET 3
206#define MXC_CRMAP_AMLPMRE1_MLPME1_MASK (0x7 << 3)
207#define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET 0
208#define MXC_CRMAP_AMLPMRE1_MLPME0_MASK 0x7
209
210#define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET 0
211#define MXC_CRMAP_AMLPMRE2_MLPME0_MASK 0x7
212
213#define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET 19
214#define MXC_CRMAP_AMLPMRF_MLPMF6_MASK (0x7 << 19)
215#define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET 16
216#define MXC_CRMAP_AMLPMRF_MLPMF5_MASK (0x7 << 16)
217#define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET 9
218#define MXC_CRMAP_AMLPMRF_MLPMF3_MASK (0x7 << 9)
219#define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET 6
220#define MXC_CRMAP_AMLPMRF_MLPMF2_MASK (0x7 << 6)
221#define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET 3
222#define MXC_CRMAP_AMLPMRF_MLPMF1_MASK (0x7 << 3)
223#define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET 0
224#define MXC_CRMAP_AMLPMRF_MLPMF0_MASK (0x7 << 0)
225
226#define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET 28
227#define MXC_CRMAP_AMLPMRG_MLPMG9_MASK (0x7 << 28)
228#define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET 22
229#define MXC_CRMAP_AMLPMRG_MLPMG7_MASK (0x7 << 22)
230#define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET 19
231#define MXC_CRMAP_AMLPMRG_MLPMG6_MASK (0x7 << 19)
232#define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET 16
233#define MXC_CRMAP_AMLPMRG_MLPMG5_MASK (0x7 << 16)
234#define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET 12
235#define MXC_CRMAP_AMLPMRG_MLPMG4_MASK (0x7 << 12)
236#define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET 9
237#define MXC_CRMAP_AMLPMRG_MLPMG3_MASK (0x7 << 9)
238#define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET 6
239#define MXC_CRMAP_AMLPMRG_MLPMG2_MASK (0x7 << 6)
240#define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET 3
241#define MXC_CRMAP_AMLPMRG_MLPMG1_MASK (0x7 << 3)
242#define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET 0
243#define MXC_CRMAP_AMLPMRG_MLPMG0_MASK 0x7
244
245#define MXC_CRMAP_AGPR_IPUPAD_OFFSET 20
246#define MXC_CRMAP_AGPR_IPUPAD_MASK (0x7 << 20)
247
248#define MXC_CRMAP_APRA_EL1TEN_OFFSET 29
249#define MXC_CRMAP_APRA_SIMEN_OFFSET 24
250#define MXC_CRMAP_APRA_UART3DIV_OFFSET 17
251#define MXC_CRMAP_APRA_UART3DIV_MASK (0xF << 17)
252#define MXC_CRMAP_APRA_UART3EN_OFFSET 16
253#define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14
254#define MXC_CRMAP_APRA_MQSPIEN_OFFSET 13
255#define MXC_CRMAP_APRA_UART2EN_OFFSET 8
256#define MXC_CRMAP_APRA_UART1EN_OFFSET 0
257
258#define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET 13
259#define MXC_CRMAP_APRB_SDHC2_ISEL_MASK (0x7 << 13)
260#define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET 9
261#define MXC_CRMAP_APRB_SDHC2_DIV_MASK (0xF << 9)
262#define MXC_CRMAP_APRB_SDHC2EN_OFFSET 8
263#define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET 5
264#define MXC_CRMAP_APRB_SDHC1_ISEL_MASK (0x7 << 5)
265#define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET 1
266#define MXC_CRMAP_APRB_SDHC1_DIV_MASK (0xF << 1)
267#define MXC_CRMAP_APRB_SDHC1EN_OFFSET 0
268
269#define MXC_CRMAP_ACSR_ADS_OFFSET 8
270#define MXC_CRMAP_ACSR_ADS (0x1 << 8)
271#define MXC_CRMAP_ACSR_ACS 0x1
272
273#define MXC_CRMAP_ADCR_LFDF_0 (0x0 << 8)
274#define MXC_CRMAP_ADCR_LFDF_2 (0x1 << 8)
275#define MXC_CRMAP_ADCR_LFDF_4 (0x2 << 8)
276#define MXC_CRMAP_ADCR_LFDF_8 (0x3 << 8)
277#define MXC_CRMAP_ADCR_LFDF_OFFSET 8
278#define MXC_CRMAP_ADCR_LFDF_MASK (0x3 << 8)
279#define MXC_CRMAP_ADCR_ALT_PLL 0x80
280#define MXC_CRMAP_ADCR_DFS_DIVEN 0x20
281#define MXC_CRMAP_ADCR_DIV_BYP 0x2
282#define MXC_CRMAP_ADCR_VSTAT 0x8
283#define MXC_CRMAP_ADCR_TSTAT 0x10
284#define MXC_CRMAP_ADCR_DVFS_VCTRL 0x10
285#define MXC_CRMAP_ADCR_CLK_ON 0x40
286
287#define MXC_CRMAP_ADFMR_FC_OFFSET 16
288#define MXC_CRMAP_ADFMR_FC_MASK (0x1F << 16)
289#define MXC_CRMAP_ADFMR_MF_OFFSET 1
290#define MXC_CRMAP_ADFMR_MF_MASK (0x3FF << 1)
291#define MXC_CRMAP_ADFMR_DFM_CLK_READY 0x1
292#define MXC_CRMAP_ADFMR_DFM_PWR_DOWN 0x8000
293
294#define MXC_CRMAP_ACR_CKOHS_HIGH (1 << 18)
295#define MXC_CRMAP_ACR_CKOS_HIGH (1 << 16)
296#define MXC_CRMAP_ACR_CKOHS_MASK (0x7 << 12)
297#define MXC_CRMAP_ACR_CKOHD (1 << 11)
298#define MXC_CRMAP_ACR_CKOHDIV_MASK (0xF << 8)
299#define MXC_CRMAP_ACR_CKOHDIV_OFFSET 8
300#define MXC_CRMAP_ACR_CKOD (1 << 7)
301#define MXC_CRMAP_ACR_CKOS_MASK (0x7 << 4)
302
303/* AP Warm reset */
304#define MXC_CRMAP_AMCR_SW_AP (1 << 14)
305
306/* Bit definitions of ACGCR in CRM_AP for tree level clock gating */
307#define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT 0x00000001
308#define MXC_CRMAP_ACGCR_ACG0_STOP 0x00000003
309#define MXC_CRMAP_ACGCR_ACG0_RUN 0x00000007
310#define MXC_CRMAP_ACGCR_ACG0_DISABLED 0x00000000
311
312#define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT 0x00000008
313#define MXC_CRMAP_ACGCR_ACG1_STOP 0x00000018
314#define MXC_CRMAP_ACGCR_ACG1_RUN 0x00000038
315#define MXC_CRMAP_ACGCR_ACG1_DISABLED 0x00000000
316
317#define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT 0x00000040
318#define MXC_CRMAP_ACGCR_ACG2_STOP 0x000000C0
319#define MXC_CRMAP_ACGCR_ACG2_RUN 0x000001C0
320#define MXC_CRMAP_ACGCR_ACG2_DISABLED 0x00000000
321
322#define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT 0x00000200
323#define MXC_CRMAP_ACGCR_ACG3_STOP 0x00000600
324#define MXC_CRMAP_ACGCR_ACG3_RUN 0x00000E00
325#define MXC_CRMAP_ACGCR_ACG3_DISABLED 0x00000000
326
327#define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT 0x00001000
328#define MXC_CRMAP_ACGCR_ACG4_STOP 0x00003000
329#define MXC_CRMAP_ACGCR_ACG4_RUN 0x00007000
330#define MXC_CRMAP_ACGCR_ACG4_DISABLED 0x00000000
331
332#define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT 0x00010000
333#define MXC_CRMAP_ACGCR_ACG5_STOP 0x00030000
334#define MXC_CRMAP_ACGCR_ACG5_RUN 0x00070000
335#define MXC_CRMAP_ACGCR_ACG5_DISABLED 0x00000000
336
337#define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT 0x00080000
338#define MXC_CRMAP_ACGCR_ACG6_STOP 0x00180000
339#define MXC_CRMAP_ACGCR_ACG6_RUN 0x00380000
340#define MXC_CRMAP_ACGCR_ACG6_DISABLED 0x00000000
341
342#define NUM_GATE_CTRL 6
343
344/* CRM COM Register Offsets */
345#define MXC_CRMCOM_CSCR (MXC_CRM_COM_BASE + 0x0C)
346#define MXC_CRMCOM_CCCR (MXC_CRM_COM_BASE + 0x10)
347
348/* CRM COM Bit Definitions */
349#define MXC_CRMCOM_CSCR_PPD1 0x08000000
350#define MXC_CRMCOM_CSCR_CKOHSEL (1 << 18)
351#define MXC_CRMCOM_CSCR_CKOSEL (1 << 17)
352#define MXC_CRMCOM_CCCR_CC_DIV_OFFSET 8
353#define MXC_CRMCOM_CCCR_CC_DIV_MASK (0x1F << 8)
354#define MXC_CRMCOM_CCCR_CC_SEL_OFFSET 0
355#define MXC_CRMCOM_CCCR_CC_SEL_MASK 0x3
356
357/* DSM Register Offsets */
358#define MXC_DSM_SLEEP_TIME (MXC_DSM_BASE + 0x0c)
359#define MXC_DSM_CONTROL0 (MXC_DSM_BASE + 0x20)
360#define MXC_DSM_CONTROL1 (MXC_DSM_BASE + 0x24)
361#define MXC_DSM_CTREN (MXC_DSM_BASE + 0x28)
362#define MXC_DSM_WARM_PER (MXC_DSM_BASE + 0x40)
363#define MXC_DSM_LOCK_PER (MXC_DSM_BASE + 0x44)
364#define MXC_DSM_MGPER (MXC_DSM_BASE + 0x4c)
365#define MXC_DSM_CRM_CONTROL (MXC_DSM_BASE + 0x50)
366
367/* Bit definitions of various registers in DSM */
368#define MXC_DSM_CRM_CTRL_DVFS_BYP 0x00000008
369#define MXC_DSM_CRM_CTRL_DVFS_VCTRL 0x00000004
370#define MXC_DSM_CRM_CTRL_LPMD1 0x00000002
371#define MXC_DSM_CRM_CTRL_LPMD0 0x00000001
372#define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE 0x00000000
373#define MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE 0x00000001
374#define MXC_DSM_CRM_CTRL_LPMD_RUN_MODE 0x00000003
375#define MXC_DSM_CONTROL0_STBY_COMMIT_EN 0x00000200
376#define MXC_DSM_CONTROL0_MSTR_EN 0x00000001
377#define MXC_DSM_CONTROL0_RESTART 0x00000010
378/* Counter Block reset */
379#define MXC_DSM_CONTROL1_CB_RST 0x00000002
380/* State Machine reset */
381#define MXC_DSM_CONTROL1_SM_RST 0x00000004
382/* Bit needed to reset counter block */
383#define MXC_CONTROL1_RST_CNT32 0x00000008
384#define MXC_DSM_CONTROL1_RST_CNT32_EN 0x00000800
385#define MXC_DSM_CONTROL1_SLEEP 0x00000100
386#define MXC_DSM_CONTROL1_WAKEUP_DISABLE 0x00004000
387#define MXC_DSM_CTREN_CNT32 0x00000001
388
389/* Magic Fix enable bit */
390#define MXC_DSM_MGPER_EN_MGFX 0x80000000
391#define MXC_DSM_MGPER_PER_MASK 0x000003FF
392#define MXC_DSM_MGPER_PER(n) (MXC_DSM_MGPER_PER_MASK & n)
393
394/* Address offsets of the CLKCTL registers */
395#define MXC_CLKCTL_GP_CTRL (MXC_CLKCTL_BASE + 0x00)
396#define MXC_CLKCTL_GP_SER (MXC_CLKCTL_BASE + 0x04)
397#define MXC_CLKCTL_GP_CER (MXC_CLKCTL_BASE + 0x08)
398
399#endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */
diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c
new file mode 100644
index 000000000000..353bd977b393
--- /dev/null
+++ b/arch/arm/mach-mxc91231/devices.c
@@ -0,0 +1,251 @@
1/*
2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/serial.h>
23#include <linux/gpio.h>
24#include <mach/hardware.h>
25#include <mach/irqs.h>
26#include <mach/imx-uart.h>
27
28static struct resource uart0[] = {
29 {
30 .start = MXC91231_UART1_BASE_ADDR,
31 .end = MXC91231_UART1_BASE_ADDR + 0x0B5,
32 .flags = IORESOURCE_MEM,
33 }, {
34 .start = MXC91231_INT_UART1_RX,
35 .end = MXC91231_INT_UART1_RX,
36 .flags = IORESOURCE_IRQ,
37 }, {
38 .start = MXC91231_INT_UART1_TX,
39 .end = MXC91231_INT_UART1_TX,
40 .flags = IORESOURCE_IRQ,
41 }, {
42 .start = MXC91231_INT_UART1_MINT,
43 .end = MXC91231_INT_UART1_MINT,
44 .flags = IORESOURCE_IRQ,
45 },
46};
47
48struct platform_device mxc_uart_device0 = {
49 .name = "imx-uart",
50 .id = 0,
51 .resource = uart0,
52 .num_resources = ARRAY_SIZE(uart0),
53};
54
55static struct resource uart1[] = {
56 {
57 .start = MXC91231_UART2_BASE_ADDR,
58 .end = MXC91231_UART2_BASE_ADDR + 0x0B5,
59 .flags = IORESOURCE_MEM,
60 }, {
61 .start = MXC91231_INT_UART2_RX,
62 .end = MXC91231_INT_UART2_RX,
63 .flags = IORESOURCE_IRQ,
64 }, {
65 .start = MXC91231_INT_UART2_TX,
66 .end = MXC91231_INT_UART2_TX,
67 .flags = IORESOURCE_IRQ,
68 }, {
69 .start = MXC91231_INT_UART2_MINT,
70 .end = MXC91231_INT_UART2_MINT,
71 .flags = IORESOURCE_IRQ,
72 },
73};
74
75struct platform_device mxc_uart_device1 = {
76 .name = "imx-uart",
77 .id = 1,
78 .resource = uart1,
79 .num_resources = ARRAY_SIZE(uart1),
80};
81
82static struct resource uart2[] = {
83 {
84 .start = MXC91231_UART3_BASE_ADDR,
85 .end = MXC91231_UART3_BASE_ADDR + 0x0B5,
86 .flags = IORESOURCE_MEM,
87 }, {
88 .start = MXC91231_INT_UART3_RX,
89 .end = MXC91231_INT_UART3_RX,
90 .flags = IORESOURCE_IRQ,
91 }, {
92 .start = MXC91231_INT_UART3_TX,
93 .end = MXC91231_INT_UART3_TX,
94 .flags = IORESOURCE_IRQ,
95 }, {
96 .start = MXC91231_INT_UART3_MINT,
97 .end = MXC91231_INT_UART3_MINT,
98 .flags = IORESOURCE_IRQ,
99
100 },
101};
102
103struct platform_device mxc_uart_device2 = {
104 .name = "imx-uart",
105 .id = 2,
106 .resource = uart2,
107 .num_resources = ARRAY_SIZE(uart2),
108};
109
110/* GPIO port description */
111static struct mxc_gpio_port mxc_gpio_ports[] = {
112 [0] = {
113 .chip.label = "gpio-0",
114 .base = MXC91231_IO_ADDRESS(MXC91231_GPIO1_AP_BASE_ADDR),
115 .irq = MXC91231_INT_GPIO1,
116 .virtual_irq_start = MXC_GPIO_IRQ_START,
117 },
118 [1] = {
119 .chip.label = "gpio-1",
120 .base = MXC91231_IO_ADDRESS(MXC91231_GPIO2_AP_BASE_ADDR),
121 .irq = MXC91231_INT_GPIO2,
122 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
123 },
124 [2] = {
125 .chip.label = "gpio-2",
126 .base = MXC91231_IO_ADDRESS(MXC91231_GPIO3_AP_BASE_ADDR),
127 .irq = MXC91231_INT_GPIO3,
128 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
129 },
130 [3] = {
131 .chip.label = "gpio-3",
132 .base = MXC91231_IO_ADDRESS(MXC91231_GPIO4_SH_BASE_ADDR),
133 .irq = MXC91231_INT_GPIO4,
134 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
135 },
136};
137
138int __init mxc_register_gpios(void)
139{
140 return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
141}
142
143static struct resource mxc_nand_resources[] = {
144 {
145 .start = MXC91231_NFC_BASE_ADDR,
146 .end = MXC91231_NFC_BASE_ADDR + 0xfff,
147 .flags = IORESOURCE_MEM
148 }, {
149 .start = MXC91231_INT_NANDFC,
150 .end = MXC91231_INT_NANDFC,
151 .flags = IORESOURCE_IRQ
152 },
153};
154
155struct platform_device mxc_nand_device = {
156 .name = "mxc_nand",
157 .id = 0,
158 .num_resources = ARRAY_SIZE(mxc_nand_resources),
159 .resource = mxc_nand_resources,
160};
161
162static struct resource mxc_sdhc0_resources[] = {
163 {
164 .start = MXC91231_MMC_SDHC1_BASE_ADDR,
165 .end = MXC91231_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
166 .flags = IORESOURCE_MEM,
167 }, {
168 .start = MXC91231_INT_MMC_SDHC1,
169 .end = MXC91231_INT_MMC_SDHC1,
170 .flags = IORESOURCE_IRQ,
171 },
172};
173
174static struct resource mxc_sdhc1_resources[] = {
175 {
176 .start = MXC91231_MMC_SDHC2_BASE_ADDR,
177 .end = MXC91231_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
178 .flags = IORESOURCE_MEM,
179 }, {
180 .start = MXC91231_INT_MMC_SDHC2,
181 .end = MXC91231_INT_MMC_SDHC2,
182 .flags = IORESOURCE_IRQ,
183 },
184};
185
186struct platform_device mxc_sdhc_device0 = {
187 .name = "mxc-mmc",
188 .id = 0,
189 .num_resources = ARRAY_SIZE(mxc_sdhc0_resources),
190 .resource = mxc_sdhc0_resources,
191};
192
193struct platform_device mxc_sdhc_device1 = {
194 .name = "mxc-mmc",
195 .id = 1,
196 .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
197 .resource = mxc_sdhc1_resources,
198};
199
200static struct resource mxc_cspi0_resources[] = {
201 {
202 .start = MXC91231_CSPI1_BASE_ADDR,
203 .end = MXC91231_CSPI1_BASE_ADDR + 0x20,
204 .flags = IORESOURCE_MEM,
205 }, {
206 .start = MXC91231_INT_CSPI1,
207 .end = MXC91231_INT_CSPI1,
208 .flags = IORESOURCE_IRQ,
209 },
210};
211
212struct platform_device mxc_cspi_device0 = {
213 .name = "spi_imx",
214 .id = 0,
215 .num_resources = ARRAY_SIZE(mxc_cspi0_resources),
216 .resource = mxc_cspi0_resources,
217};
218
219static struct resource mxc_cspi1_resources[] = {
220 {
221 .start = MXC91231_CSPI2_BASE_ADDR,
222 .end = MXC91231_CSPI2_BASE_ADDR + 0x20,
223 .flags = IORESOURCE_MEM,
224 }, {
225 .start = MXC91231_INT_CSPI2,
226 .end = MXC91231_INT_CSPI2,
227 .flags = IORESOURCE_IRQ,
228 },
229};
230
231struct platform_device mxc_cspi_device1 = {
232 .name = "spi_imx",
233 .id = 1,
234 .num_resources = ARRAY_SIZE(mxc_cspi1_resources),
235 .resource = mxc_cspi1_resources,
236};
237
238static struct resource mxc_wdog0_resources[] = {
239 {
240 .start = MXC91231_WDOG1_BASE_ADDR,
241 .end = MXC91231_WDOG1_BASE_ADDR + 0x10,
242 .flags = IORESOURCE_MEM,
243 },
244};
245
246struct platform_device mxc_wdog_device0 = {
247 .name = "mxc-wdt",
248 .id = 0,
249 .num_resources = ARRAY_SIZE(mxc_wdog0_resources),
250 .resource = mxc_wdog0_resources,
251};
diff --git a/arch/arm/mach-mxc91231/devices.h b/arch/arm/mach-mxc91231/devices.h
new file mode 100644
index 000000000000..72a2136ce27d
--- /dev/null
+++ b/arch/arm/mach-mxc91231/devices.h
@@ -0,0 +1,13 @@
1extern struct platform_device mxc_uart_device0;
2extern struct platform_device mxc_uart_device1;
3extern struct platform_device mxc_uart_device2;
4
5extern struct platform_device mxc_nand_device;
6
7extern struct platform_device mxc_sdhc_device0;
8extern struct platform_device mxc_sdhc_device1;
9
10extern struct platform_device mxc_cspi_device0;
11extern struct platform_device mxc_cspi_device1;
12
13extern struct platform_device mxc_wdog_device0;
diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c
new file mode 100644
index 000000000000..405d9b19d891
--- /dev/null
+++ b/arch/arm/mach-mxc91231/iomux.c
@@ -0,0 +1,177 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <linux/module.h>
22#include <linux/spinlock.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <mach/hardware.h>
26#include <mach/gpio.h>
27#include <mach/iomux-mxc91231.h>
28
29/*
30 * IOMUX register (base) addresses
31 */
32#define IOMUX_AP_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_AP_BASE_ADDR)
33#define IOMUX_COM_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_COM_BASE_ADDR)
34#define IOMUXSW_AP_MUX_CTL (IOMUX_AP_BASE + 0x000)
35#define IOMUXSW_SP_MUX_CTL (IOMUX_COM_BASE + 0x000)
36#define IOMUXSW_PAD_CTL (IOMUX_COM_BASE + 0x200)
37
38#define IOMUXINT_OBS1 (IOMUX_AP_BASE + 0x600)
39#define IOMUXINT_OBS2 (IOMUX_AP_BASE + 0x004)
40
41static DEFINE_SPINLOCK(gpio_mux_lock);
42
43#define NB_PORTS ((PIN_MAX + 32) / 32)
44#define PIN_GLOBAL_NUM(pin) \
45 (((pin & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT)*PIN_AP_MAX + \
46 ((pin & MUX_REG_MASK) >> MUX_REG_SHIFT)*4 + \
47 ((pin & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT))
48
49unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
50/*
51 * set the mode for a IOMUX pin.
52 */
53int mxc_iomux_mode(const unsigned int pin_mode)
54{
55 u32 side, field, l, mode, ret = 0;
56 void __iomem *reg;
57
58 side = (pin_mode & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT;
59 switch (side) {
60 case MUX_SIDE_AP:
61 reg = IOMUXSW_AP_MUX_CTL;
62 break;
63 case MUX_SIDE_SP:
64 reg = IOMUXSW_SP_MUX_CTL;
65 break;
66 default:
67 return -EINVAL;
68 }
69 reg += ((pin_mode & MUX_REG_MASK) >> MUX_REG_SHIFT) * 4;
70 field = (pin_mode & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT;
71 mode = (pin_mode & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
72
73 spin_lock(&gpio_mux_lock);
74
75 l = __raw_readl(reg);
76 l &= ~(0xff << (field * 8));
77 l |= mode << (field * 8);
78 __raw_writel(l, reg);
79
80 spin_unlock(&gpio_mux_lock);
81
82 return ret;
83}
84EXPORT_SYMBOL(mxc_iomux_mode);
85
86/*
87 * This function configures the pad value for a IOMUX pin.
88 */
89void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
90{
91 u32 padgrp, field, l;
92 void __iomem *reg;
93
94 padgrp = (pin & MUX_PADGRP_MASK) >> MUX_PADGRP_SHIFT;
95 reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
96 field = (pin + 2) % 3;
97
98 pr_debug("%s: reg offset = 0x%x, field = %d\n",
99 __func__, (pin + 2) / 3, field);
100
101 spin_lock(&gpio_mux_lock);
102
103 l = __raw_readl(reg);
104 l &= ~(0x1ff << (field * 10));
105 l |= config << (field * 10);
106 __raw_writel(l, reg);
107
108 spin_unlock(&gpio_mux_lock);
109}
110EXPORT_SYMBOL(mxc_iomux_set_pad);
111
112/*
113 * allocs a single pin:
114 * - reserves the pin so that it is not claimed by another driver
115 * - setups the iomux according to the configuration
116 */
117int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label)
118{
119 unsigned pad = PIN_GLOBAL_NUM(pin_mode);
120 if (pad >= (PIN_MAX + 1)) {
121 printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
122 pad, label ? label : "?");
123 return -EINVAL;
124 }
125
126 if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
127 printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
128 pad, label ? label : "?");
129 return -EBUSY;
130 }
131 mxc_iomux_mode(pin_mode);
132
133 return 0;
134}
135EXPORT_SYMBOL(mxc_iomux_alloc_pin);
136
137int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
138 const char *label)
139{
140 unsigned int *p = pin_list;
141 int i;
142 int ret = -EINVAL;
143
144 for (i = 0; i < count; i++) {
145 ret = mxc_iomux_alloc_pin(*p, label);
146 if (ret)
147 goto setup_error;
148 p++;
149 }
150 return 0;
151
152setup_error:
153 mxc_iomux_release_multiple_pins(pin_list, i);
154 return ret;
155}
156EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
157
158void mxc_iomux_release_pin(const unsigned int pin_mode)
159{
160 unsigned pad = PIN_GLOBAL_NUM(pin_mode);
161
162 if (pad < (PIN_MAX + 1))
163 clear_bit(pad, mxc_pin_alloc_map);
164}
165EXPORT_SYMBOL(mxc_iomux_release_pin);
166
167void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
168{
169 unsigned int *p = pin_list;
170 int i;
171
172 for (i = 0; i < count; i++) {
173 mxc_iomux_release_pin(*p);
174 p++;
175 }
176}
177EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
new file mode 100644
index 000000000000..7dbe4ca12efd
--- /dev/null
+++ b/arch/arm/mach-mxc91231/magx-zn5.c
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
3 *
4 * This file is released under the GPLv2 or later.
5 */
6
7#include <linux/irq.h>
8#include <linux/init.h>
9#include <linux/device.h>
10
11#include <asm/mach-types.h>
12#include <asm/mach/time.h>
13#include <asm/mach/arch.h>
14
15#include <mach/common.h>
16#include <mach/hardware.h>
17#include <mach/iomux-mxc91231.h>
18#include <mach/mmc.h>
19#include <mach/imx-uart.h>
20
21#include "devices.h"
22
23static struct imxuart_platform_data uart_pdata = {
24};
25
26static struct imxmmc_platform_data sdhc_pdata = {
27};
28
29static void __init zn5_init(void)
30{
31 pm_power_off = mxc91231_power_off;
32
33 mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_DAT_VP__RXD2, "uart2-rx");
34 mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_SE0_VM__TXD2, "uart2-tx");
35
36 mxc_register_device(&mxc_uart_device1, &uart_pdata);
37 mxc_register_device(&mxc_uart_device0, &uart_pdata);
38
39 mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
40
41 mxc_register_device(&mxc_wdog_device0, NULL);
42
43 return;
44}
45
46static void __init zn5_timer_init(void)
47{
48 mxc91231_clocks_init(26000000); /* 26mhz ckih */
49}
50
51struct sys_timer zn5_timer = {
52 .init = zn5_timer_init,
53};
54
55MACHINE_START(MAGX_ZN5, "Motorola Zn5")
56 .phys_io = MXC91231_AIPS1_BASE_ADDR,
57 .io_pg_offst = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
58 .boot_params = PHYS_OFFSET + 0x100,
59 .map_io = mxc91231_map_io,
60 .init_irq = mxc91231_init_irq,
61 .timer = &zn5_timer,
62 .init_machine = zn5_init,
63MACHINE_END
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
new file mode 100644
index 000000000000..6becda3ff331
--- /dev/null
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -0,0 +1,94 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2004-2005 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MXC specific definitions
7 * Copyright 2006 Motorola, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <linux/mm.h>
26#include <linux/init.h>
27#include <mach/hardware.h>
28#include <mach/common.h>
29#include <asm/pgtable.h>
30#include <asm/mach/map.h>
31
32/*
33 * This structure defines the MXC memory map.
34 */
35static struct map_desc mxc_io_desc[] __initdata = {
36 {
37 .virtual = MXC91231_L2CC_BASE_ADDR_VIRT,
38 .pfn = __phys_to_pfn(MXC91231_L2CC_BASE_ADDR),
39 .length = MXC91231_L2CC_SIZE,
40 .type = MT_DEVICE,
41 }, {
42 .virtual = MXC91231_X_MEMC_BASE_ADDR_VIRT,
43 .pfn = __phys_to_pfn(MXC91231_X_MEMC_BASE_ADDR),
44 .length = MXC91231_X_MEMC_SIZE,
45 .type = MT_DEVICE,
46 }, {
47 .virtual = MXC91231_ROMP_BASE_ADDR_VIRT,
48 .pfn = __phys_to_pfn(MXC91231_ROMP_BASE_ADDR),
49 .length = MXC91231_ROMP_SIZE,
50 .type = MT_DEVICE,
51 }, {
52 .virtual = MXC91231_AVIC_BASE_ADDR_VIRT,
53 .pfn = __phys_to_pfn(MXC91231_AVIC_BASE_ADDR),
54 .length = MXC91231_AVIC_SIZE,
55 .type = MT_DEVICE,
56 }, {
57 .virtual = MXC91231_AIPS1_BASE_ADDR_VIRT,
58 .pfn = __phys_to_pfn(MXC91231_AIPS1_BASE_ADDR),
59 .length = MXC91231_AIPS1_SIZE,
60 .type = MT_DEVICE,
61 }, {
62 .virtual = MXC91231_SPBA0_BASE_ADDR_VIRT,
63 .pfn = __phys_to_pfn(MXC91231_SPBA0_BASE_ADDR),
64 .length = MXC91231_SPBA0_SIZE,
65 .type = MT_DEVICE,
66 }, {
67 .virtual = MXC91231_SPBA1_BASE_ADDR_VIRT,
68 .pfn = __phys_to_pfn(MXC91231_SPBA1_BASE_ADDR),
69 .length = MXC91231_SPBA1_SIZE,
70 .type = MT_DEVICE,
71 }, {
72 .virtual = MXC91231_AIPS2_BASE_ADDR_VIRT,
73 .pfn = __phys_to_pfn(MXC91231_AIPS2_BASE_ADDR),
74 .length = MXC91231_AIPS2_SIZE,
75 .type = MT_DEVICE,
76 },
77};
78
79/*
80 * This function initializes the memory map. It is called during the
81 * system startup to create static physical to virtual memory map for
82 * the IO modules.
83 */
84void __init mxc91231_map_io(void)
85{
86 mxc_set_cpu_type(MXC_CPU_MXC91231);
87
88 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
89}
90
91void __init mxc91231_init_irq(void)
92{
93 mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
94}
diff --git a/arch/arm/mach-mxc91231/system.c b/arch/arm/mach-mxc91231/system.c
new file mode 100644
index 000000000000..736f7efd874a
--- /dev/null
+++ b/arch/arm/mach-mxc91231/system.c
@@ -0,0 +1,51 @@
1/*
2 * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
3 *
4 * This file is released under the GPLv2 or later.
5 */
6
7#include <linux/delay.h>
8#include <linux/io.h>
9
10#include <asm/proc-fns.h>
11#include <mach/hardware.h>
12
13#include "crm_regs.h"
14
15#define WDOG_WCR MXC91231_IO_ADDRESS(MXC91231_WDOG1_BASE_ADDR)
16#define WDOG_WCR_OUT_ENABLE (1 << 6)
17#define WDOG_WCR_ASSERT (1 << 5)
18
19void mxc91231_power_off(void)
20{
21 u16 wcr;
22
23 wcr = __raw_readw(WDOG_WCR);
24 wcr |= WDOG_WCR_OUT_ENABLE;
25 wcr &= ~WDOG_WCR_ASSERT;
26 __raw_writew(wcr, WDOG_WCR);
27}
28
29void mxc91231_arch_reset(char mode, const char *cmd)
30{
31 u32 amcr;
32
33 /* Reset the AP using CRM */
34 amcr = __raw_readl(MXC_CRMAP_AMCR);
35 amcr &= ~MXC_CRMAP_AMCR_SW_AP;
36 __raw_writel(amcr, MXC_CRMAP_AMCR);
37
38 mdelay(10);
39 cpu_reset(0);
40}
41
42void mxc91231_prepare_idle(void)
43{
44 u32 crm_ctl;
45
46 /* Go to WAIT mode after WFI */
47 crm_ctl = __raw_readl(MXC_DSM_CRM_CONTROL);
48 crm_ctl &= ~(MXC_DSM_CRM_CTRL_LPMD0 | MXC_DSM_CRM_CTRL_LPMD1);
49 crm_ctl |= MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE;
50 __raw_writel(crm_ctl, MXC_DSM_CRM_CONTROL);
51}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 02:43:36 -0500