diff options
Diffstat (limited to 'arch/arm/mach-mx5')
-rw-r--r-- | arch/arm/mach-mx5/clock-mx51-mx53.c | 16 | ||||
-rw-r--r-- | arch/arm/mach-mx5/cpu.c | 55 | ||||
-rw-r--r-- | arch/arm/mach-mx5/mm.c | 2 |
3 files changed, 41 insertions, 32 deletions
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index ca4f9d58cfeb..344ee8ef1eef 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c | |||
@@ -780,6 +780,12 @@ static struct clk ahb_clk = { | |||
780 | .round_rate = _clk_ahb_round_rate, | 780 | .round_rate = _clk_ahb_round_rate, |
781 | }; | 781 | }; |
782 | 782 | ||
783 | static struct clk iim_clk = { | ||
784 | .parent = &ipg_clk, | ||
785 | .enable_reg = MXC_CCM_CCGR0, | ||
786 | .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, | ||
787 | }; | ||
788 | |||
783 | /* Main IP interface clock for access to registers */ | 789 | /* Main IP interface clock for access to registers */ |
784 | static struct clk ipg_clk = { | 790 | static struct clk ipg_clk = { |
785 | .parent = &ahb_clk, | 791 | .parent = &ahb_clk, |
@@ -1099,6 +1105,7 @@ static struct clk_lookup mx51_lookups[] = { | |||
1099 | _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) | 1105 | _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) |
1100 | _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) | 1106 | _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) |
1101 | _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) | 1107 | _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) |
1108 | _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) | ||
1102 | }; | 1109 | }; |
1103 | 1110 | ||
1104 | static struct clk_lookup mx53_lookups[] = { | 1111 | static struct clk_lookup mx53_lookups[] = { |
@@ -1107,6 +1114,7 @@ static struct clk_lookup mx53_lookups[] = { | |||
1107 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) | 1114 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) |
1108 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) | 1115 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) |
1109 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) | 1116 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) |
1117 | _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) | ||
1110 | }; | 1118 | }; |
1111 | 1119 | ||
1112 | static void clk_tree_init(void) | 1120 | static void clk_tree_init(void) |
@@ -1147,6 +1155,10 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, | |||
1147 | clk_enable(&cpu_clk); | 1155 | clk_enable(&cpu_clk); |
1148 | clk_enable(&main_bus_clk); | 1156 | clk_enable(&main_bus_clk); |
1149 | 1157 | ||
1158 | clk_enable(&iim_clk); | ||
1159 | mx51_revision(); | ||
1160 | clk_disable(&iim_clk); | ||
1161 | |||
1150 | /* set the usboh3_clk parent to pll2_sw_clk */ | 1162 | /* set the usboh3_clk parent to pll2_sw_clk */ |
1151 | clk_set_parent(&usboh3_clk, &pll2_sw_clk); | 1163 | clk_set_parent(&usboh3_clk, &pll2_sw_clk); |
1152 | 1164 | ||
@@ -1182,6 +1194,10 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, | |||
1182 | clk_enable(&cpu_clk); | 1194 | clk_enable(&cpu_clk); |
1183 | clk_enable(&main_bus_clk); | 1195 | clk_enable(&main_bus_clk); |
1184 | 1196 | ||
1197 | clk_enable(&iim_clk); | ||
1198 | mx53_revision(); | ||
1199 | clk_disable(&iim_clk); | ||
1200 | |||
1185 | /* System timer */ | 1201 | /* System timer */ |
1186 | mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), | 1202 | mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), |
1187 | MX53_INT_GPT); | 1203 | MX53_INT_GPT); |
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index a00d2bc7246a..d40671da4372 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c | |||
@@ -20,37 +20,18 @@ | |||
20 | 20 | ||
21 | static int cpu_silicon_rev = -1; | 21 | static int cpu_silicon_rev = -1; |
22 | 22 | ||
23 | #define SI_REV 0x48 | 23 | #define IIM_SREV 0x24 |
24 | 24 | ||
25 | static void query_silicon_parameter(void) | 25 | static int get_mx51_srev(void) |
26 | { | 26 | { |
27 | void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE); | 27 | void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); |
28 | u32 rev; | 28 | u32 rev = readl(iim_base + IIM_SREV) & 0xff; |
29 | 29 | ||
30 | if (!rom) { | 30 | if (rev == 0x0) |
31 | cpu_silicon_rev = -EINVAL; | 31 | return IMX_CHIP_REVISION_2_0; |
32 | return; | 32 | else if (rev == 0x10) |
33 | } | 33 | return IMX_CHIP_REVISION_3_0; |
34 | 34 | return 0; | |
35 | rev = readl(rom + SI_REV); | ||
36 | switch (rev) { | ||
37 | case 0x1: | ||
38 | cpu_silicon_rev = MX51_CHIP_REV_1_0; | ||
39 | break; | ||
40 | case 0x2: | ||
41 | cpu_silicon_rev = MX51_CHIP_REV_1_1; | ||
42 | break; | ||
43 | case 0x10: | ||
44 | cpu_silicon_rev = MX51_CHIP_REV_2_0; | ||
45 | break; | ||
46 | case 0x20: | ||
47 | cpu_silicon_rev = MX51_CHIP_REV_3_0; | ||
48 | break; | ||
49 | default: | ||
50 | cpu_silicon_rev = 0; | ||
51 | } | ||
52 | |||
53 | iounmap(rom); | ||
54 | } | 35 | } |
55 | 36 | ||
56 | /* | 37 | /* |
@@ -64,7 +45,7 @@ int mx51_revision(void) | |||
64 | return -EINVAL; | 45 | return -EINVAL; |
65 | 46 | ||
66 | if (cpu_silicon_rev == -1) | 47 | if (cpu_silicon_rev == -1) |
67 | query_silicon_parameter(); | 48 | cpu_silicon_rev = get_mx51_srev(); |
68 | 49 | ||
69 | return cpu_silicon_rev; | 50 | return cpu_silicon_rev; |
70 | } | 51 | } |
@@ -82,7 +63,7 @@ static int __init mx51_neon_fixup(void) | |||
82 | if (!cpu_is_mx51()) | 63 | if (!cpu_is_mx51()) |
83 | return 0; | 64 | return 0; |
84 | 65 | ||
85 | if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) { | 66 | if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) { |
86 | elf_hwcap &= ~HWCAP_NEON; | 67 | elf_hwcap &= ~HWCAP_NEON; |
87 | pr_info("Turning off NEON support, detected broken NEON implementation\n"); | 68 | pr_info("Turning off NEON support, detected broken NEON implementation\n"); |
88 | } | 69 | } |
@@ -92,6 +73,18 @@ static int __init mx51_neon_fixup(void) | |||
92 | late_initcall(mx51_neon_fixup); | 73 | late_initcall(mx51_neon_fixup); |
93 | #endif | 74 | #endif |
94 | 75 | ||
76 | static int get_mx53_srev(void) | ||
77 | { | ||
78 | void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); | ||
79 | u32 rev = readl(iim_base + IIM_SREV) & 0xff; | ||
80 | |||
81 | if (rev == 0x0) | ||
82 | return IMX_CHIP_REVISION_1_0; | ||
83 | else if (rev == 0x10) | ||
84 | return IMX_CHIP_REVISION_2_0; | ||
85 | return 0; | ||
86 | } | ||
87 | |||
95 | /* | 88 | /* |
96 | * Returns: | 89 | * Returns: |
97 | * the silicon revision of the cpu | 90 | * the silicon revision of the cpu |
@@ -103,7 +96,7 @@ int mx53_revision(void) | |||
103 | return -EINVAL; | 96 | return -EINVAL; |
104 | 97 | ||
105 | if (cpu_silicon_rev == -1) | 98 | if (cpu_silicon_rev == -1) |
106 | query_silicon_parameter(); | 99 | cpu_silicon_rev = get_mx53_srev(); |
107 | 100 | ||
108 | return cpu_silicon_rev; | 101 | return cpu_silicon_rev; |
109 | } | 102 | } |
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index cbaf282fb818..e57f96858f0d 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c | |||
@@ -68,7 +68,7 @@ void __init mx51_init_irq(void) | |||
68 | unsigned long tzic_addr; | 68 | unsigned long tzic_addr; |
69 | void __iomem *tzic_virt; | 69 | void __iomem *tzic_virt; |
70 | 70 | ||
71 | if (mx51_revision() < MX51_CHIP_REV_2_0) | 71 | if (mx51_revision() < IMX_CHIP_REVISION_2_0) |
72 | tzic_addr = MX51_TZIC_BASE_ADDR_TO1; | 72 | tzic_addr = MX51_TZIC_BASE_ADDR_TO1; |
73 | else | 73 | else |
74 | tzic_addr = MX51_TZIC_BASE_ADDR; | 74 | tzic_addr = MX51_TZIC_BASE_ADDR; |