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-rw-r--r--arch/arm/mach-mx5/clock-mx51.c825
-rw-r--r--arch/arm/mach-mx5/cpu.c47
-rw-r--r--arch/arm/mach-mx5/crm_regs.h583
-rw-r--r--arch/arm/mach-mx5/devices.c96
-rw-r--r--arch/arm/mach-mx5/devices.h4
-rw-r--r--arch/arm/mach-mx5/mm.c89
6 files changed, 1644 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
new file mode 100644
index 000000000000..be90c03101cd
--- /dev/null
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -0,0 +1,825 @@
1/*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/mm.h>
14#include <linux/delay.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17
18#include <asm/clkdev.h>
19
20#include <mach/hardware.h>
21#include <mach/common.h>
22#include <mach/clock.h>
23
24#include "crm_regs.h"
25
26/* External clock values passed-in by the board code */
27static unsigned long external_high_reference, external_low_reference;
28static unsigned long oscillator_reference, ckih2_reference;
29
30static struct clk osc_clk;
31static struct clk pll1_main_clk;
32static struct clk pll1_sw_clk;
33static struct clk pll2_sw_clk;
34static struct clk pll3_sw_clk;
35static struct clk lp_apm_clk;
36static struct clk periph_apm_clk;
37static struct clk ahb_clk;
38static struct clk ipg_clk;
39
40#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
41
42static int _clk_ccgr_enable(struct clk *clk)
43{
44 u32 reg;
45
46 reg = __raw_readl(clk->enable_reg);
47 reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift;
48 __raw_writel(reg, clk->enable_reg);
49
50 return 0;
51}
52
53static void _clk_ccgr_disable(struct clk *clk)
54{
55 u32 reg;
56 reg = __raw_readl(clk->enable_reg);
57 reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift);
58 __raw_writel(reg, clk->enable_reg);
59
60}
61
62static void _clk_ccgr_disable_inwait(struct clk *clk)
63{
64 u32 reg;
65
66 reg = __raw_readl(clk->enable_reg);
67 reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
68 reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
69 __raw_writel(reg, clk->enable_reg);
70}
71
72/*
73 * For the 4-to-1 muxed input clock
74 */
75static inline u32 _get_mux(struct clk *parent, struct clk *m0,
76 struct clk *m1, struct clk *m2, struct clk *m3)
77{
78 if (parent == m0)
79 return 0;
80 else if (parent == m1)
81 return 1;
82 else if (parent == m2)
83 return 2;
84 else if (parent == m3)
85 return 3;
86 else
87 BUG();
88
89 return -EINVAL;
90}
91
92static inline void __iomem *_get_pll_base(struct clk *pll)
93{
94 if (pll == &pll1_main_clk)
95 return MX51_DPLL1_BASE;
96 else if (pll == &pll2_sw_clk)
97 return MX51_DPLL2_BASE;
98 else if (pll == &pll3_sw_clk)
99 return MX51_DPLL3_BASE;
100 else
101 BUG();
102
103 return NULL;
104}
105
106static unsigned long clk_pll_get_rate(struct clk *clk)
107{
108 long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
109 unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
110 void __iomem *pllbase;
111 s64 temp;
112 unsigned long parent_rate;
113
114 parent_rate = clk_get_rate(clk->parent);
115
116 pllbase = _get_pll_base(clk);
117
118 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
119 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
120 dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
121
122 if (pll_hfsm == 0) {
123 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
124 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
125 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
126 } else {
127 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
128 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
129 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
130 }
131 pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
132 mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
133 mfi = (mfi <= 5) ? 5 : mfi;
134 mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
135 mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
136 /* Sign extend to 32-bits */
137 if (mfn >= 0x04000000) {
138 mfn |= 0xFC000000;
139 mfn_abs = -mfn;
140 }
141
142 ref_clk = 2 * parent_rate;
143 if (dbl != 0)
144 ref_clk *= 2;
145
146 ref_clk /= (pdf + 1);
147 temp = (u64) ref_clk * mfn_abs;
148 do_div(temp, mfd + 1);
149 if (mfn < 0)
150 temp = -temp;
151 temp = (ref_clk * mfi) + temp;
152
153 return temp;
154}
155
156static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
157{
158 u32 reg;
159 void __iomem *pllbase;
160
161 long mfi, pdf, mfn, mfd = 999999;
162 s64 temp64;
163 unsigned long quad_parent_rate;
164 unsigned long pll_hfsm, dp_ctl;
165 unsigned long parent_rate;
166
167 parent_rate = clk_get_rate(clk->parent);
168
169 pllbase = _get_pll_base(clk);
170
171 quad_parent_rate = 4 * parent_rate;
172 pdf = mfi = -1;
173 while (++pdf < 16 && mfi < 5)
174 mfi = rate * (pdf+1) / quad_parent_rate;
175 if (mfi > 15)
176 return -EINVAL;
177 pdf--;
178
179 temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
180 do_div(temp64, quad_parent_rate/1000000);
181 mfn = (long)temp64;
182
183 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
184 /* use dpdck0_2 */
185 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
186 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
187 if (pll_hfsm == 0) {
188 reg = mfi << 4 | pdf;
189 __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
190 __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
191 __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
192 } else {
193 reg = mfi << 4 | pdf;
194 __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
195 __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
196 __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
197 }
198
199 return 0;
200}
201
202static int _clk_pll_enable(struct clk *clk)
203{
204 u32 reg;
205 void __iomem *pllbase;
206 int i = 0;
207
208 pllbase = _get_pll_base(clk);
209 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
210 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
211
212 /* Wait for lock */
213 do {
214 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
215 if (reg & MXC_PLL_DP_CTL_LRF)
216 break;
217
218 udelay(1);
219 } while (++i < MAX_DPLL_WAIT_TRIES);
220
221 if (i == MAX_DPLL_WAIT_TRIES) {
222 pr_err("MX5: pll locking failed\n");
223 return -EINVAL;
224 }
225
226 return 0;
227}
228
229static void _clk_pll_disable(struct clk *clk)
230{
231 u32 reg;
232 void __iomem *pllbase;
233
234 pllbase = _get_pll_base(clk);
235 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
236 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
237}
238
239static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
240{
241 u32 reg, step;
242
243 reg = __raw_readl(MXC_CCM_CCSR);
244
245 /* When switching from pll_main_clk to a bypass clock, first select a
246 * multiplexed clock in 'step_sel', then shift the glitchless mux
247 * 'pll1_sw_clk_sel'.
248 *
249 * When switching back, do it in reverse order
250 */
251 if (parent == &pll1_main_clk) {
252 /* Switch to pll1_main_clk */
253 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
254 __raw_writel(reg, MXC_CCM_CCSR);
255 /* step_clk mux switched to lp_apm, to save power. */
256 reg = __raw_readl(MXC_CCM_CCSR);
257 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
258 reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
259 MXC_CCM_CCSR_STEP_SEL_OFFSET);
260 } else {
261 if (parent == &lp_apm_clk) {
262 step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
263 } else if (parent == &pll2_sw_clk) {
264 step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
265 } else if (parent == &pll3_sw_clk) {
266 step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
267 } else
268 return -EINVAL;
269
270 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
271 reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
272
273 __raw_writel(reg, MXC_CCM_CCSR);
274 /* Switch to step_clk */
275 reg = __raw_readl(MXC_CCM_CCSR);
276 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
277 }
278 __raw_writel(reg, MXC_CCM_CCSR);
279 return 0;
280}
281
282static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
283{
284 u32 reg, div;
285 unsigned long parent_rate;
286
287 parent_rate = clk_get_rate(clk->parent);
288
289 reg = __raw_readl(MXC_CCM_CCSR);
290
291 if (clk->parent == &pll2_sw_clk) {
292 div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
293 MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
294 } else if (clk->parent == &pll3_sw_clk) {
295 div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
296 MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
297 } else
298 div = 1;
299 return parent_rate / div;
300}
301
302static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
303{
304 u32 reg;
305
306 reg = __raw_readl(MXC_CCM_CCSR);
307
308 if (parent == &pll2_sw_clk)
309 reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
310 else
311 reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
312
313 __raw_writel(reg, MXC_CCM_CCSR);
314 return 0;
315}
316
317static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
318{
319 u32 reg;
320
321 if (parent == &osc_clk)
322 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
323 else
324 return -EINVAL;
325
326 __raw_writel(reg, MXC_CCM_CCSR);
327
328 return 0;
329}
330
331static unsigned long clk_arm_get_rate(struct clk *clk)
332{
333 u32 cacrr, div;
334 unsigned long parent_rate;
335
336 parent_rate = clk_get_rate(clk->parent);
337 cacrr = __raw_readl(MXC_CCM_CACRR);
338 div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
339
340 return parent_rate / div;
341}
342
343static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
344{
345 u32 reg, mux;
346 int i = 0;
347
348 mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
349
350 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
351 reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
352 __raw_writel(reg, MXC_CCM_CBCMR);
353
354 /* Wait for lock */
355 do {
356 reg = __raw_readl(MXC_CCM_CDHIPR);
357 if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
358 break;
359
360 udelay(1);
361 } while (++i < MAX_DPLL_WAIT_TRIES);
362
363 if (i == MAX_DPLL_WAIT_TRIES) {
364 pr_err("MX5: Set parent for periph_apm clock failed\n");
365 return -EINVAL;
366 }
367
368 return 0;
369}
370
371static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
372{
373 u32 reg;
374
375 reg = __raw_readl(MXC_CCM_CBCDR);
376
377 if (parent == &pll2_sw_clk)
378 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
379 else if (parent == &periph_apm_clk)
380 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
381 else
382 return -EINVAL;
383
384 __raw_writel(reg, MXC_CCM_CBCDR);
385
386 return 0;
387}
388
389static struct clk main_bus_clk = {
390 .parent = &pll2_sw_clk,
391 .set_parent = _clk_main_bus_set_parent,
392};
393
394static unsigned long clk_ahb_get_rate(struct clk *clk)
395{
396 u32 reg, div;
397 unsigned long parent_rate;
398
399 parent_rate = clk_get_rate(clk->parent);
400
401 reg = __raw_readl(MXC_CCM_CBCDR);
402 div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
403 MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
404 return parent_rate / div;
405}
406
407
408static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
409{
410 u32 reg, div;
411 unsigned long parent_rate;
412 int i = 0;
413
414 parent_rate = clk_get_rate(clk->parent);
415
416 div = parent_rate / rate;
417 if (div > 8 || div < 1 || ((parent_rate / div) != rate))
418 return -EINVAL;
419
420 reg = __raw_readl(MXC_CCM_CBCDR);
421 reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
422 reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
423 __raw_writel(reg, MXC_CCM_CBCDR);
424
425 /* Wait for lock */
426 do {
427 reg = __raw_readl(MXC_CCM_CDHIPR);
428 if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
429 break;
430
431 udelay(1);
432 } while (++i < MAX_DPLL_WAIT_TRIES);
433
434 if (i == MAX_DPLL_WAIT_TRIES) {
435 pr_err("MX5: clk_ahb_set_rate failed\n");
436 return -EINVAL;
437 }
438
439 return 0;
440}
441
442static unsigned long _clk_ahb_round_rate(struct clk *clk,
443 unsigned long rate)
444{
445 u32 div;
446 unsigned long parent_rate;
447
448 parent_rate = clk_get_rate(clk->parent);
449
450 div = parent_rate / rate;
451 if (div > 8)
452 div = 8;
453 else if (div == 0)
454 div++;
455 return parent_rate / div;
456}
457
458
459static int _clk_max_enable(struct clk *clk)
460{
461 u32 reg;
462
463 _clk_ccgr_enable(clk);
464
465 /* Handshake with MAX when LPM is entered. */
466 reg = __raw_readl(MXC_CCM_CLPCR);
467 reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
468 __raw_writel(reg, MXC_CCM_CLPCR);
469
470 return 0;
471}
472
473static void _clk_max_disable(struct clk *clk)
474{
475 u32 reg;
476
477 _clk_ccgr_disable_inwait(clk);
478
479 /* No Handshake with MAX when LPM is entered as its disabled. */
480 reg = __raw_readl(MXC_CCM_CLPCR);
481 reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
482 __raw_writel(reg, MXC_CCM_CLPCR);
483}
484
485static unsigned long clk_ipg_get_rate(struct clk *clk)
486{
487 u32 reg, div;
488 unsigned long parent_rate;
489
490 parent_rate = clk_get_rate(clk->parent);
491
492 reg = __raw_readl(MXC_CCM_CBCDR);
493 div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
494 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
495
496 return parent_rate / div;
497}
498
499static unsigned long clk_ipg_per_get_rate(struct clk *clk)
500{
501 u32 reg, prediv1, prediv2, podf;
502 unsigned long parent_rate;
503
504 parent_rate = clk_get_rate(clk->parent);
505
506 if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
507 /* the main_bus_clk is the one before the DVFS engine */
508 reg = __raw_readl(MXC_CCM_CBCDR);
509 prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
510 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
511 prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
512 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
513 podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
514 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
515 return parent_rate / (prediv1 * prediv2 * podf);
516 } else if (clk->parent == &ipg_clk)
517 return parent_rate;
518 else
519 BUG();
520}
521
522static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
523{
524 u32 reg;
525
526 reg = __raw_readl(MXC_CCM_CBCMR);
527
528 reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
529 reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
530
531 if (parent == &ipg_clk)
532 reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
533 else if (parent == &lp_apm_clk)
534 reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
535 else if (parent != &main_bus_clk)
536 return -EINVAL;
537
538 __raw_writel(reg, MXC_CCM_CBCMR);
539
540 return 0;
541}
542
543static unsigned long clk_uart_get_rate(struct clk *clk)
544{
545 u32 reg, prediv, podf;
546 unsigned long parent_rate;
547
548 parent_rate = clk_get_rate(clk->parent);
549
550 reg = __raw_readl(MXC_CCM_CSCDR1);
551 prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
552 MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
553 podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
554 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
555
556 return parent_rate / (prediv * podf);
557}
558
559static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
560{
561 u32 reg, mux;
562
563 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
564 &lp_apm_clk);
565 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;
566 reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
567 __raw_writel(reg, MXC_CCM_CSCMR1);
568
569 return 0;
570}
571
572static unsigned long get_high_reference_clock_rate(struct clk *clk)
573{
574 return external_high_reference;
575}
576
577static unsigned long get_low_reference_clock_rate(struct clk *clk)
578{
579 return external_low_reference;
580}
581
582static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
583{
584 return oscillator_reference;
585}
586
587static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
588{
589 return ckih2_reference;
590}
591
592/* External high frequency clock */
593static struct clk ckih_clk = {
594 .get_rate = get_high_reference_clock_rate,
595};
596
597static struct clk ckih2_clk = {
598 .get_rate = get_ckih2_reference_clock_rate,
599};
600
601static struct clk osc_clk = {
602 .get_rate = get_oscillator_reference_clock_rate,
603};
604
605/* External low frequency (32kHz) clock */
606static struct clk ckil_clk = {
607 .get_rate = get_low_reference_clock_rate,
608};
609
610static struct clk pll1_main_clk = {
611 .parent = &osc_clk,
612 .get_rate = clk_pll_get_rate,
613 .enable = _clk_pll_enable,
614 .disable = _clk_pll_disable,
615};
616
617/* Clock tree block diagram (WIP):
618 * CCM: Clock Controller Module
619 *
620 * PLL output -> |
621 * | CCM Switcher -> CCM_CLK_ROOT_GEN ->
622 * PLL bypass -> |
623 *
624 */
625
626/* PLL1 SW supplies to ARM core */
627static struct clk pll1_sw_clk = {
628 .parent = &pll1_main_clk,
629 .set_parent = _clk_pll1_sw_set_parent,
630 .get_rate = clk_pll1_sw_get_rate,
631};
632
633/* PLL2 SW supplies to AXI/AHB/IP buses */
634static struct clk pll2_sw_clk = {
635 .parent = &osc_clk,
636 .get_rate = clk_pll_get_rate,
637 .set_rate = _clk_pll_set_rate,
638 .set_parent = _clk_pll2_sw_set_parent,
639 .enable = _clk_pll_enable,
640 .disable = _clk_pll_disable,
641};
642
643/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
644static struct clk pll3_sw_clk = {
645 .parent = &osc_clk,
646 .set_rate = _clk_pll_set_rate,
647 .get_rate = clk_pll_get_rate,
648 .enable = _clk_pll_enable,
649 .disable = _clk_pll_disable,
650};
651
652/* Low-power Audio Playback Mode clock */
653static struct clk lp_apm_clk = {
654 .parent = &osc_clk,
655 .set_parent = _clk_lp_apm_set_parent,
656};
657
658static struct clk periph_apm_clk = {
659 .parent = &pll1_sw_clk,
660 .set_parent = _clk_periph_apm_set_parent,
661};
662
663static struct clk cpu_clk = {
664 .parent = &pll1_sw_clk,
665 .get_rate = clk_arm_get_rate,
666};
667
668static struct clk ahb_clk = {
669 .parent = &main_bus_clk,
670 .get_rate = clk_ahb_get_rate,
671 .set_rate = _clk_ahb_set_rate,
672 .round_rate = _clk_ahb_round_rate,
673};
674
675/* Main IP interface clock for access to registers */
676static struct clk ipg_clk = {
677 .parent = &ahb_clk,
678 .get_rate = clk_ipg_get_rate,
679};
680
681static struct clk ipg_perclk = {
682 .parent = &lp_apm_clk,
683 .get_rate = clk_ipg_per_get_rate,
684 .set_parent = _clk_ipg_per_set_parent,
685};
686
687static struct clk uart_root_clk = {
688 .parent = &pll2_sw_clk,
689 .get_rate = clk_uart_get_rate,
690 .set_parent = _clk_uart_set_parent,
691};
692
693static struct clk ahb_max_clk = {
694 .parent = &ahb_clk,
695 .enable_reg = MXC_CCM_CCGR0,
696 .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
697 .enable = _clk_max_enable,
698 .disable = _clk_max_disable,
699};
700
701static struct clk aips_tz1_clk = {
702 .parent = &ahb_clk,
703 .secondary = &ahb_max_clk,
704 .enable_reg = MXC_CCM_CCGR0,
705 .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
706 .enable = _clk_ccgr_enable,
707 .disable = _clk_ccgr_disable_inwait,
708};
709
710static struct clk aips_tz2_clk = {
711 .parent = &ahb_clk,
712 .secondary = &ahb_max_clk,
713 .enable_reg = MXC_CCM_CCGR0,
714 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
715 .enable = _clk_ccgr_enable,
716 .disable = _clk_ccgr_disable_inwait,
717};
718
719static struct clk gpt_32k_clk = {
720 .id = 0,
721 .parent = &ckil_clk,
722};
723
724#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
725 static struct clk name = { \
726 .id = i, \
727 .enable_reg = er, \
728 .enable_shift = es, \
729 .get_rate = gr, \
730 .set_rate = sr, \
731 .enable = _clk_ccgr_enable, \
732 .disable = _clk_ccgr_disable, \
733 .parent = p, \
734 .secondary = s, \
735 }
736
737/* DEFINE_CLOCK(name, id, enable_reg, enable_shift,
738 get_rate, set_rate, parent, secondary); */
739
740/* Shared peripheral bus arbiter */
741DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
742 NULL, NULL, &ipg_clk, NULL);
743
744/* UART */
745DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
746 NULL, NULL, &uart_root_clk, NULL);
747DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
748 NULL, NULL, &uart_root_clk, NULL);
749DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
750 NULL, NULL, &uart_root_clk, NULL);
751DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
752 NULL, NULL, &ipg_clk, &aips_tz1_clk);
753DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
754 NULL, NULL, &ipg_clk, &aips_tz1_clk);
755DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
756 NULL, NULL, &ipg_clk, &spba_clk);
757
758/* GPT */
759DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
760 NULL, NULL, &ipg_perclk, NULL);
761DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
762 NULL, NULL, &ipg_clk, NULL);
763
764/* FEC */
765DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
766 NULL, NULL, &ipg_clk, NULL);
767
768#define _REGISTER_CLOCK(d, n, c) \
769 { \
770 .dev_id = d, \
771 .con_id = n, \
772 .clk = &c, \
773 },
774
775static struct clk_lookup lookups[] = {
776 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
777 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
778 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
779 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
780 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
781};
782
783static void clk_tree_init(void)
784{
785 u32 reg;
786
787 ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
788
789 /*
790 * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
791 * 8MHz, its derived from lp_apm.
792 *
793 * FIXME: Verify if true for all boards
794 */
795 reg = __raw_readl(MXC_CCM_CBCDR);
796 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
797 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
798 reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
799 reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
800 __raw_writel(reg, MXC_CCM_CBCDR);
801}
802
803int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
804 unsigned long ckih1, unsigned long ckih2)
805{
806 int i;
807
808 external_low_reference = ckil;
809 external_high_reference = ckih1;
810 ckih2_reference = ckih2;
811 oscillator_reference = osc;
812
813 for (i = 0; i < ARRAY_SIZE(lookups); i++)
814 clkdev_add(&lookups[i]);
815
816 clk_tree_init();
817
818 clk_enable(&cpu_clk);
819 clk_enable(&main_bus_clk);
820
821 /* System timer */
822 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
823 MX51_MXC_INT_GPT);
824 return 0;
825}
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
new file mode 100644
index 000000000000..41c769f08c4d
--- /dev/null
+++ b/arch/arm/mach-mx5/cpu.c
@@ -0,0 +1,47 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * This file contains the CPU initialization code.
12 */
13
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <mach/hardware.h>
18#include <asm/io.h>
19
20static int __init post_cpu_init(void)
21{
22 unsigned int reg;
23 void __iomem *base;
24
25 if (!cpu_is_mx51())
26 return 0;
27
28 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
29 __raw_writel(0x0, base + 0x40);
30 __raw_writel(0x0, base + 0x44);
31 __raw_writel(0x0, base + 0x48);
32 __raw_writel(0x0, base + 0x4C);
33 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
34 __raw_writel(reg, base + 0x50);
35
36 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
37 __raw_writel(0x0, base + 0x40);
38 __raw_writel(0x0, base + 0x44);
39 __raw_writel(0x0, base + 0x48);
40 __raw_writel(0x0, base + 0x4C);
41 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
42 __raw_writel(reg, base + 0x50);
43
44 return 0;
45}
46
47postcore_initcall(post_cpu_init);
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
new file mode 100644
index 000000000000..c776b9af0624
--- /dev/null
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -0,0 +1,583 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
12#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
13
14#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
15#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
16#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
17#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
18#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
19#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
20
21/* PLL Register Offsets */
22#define MXC_PLL_DP_CTL 0x00
23#define MXC_PLL_DP_CONFIG 0x04
24#define MXC_PLL_DP_OP 0x08
25#define MXC_PLL_DP_MFD 0x0C
26#define MXC_PLL_DP_MFN 0x10
27#define MXC_PLL_DP_MFNMINUS 0x14
28#define MXC_PLL_DP_MFNPLUS 0x18
29#define MXC_PLL_DP_HFS_OP 0x1C
30#define MXC_PLL_DP_HFS_MFD 0x20
31#define MXC_PLL_DP_HFS_MFN 0x24
32#define MXC_PLL_DP_MFN_TOGC 0x28
33#define MXC_PLL_DP_DESTAT 0x2c
34
35/* PLL Register Bit definitions */
36#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
37#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
38#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
39#define MXC_PLL_DP_CTL_ADE 0x800
40#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
41#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
42#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
43#define MXC_PLL_DP_CTL_HFSM 0x80
44#define MXC_PLL_DP_CTL_PRE 0x40
45#define MXC_PLL_DP_CTL_UPEN 0x20
46#define MXC_PLL_DP_CTL_RST 0x10
47#define MXC_PLL_DP_CTL_RCP 0x8
48#define MXC_PLL_DP_CTL_PLM 0x4
49#define MXC_PLL_DP_CTL_BRM0 0x2
50#define MXC_PLL_DP_CTL_LRF 0x1
51
52#define MXC_PLL_DP_CONFIG_BIST 0x8
53#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
54#define MXC_PLL_DP_CONFIG_AREN 0x2
55#define MXC_PLL_DP_CONFIG_LDREQ 0x1
56
57#define MXC_PLL_DP_OP_MFI_OFFSET 4
58#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
59#define MXC_PLL_DP_OP_PDF_OFFSET 0
60#define MXC_PLL_DP_OP_PDF_MASK 0xF
61
62#define MXC_PLL_DP_MFD_OFFSET 0
63#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
64
65#define MXC_PLL_DP_MFN_OFFSET 0x0
66#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
67
68#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
69#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
70#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
71#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
72
73#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
74#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
75
76/* Register addresses of CCM*/
77#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00)
78#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04)
79#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08)
80#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C)
81#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10)
82#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14)
83#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18)
84#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C)
85#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20)
86#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24)
87#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28)
88#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C)
89#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30)
90#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34)
91#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38)
92#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C)
93#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40)
94#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44)
95#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48)
96#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C)
97#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50)
98#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54)
99#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58)
100#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C)
101#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60)
102#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64)
103#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68)
104#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C)
105#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70)
106#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74)
107#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78)
108#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C)
109#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80)
110#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84)
111
112/* Define the bits in register CCR */
113#define MXC_CCM_CCR_COSC_EN (1 << 12)
114#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
115#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
116#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
117#define MXC_CCM_CCR_FPM_EN (1 << 8)
118#define MXC_CCM_CCR_OSCNT_OFFSET (0)
119#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
120
121/* Define the bits in register CCDR */
122#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
123#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
124#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
125
126/* Define the bits in register CSR */
127#define MXC_CCM_CSR_COSR_READY (1 << 5)
128#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
129#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
130#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
131#define MXC_CCM_CSR_FPM_READY (1 << 1)
132#define MXC_CCM_CSR_REF_EN_B (1 << 0)
133
134/* Define the bits in register CCSR */
135#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
136#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
137#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
138#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0
139#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */
140#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
141#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
142#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
143#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
144#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
145#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
146#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk,
147 1: step_clk */
148#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
149#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
150
151/* Define the bits in register CACRR */
152#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
153#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
154
155/* Define the bits in register CBCDR */
156#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
157#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
158#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
159#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
160#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
161#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
162#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
163#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
164#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
165#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
166#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
167#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
168#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
169#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
170#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
171#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
172#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
173#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
174#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
175#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
176#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
177#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
178#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
179#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
180
181/* Define the bits in register CBCMR */
182#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
183#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
184#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
185#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
186#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
187#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
188#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
189#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
190#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
191#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
192#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
193#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
194#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
195#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
196#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
197#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
198
199/* Define the bits in register CSCMR1 */
200#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
201#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
202#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
203#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
204#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
205#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
206#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
207#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
208#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
209#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
210#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
211#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
212#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
213#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
214#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
215#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
216#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
217#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
218#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
219#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
220#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
221#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
222#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
223#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
224#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
225#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
226#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
227#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
228#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
229#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
230#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
231#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
232
233/* Define the bits in register CSCMR2 */
234#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
235#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
236#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
237#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
238#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
239#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
240#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
241#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
242#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
243#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
244#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
245#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
246#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
247#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
248#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
249#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
250#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
251#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
252#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
253#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
254#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
255#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
256#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
257#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
258#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
259#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
260#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
261
262/* Define the bits in register CSCDR1 */
263#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
264#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
265#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
266#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
267#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
268#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
269#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
270#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
271#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
272#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
273#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
274#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
275#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
276#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
277#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
278#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
279#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
280#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
281
282/* Define the bits in register CS1CDR and CS2CDR */
283#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
284#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
285#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
286#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
287#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
288#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
289#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
290#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
291
292#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
293#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
294#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
295#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
296#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
297#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
298#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
299#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
300
301/* Define the bits in register CDCDR */
302#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
303#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
304#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
305#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
306#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
307#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
308#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
309#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
310#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
311#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
312#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
313#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
314#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
315#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
316#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
317#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
318
319/* Define the bits in register CHSCCDR */
320#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
321#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
322#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
323#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
324#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
325#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
326#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
327#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
328
329/* Define the bits in register CSCDR2 */
330#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
331#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
332#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
333#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
334#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
335#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
336#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
337#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
338#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
339#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
340#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
341#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
342
343/* Define the bits in register CSCDR3 */
344#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
345#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
346#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
347#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
348#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
349#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
350#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
351#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
352
353/* Define the bits in register CSCDR4 */
354#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
355#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
356#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
357#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
358#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
359#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
360#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
361#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
362
363/* Define the bits in register CDHIPR */
364#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
365#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
366#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
367#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
368#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
369#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
370#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
371#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
372#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
373#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
374
375/* Define the bits in register CDCR */
376#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
377#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
378#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
379
380/* Define the bits in register CLPCR */
381#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
382#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
383#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
384#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
385#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
386#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
387#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
388#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
389#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
390#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
391#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
392#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
393#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
394#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
395#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
396#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
397#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
398#define MXC_CCM_CLPCR_LPM_OFFSET (0)
399#define MXC_CCM_CLPCR_LPM_MASK (0x3)
400
401/* Define the bits in register CISR */
402#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
403#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
404#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
405#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
406#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
407#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
408#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
409#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
410#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
411#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
412#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
413#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
414#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
415#define MXC_CCM_CISR_LRF_PLL1 (0x1)
416
417/* Define the bits in register CIMR */
418#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
419#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
420#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
421#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
422#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
423#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
424#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
425#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
426#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
427#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
428#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
429#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
430#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
431
432/* Define the bits in register CCOSR */
433#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
434#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
435#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
436#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
437#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
438#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
439#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
440#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
441#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
442#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
443
444/* Define the bits in registers CGPR */
445#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
446#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
447#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
448#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
449
450/* Define the bits in registers CCGRx */
451#define MXC_CCM_CCGRx_CG_MASK 0x3
452#define MXC_CCM_CCGRx_MOD_OFF 0x0
453#define MXC_CCM_CCGRx_MOD_ON 0x3
454#define MXC_CCM_CCGRx_MOD_IDLE 0x1
455
456#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30)
457#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28)
458#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26)
459#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24)
460#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22)
461#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20)
462#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18)
463#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16)
464#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10)
465#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8)
466#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6)
467#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4)
468#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2)
469#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0)
470
471#define MXC_CCM_CCGRx_CG15_OFFSET 30
472#define MXC_CCM_CCGRx_CG14_OFFSET 28
473#define MXC_CCM_CCGRx_CG13_OFFSET 26
474#define MXC_CCM_CCGRx_CG12_OFFSET 24
475#define MXC_CCM_CCGRx_CG11_OFFSET 22
476#define MXC_CCM_CCGRx_CG10_OFFSET 20
477#define MXC_CCM_CCGRx_CG9_OFFSET 18
478#define MXC_CCM_CCGRx_CG8_OFFSET 16
479#define MXC_CCM_CCGRx_CG7_OFFSET 14
480#define MXC_CCM_CCGRx_CG6_OFFSET 12
481#define MXC_CCM_CCGRx_CG5_OFFSET 10
482#define MXC_CCM_CCGRx_CG4_OFFSET 8
483#define MXC_CCM_CCGRx_CG3_OFFSET 6
484#define MXC_CCM_CCGRx_CG2_OFFSET 4
485#define MXC_CCM_CCGRx_CG1_OFFSET 2
486#define MXC_CCM_CCGRx_CG0_OFFSET 0
487
488#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
489#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
490#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
491#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
492#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
493#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
494#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
495#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
496#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
497#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
498#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
499#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
500#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
501
502/* CORTEXA8 platform */
503#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
504#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
505#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
506#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
507#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
508#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
509#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
510#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
511#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
512
513/* DVFS CORE */
514#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
515#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
516#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
517#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
518#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
519#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
520#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
521#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
522#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
523#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
524#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
525#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
526#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
527#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
528#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
529#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
530#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
531
532/* GPC */
533#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
534#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
535#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
536#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
537#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)
538#define MXC_GPC_PGR_ARMPG_OFFSET 8
539#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
540
541/* PGC */
542#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
543#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
544#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
545#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
546#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
547#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
548
549#define MXC_PGCR_PCR 1
550#define MXC_SRPGCR_PCR 1
551#define MXC_EMPGCR_PCR 1
552#define MXC_PGSR_PSR 1
553
554
555#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
556#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
557
558/* SRPG */
559#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
560#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
561#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
562
563#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
564#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
565#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
566
567#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
568#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
569#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
570
571#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
572#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
573#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
574
575#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
576#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
577#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
578
579#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
580#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
581#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
582
583#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
new file mode 100644
index 000000000000..d6fd3961ade9
--- /dev/null
+++ b/arch/arm/mach-mx5/devices.c
@@ -0,0 +1,96 @@
1/*
2 * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/platform_device.h>
13#include <mach/hardware.h>
14#include <mach/imx-uart.h>
15
16static struct resource uart0[] = {
17 {
18 .start = MX51_UART1_BASE_ADDR,
19 .end = MX51_UART1_BASE_ADDR + 0xfff,
20 .flags = IORESOURCE_MEM,
21 }, {
22 .start = MX51_MXC_INT_UART1,
23 .end = MX51_MXC_INT_UART1,
24 .flags = IORESOURCE_IRQ,
25 },
26};
27
28struct platform_device mxc_uart_device0 = {
29 .name = "imx-uart",
30 .id = 0,
31 .resource = uart0,
32 .num_resources = ARRAY_SIZE(uart0),
33};
34
35static struct resource uart1[] = {
36 {
37 .start = MX51_UART2_BASE_ADDR,
38 .end = MX51_UART2_BASE_ADDR + 0xfff,
39 .flags = IORESOURCE_MEM,
40 }, {
41 .start = MX51_MXC_INT_UART2,
42 .end = MX51_MXC_INT_UART2,
43 .flags = IORESOURCE_IRQ,
44 },
45};
46
47struct platform_device mxc_uart_device1 = {
48 .name = "imx-uart",
49 .id = 1,
50 .resource = uart1,
51 .num_resources = ARRAY_SIZE(uart1),
52};
53
54static struct resource uart2[] = {
55 {
56 .start = MX51_UART3_BASE_ADDR,
57 .end = MX51_UART3_BASE_ADDR + 0xfff,
58 .flags = IORESOURCE_MEM,
59 }, {
60 .start = MX51_MXC_INT_UART3,
61 .end = MX51_MXC_INT_UART3,
62 .flags = IORESOURCE_IRQ,
63 },
64};
65
66struct platform_device mxc_uart_device2 = {
67 .name = "imx-uart",
68 .id = 2,
69 .resource = uart2,
70 .num_resources = ARRAY_SIZE(uart2),
71};
72
73static struct resource mxc_fec_resources[] = {
74 {
75 .start = MX51_MXC_FEC_BASE_ADDR,
76 .end = MX51_MXC_FEC_BASE_ADDR + 0xfff,
77 .flags = IORESOURCE_MEM,
78 }, {
79 .start = MX51_MXC_INT_FEC,
80 .end = MX51_MXC_INT_FEC,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85struct platform_device mxc_fec_device = {
86 .name = "fec",
87 .id = 0,
88 .num_resources = ARRAY_SIZE(mxc_fec_resources),
89 .resource = mxc_fec_resources,
90};
91
92/* Dummy definition to allow compiling in AVIC and TZIC simultaneously */
93int __init mxc_register_gpios(void)
94{
95 return 0;
96}
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
new file mode 100644
index 000000000000..f339ab8c19be
--- /dev/null
+++ b/arch/arm/mach-mx5/devices.h
@@ -0,0 +1,4 @@
1extern struct platform_device mxc_uart_device0;
2extern struct platform_device mxc_uart_device1;
3extern struct platform_device mxc_uart_device2;
4extern struct platform_device mxc_fec_device;
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
new file mode 100644
index 000000000000..c21e18be7af8
--- /dev/null
+++ b/arch/arm/mach-mx5/mm.c
@@ -0,0 +1,89 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Create static mapping between physical to virtual memory.
12 */
13
14#include <linux/mm.h>
15#include <linux/init.h>
16
17#include <asm/mach/map.h>
18
19#include <mach/hardware.h>
20#include <mach/common.h>
21#include <mach/iomux-v3.h>
22
23/*
24 * Define the MX51 memory map.
25 */
26static struct map_desc mxc_io_desc[] __initdata = {
27 {
28 .virtual = MX51_IRAM_BASE_ADDR_VIRT,
29 .pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR),
30 .length = MX51_IRAM_SIZE,
31 .type = MT_DEVICE
32 }, {
33 .virtual = MX51_DEBUG_BASE_ADDR_VIRT,
34 .pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR),
35 .length = MX51_DEBUG_SIZE,
36 .type = MT_DEVICE
37 }, {
38 .virtual = MX51_TZIC_BASE_ADDR_VIRT,
39 .pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR),
40 .length = MX51_TZIC_SIZE,
41 .type = MT_DEVICE
42 }, {
43 .virtual = MX51_AIPS1_BASE_ADDR_VIRT,
44 .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),
45 .length = MX51_AIPS1_SIZE,
46 .type = MT_DEVICE
47 }, {
48 .virtual = MX51_SPBA0_BASE_ADDR_VIRT,
49 .pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR),
50 .length = MX51_SPBA0_SIZE,
51 .type = MT_DEVICE
52 }, {
53 .virtual = MX51_AIPS2_BASE_ADDR_VIRT,
54 .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),
55 .length = MX51_AIPS2_SIZE,
56 .type = MT_DEVICE
57 }, {
58 .virtual = MX51_NFC_AXI_BASE_ADDR_VIRT,
59 .pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR),
60 .length = MX51_NFC_AXI_SIZE,
61 .type = MT_DEVICE
62 },
63};
64
65/*
66 * This function initializes the memory map. It is called during the
67 * system startup to create static physical to virtual memory mappings
68 * for the IO modules.
69 */
70void __init mx51_map_io(void)
71{
72 u32 tzic_addr;
73
74 if (mx51_revision() < MX51_CHIP_REV_2_0)
75 tzic_addr = 0x8FFFC000;
76 else
77 tzic_addr = 0xE0003000;
78 mxc_io_desc[2].pfn = __phys_to_pfn(tzic_addr);
79
80 mxc_set_cpu_type(MXC_CPU_MX51);
81 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
82 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR));
83 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
84}
85
86void __init mx51_init_irq(void)
87{
88 tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
89}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 16:50:40 -0500