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-rw-r--r--arch/arm/mach-mx5/Kconfig42
-rw-r--r--arch/arm/mach-mx5/Makefile3
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51.c25
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51sd.c331
-rw-r--r--arch/arm/mach-mx5/board-mx51_3ds.c44
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c74
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikamx.c119
-rw-r--r--arch/arm/mach-mx5/clock-mx51.c391
-rw-r--r--arch/arm/mach-mx5/cpu.c19
-rw-r--r--arch/arm/mach-mx5/devices-imx51.h42
-rw-r--r--arch/arm/mach-mx5/devices.c114
-rw-r--r--arch/arm/mach-mx5/devices.h6
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c30
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c166
14 files changed, 1168 insertions, 238 deletions
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 0848db5dd364..a2df9ac37996 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -5,11 +5,14 @@ config ARCH_MX51
5 default y 5 default y
6 select MXC_TZIC 6 select MXC_TZIC
7 select ARCH_MXC_IOMUX_V3 7 select ARCH_MXC_IOMUX_V3
8 select ARCH_MXC_AUDMUX_V2
8 9
9comment "MX5 platforms:" 10comment "MX5 platforms:"
10 11
11config MACH_MX51_BABBAGE 12config MACH_MX51_BABBAGE
12 bool "Support MX51 BABBAGE platforms" 13 bool "Support MX51 BABBAGE platforms"
14 select IMX_HAVE_PLATFORM_IMX_I2C
15 select IMX_HAVE_PLATFORM_IMX_UART
13 help 16 help
14 Include support for MX51 Babbage platform, also known as MX51EVK in 17 Include support for MX51 Babbage platform, also known as MX51EVK in
15 u-boot. This includes specific configurations for the board and its 18 u-boot. This includes specific configurations for the board and its
@@ -17,6 +20,8 @@ config MACH_MX51_BABBAGE
17 20
18config MACH_MX51_3DS 21config MACH_MX51_3DS
19 bool "Support MX51PDK (3DS)" 22 bool "Support MX51PDK (3DS)"
23 select IMX_HAVE_PLATFORM_IMX_UART
24 select IMX_HAVE_PLATFORM_SPI_IMX
20 select MXC_DEBUG_BOARD 25 select MXC_DEBUG_BOARD
21 help 26 help
22 Include support for MX51PDK (3DS) platform. This includes specific 27 Include support for MX51PDK (3DS) platform. This includes specific
@@ -24,6 +29,10 @@ config MACH_MX51_3DS
24 29
25config MACH_EUKREA_CPUIMX51 30config MACH_EUKREA_CPUIMX51
26 bool "Support Eukrea CPUIMX51 module" 31 bool "Support Eukrea CPUIMX51 module"
32 select IMX_HAVE_PLATFORM_IMX_I2C
33 select IMX_HAVE_PLATFORM_IMX_UART
34 select IMX_HAVE_PLATFORM_MXC_NAND
35 select IMX_HAVE_PLATFORM_SPI_IMX
27 help 36 help
28 Include support for Eukrea CPUIMX51 platform. This includes 37 Include support for Eukrea CPUIMX51 platform. This includes
29 specific configurations for the module and its peripherals. 38 specific configurations for the module and its peripherals.
@@ -36,10 +45,43 @@ choice
36config MACH_EUKREA_MBIMX51_BASEBOARD 45config MACH_EUKREA_MBIMX51_BASEBOARD
37 prompt "Eukrea MBIMX51 development board" 46 prompt "Eukrea MBIMX51 development board"
38 bool 47 bool
48 select IMX_HAVE_PLATFORM_ESDHC
39 help 49 help
40 This adds board specific devices that can be found on Eukrea's 50 This adds board specific devices that can be found on Eukrea's
41 MBIMX51 evaluation board. 51 MBIMX51 evaluation board.
42 52
43endchoice 53endchoice
44 54
55config MACH_EUKREA_CPUIMX51SD
56 bool "Support Eukrea CPUIMX51SD module"
57 select IMX_HAVE_PLATFORM_IMX_I2C
58 select IMX_HAVE_PLATFORM_SPI_IMX
59 select IMX_HAVE_PLATFORM_IMX_UART
60 select IMX_HAVE_PLATFORM_MXC_NAND
61 help
62 Include support for Eukrea CPUIMX51SD platform. This includes
63 specific configurations for the module and its peripherals.
64
65choice
66 prompt "Baseboard"
67 depends on MACH_EUKREA_CPUIMX51SD
68 default MACH_EUKREA_MBIMXSD51_BASEBOARD
69
70config MACH_EUKREA_MBIMXSD51_BASEBOARD
71 prompt "Eukrea MBIMXSD development board"
72 bool
73 select IMX_HAVE_PLATFORM_ESDHC
74 help
75 This adds board specific devices that can be found on Eukrea's
76 MBIMXSD evaluation board.
77
78endchoice
79
80config MACH_MX51_EFIKAMX
81 bool "Support MX51 Genesi Efika MX nettop"
82 select IMX_HAVE_PLATFORM_IMX_UART
83 help
84 Include support for Genesi Efika MX nettop. This includes specific
85 configurations for the board and its peripherals.
86
45endif 87endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 86c66e7f52f3..1769c161a60d 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -9,3 +9,6 @@ obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
9obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o 9obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
10obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o 10obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
11obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o 11obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
12obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
13obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
14obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 623607a20f57..6a9792fd0a76 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -28,9 +28,7 @@
28#include <mach/eukrea-baseboards.h> 28#include <mach/eukrea-baseboards.h>
29#include <mach/common.h> 29#include <mach/common.h>
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31#include <mach/imx-uart.h>
32#include <mach/iomux-mx51.h> 31#include <mach/iomux-mx51.h>
33#include <mach/i2c.h>
34#include <mach/mxc_ehci.h> 32#include <mach/mxc_ehci.h>
35 33
36#include <asm/irq.h> 34#include <asm/irq.h>
@@ -39,6 +37,7 @@
39#include <asm/mach/arch.h> 37#include <asm/mach/arch.h>
40#include <asm/mach/time.h> 38#include <asm/mach/time.h>
41 39
40#include "devices-imx51.h"
42#include "devices.h" 41#include "devices.h"
43 42
44#define CPUIMX51_USBH1_STP (0*32 + 27) 43#define CPUIMX51_USBH1_STP (0*32 + 27)
@@ -109,7 +108,6 @@ static struct platform_device serial_device = {
109#endif 108#endif
110 109
111static struct platform_device *devices[] __initdata = { 110static struct platform_device *devices[] __initdata = {
112 &mxc_fec_device,
113#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 111#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
114 &serial_device, 112 &serial_device,
115#endif 113#endif
@@ -148,11 +146,19 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
148 MX51_PAD_USBH1_STP__USBH1_STP, 146 MX51_PAD_USBH1_STP__USBH1_STP,
149}; 147};
150 148
151static struct imxuart_platform_data uart_pdata = { 149static const struct mxc_nand_platform_data
150 eukrea_cpuimx51_nand_board_info __initconst = {
151 .width = 1,
152 .hw_ecc = 1,
153 .flash_bbt = 1,
154};
155
156static const struct imxuart_platform_data uart_pdata __initconst = {
152 .flags = IMXUART_HAVE_RTSCTS, 157 .flags = IMXUART_HAVE_RTSCTS,
153}; 158};
154 159
155static struct imxi2c_platform_data eukrea_cpuimx51_i2c_data = { 160static const
161struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
156 .bitrate = 100000, 162 .bitrate = 100000,
157}; 163};
158 164
@@ -239,7 +245,9 @@ static void __init eukrea_cpuimx51_init(void)
239 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, 245 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
240 ARRAY_SIZE(eukrea_cpuimx51_pads)); 246 ARRAY_SIZE(eukrea_cpuimx51_pads));
241 247
242 mxc_register_device(&mxc_uart_device0, &uart_pdata); 248 imx51_add_imx_uart(0, &uart_pdata);
249 imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
250
243 gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq"); 251 gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
244 gpio_direction_input(CPUIMX51_QUARTA_GPIO); 252 gpio_direction_input(CPUIMX51_QUARTA_GPIO);
245 gpio_free(CPUIMX51_QUARTA_GPIO); 253 gpio_free(CPUIMX51_QUARTA_GPIO);
@@ -253,9 +261,10 @@ static void __init eukrea_cpuimx51_init(void)
253 gpio_direction_input(CPUIMX51_QUARTD_GPIO); 261 gpio_direction_input(CPUIMX51_QUARTD_GPIO);
254 gpio_free(CPUIMX51_QUARTD_GPIO); 262 gpio_free(CPUIMX51_QUARTD_GPIO);
255 263
264 imx51_add_fec(NULL);
256 platform_add_devices(devices, ARRAY_SIZE(devices)); 265 platform_add_devices(devices, ARRAY_SIZE(devices));
257 266
258 mxc_register_device(&mxc_i2c_device1, &eukrea_cpuimx51_i2c_data); 267 imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
259 i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices, 268 i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
260 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices)); 269 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
261 270
@@ -283,8 +292,6 @@ static struct sys_timer mxc_timer = {
283 292
284MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") 293MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
285 /* Maintainer: Eric Bénard <eric@eukrea.com> */ 294 /* Maintainer: Eric Bénard <eric@eukrea.com> */
286 .phys_io = MX51_AIPS1_BASE_ADDR,
287 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
288 .boot_params = PHYS_OFFSET + 0x100, 295 .boot_params = PHYS_OFFSET + 0x100,
289 .map_io = mx51_map_io, 296 .map_io = mx51_map_io,
290 .init_irq = mx51_init_irq, 297 .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
new file mode 100644
index 000000000000..4b3a6119c5fb
--- /dev/null
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -0,0 +1,331 @@
1/*
2 *
3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
4 *
5 * based on board-mx51_babbage.c which is
6 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/i2c/tsc2007.h>
21#include <linux/gpio.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/fsl_devices.h>
27#include <linux/i2c-gpio.h>
28#include <linux/spi/spi.h>
29#include <linux/can/platform/mcp251x.h>
30
31#include <mach/eukrea-baseboards.h>
32#include <mach/common.h>
33#include <mach/hardware.h>
34#include <mach/iomux-mx51.h>
35#include <mach/mxc_ehci.h>
36
37#include <asm/irq.h>
38#include <asm/setup.h>
39#include <asm/mach-types.h>
40#include <asm/mach/arch.h>
41#include <asm/mach/time.h>
42
43#include "devices-imx51.h"
44#include "devices.h"
45
46#define USBH1_RST (1*32 + 28)
47#define ETH_RST (1*32 + 31)
48#define TSC2007_IRQGPIO (2*32 + 12)
49#define CAN_IRQGPIO (0*32 + 1)
50#define CAN_RST (3*32 + 15)
51#define CAN_NCS (3*32 + 24)
52#define CAN_RXOBF (0*32 + 4)
53#define CAN_RX1BF (0*32 + 6)
54#define CAN_TXORTS (0*32 + 7)
55#define CAN_TX1RTS (0*32 + 8)
56#define CAN_TX2RTS (0*32 + 9)
57#define I2C_SCL (3*32 + 16)
58#define I2C_SDA (3*32 + 17)
59
60/* USB_CTRL_1 */
61#define MX51_USB_CTRL_1_OFFSET 0x10
62#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
63
64#define MX51_USB_PLLDIV_12_MHZ 0x00
65#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
66#define MX51_USB_PLL_DIV_24_MHZ 0x02
67
68#define CPUIMX51SD_GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, \
69 MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
70
71static struct pad_desc eukrea_cpuimx51sd_pads[] = {
72 /* UART1 */
73 MX51_PAD_UART1_RXD__UART1_RXD,
74 MX51_PAD_UART1_TXD__UART1_TXD,
75 MX51_PAD_UART1_RTS__UART1_RTS,
76 MX51_PAD_UART1_CTS__UART1_CTS,
77
78 /* USB HOST1 */
79 MX51_PAD_USBH1_CLK__USBH1_CLK,
80 MX51_PAD_USBH1_DIR__USBH1_DIR,
81 MX51_PAD_USBH1_NXT__USBH1_NXT,
82 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
83 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
84 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
85 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
86 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
87 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
88 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
89 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
90 MX51_PAD_USBH1_STP__USBH1_STP,
91 MX51_PAD_EIM_CS3__GPIO_2_28, /* PHY nRESET */
92
93 /* FEC */
94 MX51_PAD_EIM_DTACK__GPIO_2_31, /* PHY nRESET */
95
96 /* HSI2C */
97 MX51_PAD_I2C1_CLK__GPIO_4_16,
98 MX51_PAD_I2C1_DAT__GPIO_4_17,
99
100 /* CAN */
101 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
102 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
103 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
104 MX51_PAD_CSPI1_SS0__GPIO_4_24, /* nCS */
105 MX51_PAD_CSI2_PIXCLK__GPIO_4_15, /* nReset */
106 MX51_PAD_GPIO_1_1__GPIO_1_1, /* IRQ */
107 MX51_PAD_GPIO_1_4__GPIO_1_4, /* Control signals */
108 MX51_PAD_GPIO_1_6__GPIO_1_6,
109 MX51_PAD_GPIO_1_7__GPIO_1_7,
110 MX51_PAD_GPIO_1_8__GPIO_1_8,
111 MX51_PAD_GPIO_1_9__GPIO_1_9,
112
113 /* Touchscreen */
114 CPUIMX51SD_GPIO_3_12, /* IRQ */
115};
116
117static const struct imxuart_platform_data uart_pdata __initconst = {
118 .flags = IMXUART_HAVE_RTSCTS,
119};
120
121static int ts_get_pendown_state(void)
122{
123 return gpio_get_value(TSC2007_IRQGPIO) ? 0 : 1;
124}
125
126static struct tsc2007_platform_data tsc2007_info = {
127 .model = 2007,
128 .x_plate_ohms = 180,
129 .get_pendown_state = ts_get_pendown_state,
130};
131
132static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
133 {
134 I2C_BOARD_INFO("pcf8563", 0x51),
135 }, {
136 I2C_BOARD_INFO("tsc2007", 0x49),
137 .type = "tsc2007",
138 .platform_data = &tsc2007_info,
139 .irq = gpio_to_irq(TSC2007_IRQGPIO),
140 },
141};
142
143static const struct mxc_nand_platform_data
144 eukrea_cpuimx51sd_nand_board_info __initconst = {
145 .width = 1,
146 .hw_ecc = 1,
147 .flash_bbt = 1,
148};
149
150/* This function is board specific as the bit mask for the plldiv will also
151be different for other Freescale SoCs, thus a common bitmask is not
152possible and cannot get place in /plat-mxc/ehci.c.*/
153static int initialize_otg_port(struct platform_device *pdev)
154{
155 u32 v;
156 void __iomem *usb_base;
157 void __iomem *usbother_base;
158
159 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
160 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
161
162 /* Set the PHY clock to 19.2MHz */
163 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
164 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
165 v |= MX51_USB_PLL_DIV_19_2_MHZ;
166 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
167 iounmap(usb_base);
168 return 0;
169}
170
171static int initialize_usbh1_port(struct platform_device *pdev)
172{
173 u32 v;
174 void __iomem *usb_base;
175 void __iomem *usbother_base;
176
177 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
178 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
179
180 /* The clock for the USBH1 ULPI port will come from the PHY. */
181 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
182 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
183 usbother_base + MX51_USB_CTRL_1_OFFSET);
184 iounmap(usb_base);
185 return 0;
186}
187
188static struct mxc_usbh_platform_data dr_utmi_config = {
189 .init = initialize_otg_port,
190 .portsc = MXC_EHCI_UTMI_16BIT,
191 .flags = MXC_EHCI_INTERNAL_PHY,
192};
193
194static struct fsl_usb2_platform_data usb_pdata = {
195 .operating_mode = FSL_USB2_DR_DEVICE,
196 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
197};
198
199static struct mxc_usbh_platform_data usbh1_config = {
200 .init = initialize_usbh1_port,
201 .portsc = MXC_EHCI_MODE_ULPI,
202 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
203};
204
205static int otg_mode_host;
206
207static int __init eukrea_cpuimx51sd_otg_mode(char *options)
208{
209 if (!strcmp(options, "host"))
210 otg_mode_host = 1;
211 else if (!strcmp(options, "device"))
212 otg_mode_host = 0;
213 else
214 pr_info("otg_mode neither \"host\" nor \"device\". "
215 "Defaulting to device\n");
216 return 0;
217}
218__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
219
220static struct i2c_gpio_platform_data pdata = {
221 .sda_pin = I2C_SDA,
222 .sda_is_open_drain = 0,
223 .scl_pin = I2C_SCL,
224 .scl_is_open_drain = 0,
225 .udelay = 2,
226};
227
228static struct platform_device hsi2c_gpio_device = {
229 .name = "i2c-gpio",
230 .id = 0,
231 .dev.platform_data = &pdata,
232};
233
234static struct mcp251x_platform_data mcp251x_info = {
235 .oscillator_frequency = 24E6,
236};
237
238static struct spi_board_info cpuimx51sd_spi_device[] = {
239 {
240 .modalias = "mcp2515",
241 .max_speed_hz = 6500000,
242 .bus_num = 0,
243 .mode = SPI_MODE_0,
244 .chip_select = 0,
245 .platform_data = &mcp251x_info,
246 .irq = gpio_to_irq(0 * 32 + 1)
247 },
248};
249
250static int cpuimx51sd_spi1_cs[] = {
251 CAN_NCS,
252};
253
254static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
255 .chipselect = cpuimx51sd_spi1_cs,
256 .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
257};
258
259static struct platform_device *platform_devices[] __initdata = {
260 &hsi2c_gpio_device,
261};
262
263static void __init eukrea_cpuimx51sd_init(void)
264{
265 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
266 ARRAY_SIZE(eukrea_cpuimx51sd_pads));
267
268 imx51_add_imx_uart(0, &uart_pdata);
269 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
270
271 gpio_request(ETH_RST, "eth_rst");
272 gpio_set_value(ETH_RST, 1);
273 imx51_add_fec(NULL);
274
275 gpio_request(CAN_IRQGPIO, "can_irq");
276 gpio_direction_input(CAN_IRQGPIO);
277 gpio_free(CAN_IRQGPIO);
278 gpio_request(CAN_NCS, "can_ncs");
279 gpio_direction_output(CAN_NCS, 1);
280 gpio_free(CAN_NCS);
281 gpio_request(CAN_RST, "can_rst");
282 gpio_direction_output(CAN_RST, 0);
283 msleep(20);
284 gpio_set_value(CAN_RST, 1);
285 imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
286 spi_register_board_info(cpuimx51sd_spi_device,
287 ARRAY_SIZE(cpuimx51sd_spi_device));
288
289 gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
290 gpio_direction_input(TSC2007_IRQGPIO);
291 gpio_free(TSC2007_IRQGPIO);
292
293 i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
294 ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
295 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
296
297 if (otg_mode_host)
298 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
299 else {
300 initialize_otg_port(NULL);
301 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
302 }
303
304 gpio_request(USBH1_RST, "usb_rst");
305 gpio_direction_output(USBH1_RST, 0);
306 msleep(20);
307 gpio_set_value(USBH1_RST, 1);
308 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
309
310#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
311 eukrea_mbimxsd51_baseboard_init();
312#endif
313}
314
315static void __init eukrea_cpuimx51sd_timer_init(void)
316{
317 mx51_clocks_init(32768, 24000000, 22579200, 0);
318}
319
320static struct sys_timer mxc_timer = {
321 .init = eukrea_cpuimx51sd_timer_init,
322};
323
324MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
325 /* Maintainer: Eric Bénard <eric@eukrea.com> */
326 .boot_params = PHYS_OFFSET + 0x100,
327 .map_io = mx51_map_io,
328 .init_irq = mx51_init_irq,
329 .init_machine = eukrea_cpuimx51sd_init,
330 .timer = &mxc_timer,
331MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index f95c2fd94667..79ce8dcf3cda 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -13,6 +13,7 @@
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/input/matrix_keypad.h> 15#include <linux/input/matrix_keypad.h>
16#include <linux/spi/spi.h>
16 17
17#include <asm/mach-types.h> 18#include <asm/mach-types.h>
18#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
@@ -21,12 +22,13 @@
21#include <mach/hardware.h> 22#include <mach/hardware.h>
22#include <mach/common.h> 23#include <mach/common.h>
23#include <mach/iomux-mx51.h> 24#include <mach/iomux-mx51.h>
24#include <mach/imx-uart.h>
25#include <mach/3ds_debugboard.h> 25#include <mach/3ds_debugboard.h>
26 26
27#include "devices-imx51.h"
27#include "devices.h" 28#include "devices.h"
28 29
29#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6) 30#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
31#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)
30 32
31static struct pad_desc mx51_3ds_pads[] = { 33static struct pad_desc mx51_3ds_pads[] = {
32 /* UART1 */ 34 /* UART1 */
@@ -61,19 +63,25 @@ static struct pad_desc mx51_3ds_pads[] = {
61 MX51_PAD_KEY_COL3__KEY_COL3, 63 MX51_PAD_KEY_COL3__KEY_COL3,
62 MX51_PAD_KEY_COL4__KEY_COL4, 64 MX51_PAD_KEY_COL4__KEY_COL4,
63 MX51_PAD_KEY_COL5__KEY_COL5, 65 MX51_PAD_KEY_COL5__KEY_COL5,
66
67 /* eCSPI2 */
68 MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
69 MX51_PAD_NANDF_RB3__ECSPI2_MISO,
70 MX51_PAD_NANDF_D15__ECSPI2_MOSI,
71 MX51_PAD_NANDF_D12__GPIO_3_28,
64}; 72};
65 73
66/* Serial ports */ 74/* Serial ports */
67#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) 75#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
68static struct imxuart_platform_data uart_pdata = { 76static const struct imxuart_platform_data uart_pdata __initconst = {
69 .flags = IMXUART_HAVE_RTSCTS, 77 .flags = IMXUART_HAVE_RTSCTS,
70}; 78};
71 79
72static inline void mxc_init_imx_uart(void) 80static inline void mxc_init_imx_uart(void)
73{ 81{
74 mxc_register_device(&mxc_uart_device0, &uart_pdata); 82 imx51_add_imx_uart(0, &uart_pdata);
75 mxc_register_device(&mxc_uart_device1, &uart_pdata); 83 imx51_add_imx_uart(1, &uart_pdata);
76 mxc_register_device(&mxc_uart_device2, &uart_pdata); 84 imx51_add_imx_uart(2, &uart_pdata);
77} 85}
78#else /* !SERIAL_IMX */ 86#else /* !SERIAL_IMX */
79static inline void mxc_init_imx_uart(void) 87static inline void mxc_init_imx_uart(void)
@@ -127,6 +135,26 @@ static inline void mxc_init_keypad(void)
127} 135}
128#endif 136#endif
129 137
138static int mx51_3ds_spi2_cs[] = {
139 MXC_SPI_CS(0),
140 MX51_3DS_ECSPI2_CS,
141};
142
143static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
144 .chipselect = mx51_3ds_spi2_cs,
145 .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs),
146};
147
148static struct spi_board_info mx51_3ds_spi_nor_device[] = {
149 {
150 .modalias = "m25p80",
151 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
152 .bus_num = 1,
153 .chip_select = 1,
154 .mode = SPI_MODE_0,
155 .platform_data = NULL,},
156};
157
130/* 158/*
131 * Board specific initialization. 159 * Board specific initialization.
132 */ 160 */
@@ -136,6 +164,10 @@ static void __init mxc_board_init(void)
136 ARRAY_SIZE(mx51_3ds_pads)); 164 ARRAY_SIZE(mx51_3ds_pads));
137 mxc_init_imx_uart(); 165 mxc_init_imx_uart();
138 166
167 imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
168 spi_register_board_info(mx51_3ds_spi_nor_device,
169 ARRAY_SIZE(mx51_3ds_spi_nor_device));
170
139 if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT)) 171 if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
140 printk(KERN_WARNING "Init of the debugboard failed, all " 172 printk(KERN_WARNING "Init of the debugboard failed, all "
141 "devices on the board are unusable.\n"); 173 "devices on the board are unusable.\n");
@@ -154,8 +186,6 @@ static struct sys_timer mxc_timer = {
154 186
155MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") 187MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
156 /* Maintainer: Freescale Semiconductor, Inc. */ 188 /* Maintainer: Freescale Semiconductor, Inc. */
157 .phys_io = MX51_AIPS1_BASE_ADDR,
158 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
159 .boot_params = PHYS_OFFSET + 0x100, 189 .boot_params = PHYS_OFFSET + 0x100,
160 .map_io = mx51_map_io, 190 .map_io = mx51_map_io,
161 .init_irq = mx51_init_irq, 191 .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 6e384d92e625..0821fe9b3b27 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -17,12 +17,11 @@
17#include <linux/delay.h> 17#include <linux/delay.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/fsl_devices.h> 19#include <linux/fsl_devices.h>
20#include <linux/fec.h>
20 21
21#include <mach/common.h> 22#include <mach/common.h>
22#include <mach/hardware.h> 23#include <mach/hardware.h>
23#include <mach/imx-uart.h>
24#include <mach/iomux-mx51.h> 24#include <mach/iomux-mx51.h>
25#include <mach/i2c.h>
26#include <mach/mxc_ehci.h> 25#include <mach/mxc_ehci.h>
27 26
28#include <asm/irq.h> 27#include <asm/irq.h>
@@ -31,11 +30,13 @@
31#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
32#include <asm/mach/time.h> 31#include <asm/mach/time.h>
33 32
33#include "devices-imx51.h"
34#include "devices.h" 34#include "devices.h"
35 35
36#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ 36#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
37#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */ 37#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
38#define BABBAGE_PHY_RESET (1*32 +5) /* GPIO_2_5 */ 38#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */
39#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */
39 40
40/* USB_CTRL_1 */ 41/* USB_CTRL_1 */
41#define MX51_USB_CTRL_1_OFFSET 0x10 42#define MX51_USB_CTRL_1_OFFSET 0x10
@@ -45,10 +46,6 @@
45#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 46#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
46#define MX51_USB_PLL_DIV_24_MHZ 0x02 47#define MX51_USB_PLL_DIV_24_MHZ 0x02
47 48
48static struct platform_device *devices[] __initdata = {
49 &mxc_fec_device,
50};
51
52static struct pad_desc mx51babbage_pads[] = { 49static struct pad_desc mx51babbage_pads[] = {
53 /* UART1 */ 50 /* UART1 */
54 MX51_PAD_UART1_RXD__UART1_RXD, 51 MX51_PAD_UART1_RXD__UART1_RXD,
@@ -93,19 +90,41 @@ static struct pad_desc mx51babbage_pads[] = {
93 90
94 /* USB HUB reset line*/ 91 /* USB HUB reset line*/
95 MX51_PAD_GPIO_1_7__GPIO_1_7, 92 MX51_PAD_GPIO_1_7__GPIO_1_7,
93
94 /* FEC */
95 MX51_PAD_EIM_EB2__FEC_MDIO,
96 MX51_PAD_EIM_EB3__FEC_RDAT1,
97 MX51_PAD_EIM_CS2__FEC_RDAT2,
98 MX51_PAD_EIM_CS3__FEC_RDAT3,
99 MX51_PAD_EIM_CS4__FEC_RX_ER,
100 MX51_PAD_EIM_CS5__FEC_CRS,
101 MX51_PAD_NANDF_RB2__FEC_COL,
102 MX51_PAD_NANDF_RB3__FEC_RXCLK,
103 MX51_PAD_NANDF_RB6__FEC_RDAT0,
104 MX51_PAD_NANDF_RB7__FEC_TDAT0,
105 MX51_PAD_NANDF_CS2__FEC_TX_ER,
106 MX51_PAD_NANDF_CS3__FEC_MDC,
107 MX51_PAD_NANDF_CS4__FEC_TDAT1,
108 MX51_PAD_NANDF_CS5__FEC_TDAT2,
109 MX51_PAD_NANDF_CS6__FEC_TDAT3,
110 MX51_PAD_NANDF_CS7__FEC_TX_EN,
111 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
112
113 /* FEC PHY reset line */
114 MX51_PAD_EIM_A20__GPIO_2_14,
96}; 115};
97 116
98/* Serial ports */ 117/* Serial ports */
99#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) 118#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
100static struct imxuart_platform_data uart_pdata = { 119static const struct imxuart_platform_data uart_pdata __initconst = {
101 .flags = IMXUART_HAVE_RTSCTS, 120 .flags = IMXUART_HAVE_RTSCTS,
102}; 121};
103 122
104static inline void mxc_init_imx_uart(void) 123static inline void mxc_init_imx_uart(void)
105{ 124{
106 mxc_register_device(&mxc_uart_device0, &uart_pdata); 125 imx51_add_imx_uart(0, &uart_pdata);
107 mxc_register_device(&mxc_uart_device1, &uart_pdata); 126 imx51_add_imx_uart(1, &uart_pdata);
108 mxc_register_device(&mxc_uart_device2, &uart_pdata); 127 imx51_add_imx_uart(2, &uart_pdata);
109} 128}
110#else /* !SERIAL_IMX */ 129#else /* !SERIAL_IMX */
111static inline void mxc_init_imx_uart(void) 130static inline void mxc_init_imx_uart(void)
@@ -113,7 +132,7 @@ static inline void mxc_init_imx_uart(void)
113} 132}
114#endif /* SERIAL_IMX */ 133#endif /* SERIAL_IMX */
115 134
116static struct imxi2c_platform_data babbage_i2c_data = { 135static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
117 .bitrate = 100000, 136 .bitrate = 100000,
118}; 137};
119 138
@@ -171,6 +190,22 @@ static inline void babbage_usbhub_reset(void)
171 gpio_set_value(BABBAGE_USB_HUB_RESET, 1); 190 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
172} 191}
173 192
193static inline void babbage_fec_reset(void)
194{
195 int ret;
196
197 /* reset FEC PHY */
198 ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset");
199 if (ret) {
200 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
201 return;
202 }
203 gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0);
204 gpio_set_value(BABBAGE_FEC_PHY_RESET, 0);
205 msleep(1);
206 gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
207}
208
174/* This function is board specific as the bit mask for the plldiv will also 209/* This function is board specific as the bit mask for the plldiv will also
175be different for other Freescale SoCs, thus a common bitmask is not 210be different for other Freescale SoCs, thus a common bitmask is not
176possible and cannot get place in /plat-mxc/ehci.c.*/ 211possible and cannot get place in /plat-mxc/ehci.c.*/
@@ -178,7 +213,7 @@ static int initialize_otg_port(struct platform_device *pdev)
178{ 213{
179 u32 v; 214 u32 v;
180 void __iomem *usb_base; 215 void __iomem *usb_base;
181 u32 usbother_base; 216 void __iomem *usbother_base;
182 217
183 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 218 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
184 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 219 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -196,7 +231,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
196{ 231{
197 u32 v; 232 u32 v;
198 void __iomem *usb_base; 233 void __iomem *usb_base;
199 u32 usbother_base; 234 void __iomem *usbother_base;
200 235
201 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 236 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
202 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 237 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -250,10 +285,11 @@ static void __init mxc_board_init(void)
250 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, 285 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
251 ARRAY_SIZE(mx51babbage_pads)); 286 ARRAY_SIZE(mx51babbage_pads));
252 mxc_init_imx_uart(); 287 mxc_init_imx_uart();
253 platform_add_devices(devices, ARRAY_SIZE(devices)); 288 babbage_fec_reset();
289 imx51_add_fec(NULL);
254 290
255 mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data); 291 imx51_add_imx_i2c(0, &babbage_i2c_data);
256 mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data); 292 imx51_add_imx_i2c(1, &babbage_i2c_data);
257 mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data); 293 mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
258 294
259 if (otg_mode_host) 295 if (otg_mode_host)
@@ -281,9 +317,7 @@ static struct sys_timer mxc_timer = {
281 317
282MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") 318MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
283 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */ 319 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
284 .phys_io = MX51_AIPS1_BASE_ADDR, 320 .boot_params = MX51_PHYS_OFFSET + 0x100,
285 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
286 .boot_params = PHYS_OFFSET + 0x100,
287 .map_io = mx51_map_io, 321 .map_io = mx51_map_io,
288 .init_irq = mx51_init_irq, 322 .init_irq = mx51_init_irq,
289 .init_machine = mxc_board_init, 323 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
new file mode 100644
index 000000000000..6e623bda3ee7
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -0,0 +1,119 @@
1/*
2 * Copyright (C) 2010 Linaro Limited
3 *
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/gpio.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/fsl_devices.h>
24
25#include <mach/common.h>
26#include <mach/hardware.h>
27#include <mach/iomux-mx51.h>
28#include <mach/i2c.h>
29#include <mach/mxc_ehci.h>
30
31#include <asm/irq.h>
32#include <asm/setup.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/time.h>
36
37#include "devices-imx51.h"
38#include "devices.h"
39
40#define MX51_USB_PLL_DIV_24_MHZ 0x01
41
42static struct pad_desc mx51efikamx_pads[] = {
43 /* UART1 */
44 MX51_PAD_UART1_RXD__UART1_RXD,
45 MX51_PAD_UART1_TXD__UART1_TXD,
46 MX51_PAD_UART1_RTS__UART1_RTS,
47 MX51_PAD_UART1_CTS__UART1_CTS,
48};
49
50/* Serial ports */
51#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
52static const struct imxuart_platform_data uart_pdata = {
53 .flags = IMXUART_HAVE_RTSCTS,
54};
55
56static inline void mxc_init_imx_uart(void)
57{
58 imx51_add_imx_uart(0, &uart_pdata);
59 imx51_add_imx_uart(1, &uart_pdata);
60 imx51_add_imx_uart(2, &uart_pdata);
61}
62#else /* !SERIAL_IMX */
63static inline void mxc_init_imx_uart(void)
64{
65}
66#endif /* SERIAL_IMX */
67
68/* This function is board specific as the bit mask for the plldiv will also
69 * be different for other Freescale SoCs, thus a common bitmask is not
70 * possible and cannot get place in /plat-mxc/ehci.c.
71 */
72static int initialize_otg_port(struct platform_device *pdev)
73{
74 u32 v;
75 void __iomem *usb_base;
76 void __iomem *usbother_base;
77 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
78 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
79
80 /* Set the PHY clock to 19.2MHz */
81 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
82 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
83 v |= MX51_USB_PLL_DIV_24_MHZ;
84 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
85 iounmap(usb_base);
86 return 0;
87}
88
89static struct mxc_usbh_platform_data dr_utmi_config = {
90 .init = initialize_otg_port,
91 .portsc = MXC_EHCI_UTMI_16BIT,
92 .flags = MXC_EHCI_INTERNAL_PHY,
93};
94
95static void __init mxc_board_init(void)
96{
97 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
98 ARRAY_SIZE(mx51efikamx_pads));
99 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
100 mxc_init_imx_uart();
101}
102
103static void __init mx51_efikamx_timer_init(void)
104{
105 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
106}
107
108static struct sys_timer mxc_timer = {
109 .init = mx51_efikamx_timer_init,
110};
111
112MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
113 /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
114 .boot_params = MX51_PHYS_OFFSET + 0x100,
115 .map_io = mx51_map_io,
116 .init_irq = mx51_init_irq,
117 .init_machine = mxc_board_init,
118 .timer = &mxc_timer,
119MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index 57c10a9926cc..f2aae92cf0e2 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -41,34 +41,66 @@ static struct clk usboh3_clk;
41 41
42#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ 42#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
43 43
44static int _clk_ccgr_enable(struct clk *clk) 44/* calculate best pre and post dividers to get the required divider */
45static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
46 u32 max_pre, u32 max_post)
45{ 47{
46 u32 reg; 48 if (div >= max_pre * max_post) {
49 *pre = max_pre;
50 *post = max_post;
51 } else if (div >= max_pre) {
52 u32 min_pre, temp_pre, old_err, err;
53 min_pre = DIV_ROUND_UP(div, max_post);
54 old_err = max_pre;
55 for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
56 err = div % temp_pre;
57 if (err == 0) {
58 *pre = temp_pre;
59 break;
60 }
61 err = temp_pre - err;
62 if (err < old_err) {
63 old_err = err;
64 *pre = temp_pre;
65 }
66 }
67 *post = DIV_ROUND_UP(div, *pre);
68 } else {
69 *pre = div;
70 *post = 1;
71 }
72}
73
74static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
75{
76 u32 reg = __raw_readl(clk->enable_reg);
77
78 reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
79 reg |= mode << clk->enable_shift;
47 80
48 reg = __raw_readl(clk->enable_reg);
49 reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift;
50 __raw_writel(reg, clk->enable_reg); 81 __raw_writel(reg, clk->enable_reg);
82}
51 83
84static int _clk_ccgr_enable(struct clk *clk)
85{
86 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
52 return 0; 87 return 0;
53} 88}
54 89
55static void _clk_ccgr_disable(struct clk *clk) 90static void _clk_ccgr_disable(struct clk *clk)
56{ 91{
57 u32 reg; 92 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
58 reg = __raw_readl(clk->enable_reg); 93}
59 reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
60 __raw_writel(reg, clk->enable_reg);
61 94
95static int _clk_ccgr_enable_inrun(struct clk *clk)
96{
97 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
98 return 0;
62} 99}
63 100
64static void _clk_ccgr_disable_inwait(struct clk *clk) 101static void _clk_ccgr_disable_inwait(struct clk *clk)
65{ 102{
66 u32 reg; 103 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
67
68 reg = __raw_readl(clk->enable_reg);
69 reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
70 reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
71 __raw_writel(reg, clk->enable_reg);
72} 104}
73 105
74/* 106/*
@@ -542,60 +574,60 @@ static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
542 return 0; 574 return 0;
543} 575}
544 576
545static unsigned long clk_uart_get_rate(struct clk *clk) 577#define clk_nfc_set_parent NULL
546{
547 u32 reg, prediv, podf;
548 unsigned long parent_rate;
549 578
550 parent_rate = clk_get_rate(clk->parent); 579static unsigned long clk_nfc_get_rate(struct clk *clk)
551 580{
552 reg = __raw_readl(MXC_CCM_CSCDR1); 581 unsigned long rate;
553 prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> 582 u32 reg, div;
554 MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
555 podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
556 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
557 583
558 return parent_rate / (prediv * podf); 584 reg = __raw_readl(MXC_CCM_CBCDR);
585 div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
586 MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
587 rate = clk_get_rate(clk->parent) / div;
588 WARN_ON(rate == 0);
589 return rate;
559} 590}
560 591
561static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) 592static unsigned long clk_nfc_round_rate(struct clk *clk,
593 unsigned long rate)
562{ 594{
563 u32 reg, mux; 595 u32 div;
596 unsigned long parent_rate = clk_get_rate(clk->parent);
564 597
565 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, 598 if (!rate)
566 &lp_apm_clk); 599 return -EINVAL;
567 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;
568 reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
569 __raw_writel(reg, MXC_CCM_CSCMR1);
570 600
571 return 0; 601 div = parent_rate / rate;
572}
573 602
574static unsigned long clk_usboh3_get_rate(struct clk *clk) 603 if (parent_rate % rate)
575{ 604 div++;
576 u32 reg, prediv, podf;
577 unsigned long parent_rate;
578 605
579 parent_rate = clk_get_rate(clk->parent); 606 if (div > 8)
607 return -EINVAL;
580 608
581 reg = __raw_readl(MXC_CCM_CSCDR1); 609 return parent_rate / div;
582 prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
583 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
584 podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
585 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
586 610
587 return parent_rate / (prediv * podf);
588} 611}
589 612
590static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent) 613static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
591{ 614{
592 u32 reg, mux; 615 u32 reg, div;
616
617 div = clk_get_rate(clk->parent) / rate;
618 if (div == 0)
619 div++;
620 if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
621 return -EINVAL;
622
623 reg = __raw_readl(MXC_CCM_CBCDR);
624 reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
625 reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
626 __raw_writel(reg, MXC_CCM_CBCDR);
593 627
594 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, 628 while (__raw_readl(MXC_CCM_CDHIPR) &
595 &lp_apm_clk); 629 MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
596 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; 630 }
597 reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
598 __raw_writel(reg, MXC_CCM_CSCMR1);
599 631
600 return 0; 632 return 0;
601} 633}
@@ -620,6 +652,17 @@ static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
620 return ckih2_reference; 652 return ckih2_reference;
621} 653}
622 654
655static unsigned long clk_emi_slow_get_rate(struct clk *clk)
656{
657 u32 reg, div;
658
659 reg = __raw_readl(MXC_CCM_CBCDR);
660 div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
661 MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
662
663 return clk_get_rate(clk->parent) / div;
664}
665
623/* External high frequency clock */ 666/* External high frequency clock */
624static struct clk ckih_clk = { 667static struct clk ckih_clk = {
625 .get_rate = get_high_reference_clock_rate, 668 .get_rate = get_high_reference_clock_rate,
@@ -715,18 +758,6 @@ static struct clk ipg_perclk = {
715 .set_parent = _clk_ipg_per_set_parent, 758 .set_parent = _clk_ipg_per_set_parent,
716}; 759};
717 760
718static struct clk uart_root_clk = {
719 .parent = &pll2_sw_clk,
720 .get_rate = clk_uart_get_rate,
721 .set_parent = _clk_uart_set_parent,
722};
723
724static struct clk usboh3_clk = {
725 .parent = &pll2_sw_clk,
726 .get_rate = clk_usboh3_get_rate,
727 .set_parent = _clk_usboh3_set_parent,
728};
729
730static struct clk ahb_max_clk = { 761static struct clk ahb_max_clk = {
731 .parent = &ahb_clk, 762 .parent = &ahb_clk,
732 .enable_reg = MXC_CCM_CCGR0, 763 .enable_reg = MXC_CCM_CCGR0,
@@ -762,45 +793,183 @@ static struct clk kpp_clk = {
762 .id = 0, 793 .id = 0,
763}; 794};
764 795
765#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ 796static struct clk emi_slow_clk = {
797 .parent = &pll2_sw_clk,
798 .enable_reg = MXC_CCM_CCGR5,
799 .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
800 .enable = _clk_ccgr_enable,
801 .disable = _clk_ccgr_disable_inwait,
802 .get_rate = clk_emi_slow_get_rate,
803};
804
805#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \
766 static struct clk name = { \ 806 static struct clk name = { \
767 .id = i, \ 807 .id = i, \
768 .enable_reg = er, \ 808 .enable_reg = er, \
769 .enable_shift = es, \ 809 .enable_shift = es, \
770 .get_rate = gr, \ 810 .get_rate = pfx##_get_rate, \
771 .set_rate = sr, \ 811 .set_rate = pfx##_set_rate, \
812 .round_rate = pfx##_round_rate, \
813 .set_parent = pfx##_set_parent, \
772 .enable = _clk_ccgr_enable, \ 814 .enable = _clk_ccgr_enable, \
773 .disable = _clk_ccgr_disable, \ 815 .disable = _clk_ccgr_disable, \
774 .parent = p, \ 816 .parent = p, \
775 .secondary = s, \ 817 .secondary = s, \
776 } 818 }
777 819
778/* DEFINE_CLOCK(name, id, enable_reg, enable_shift, 820#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s) \
779 get_rate, set_rate, parent, secondary); */ 821 static struct clk name = { \
822 .id = i, \
823 .enable_reg = er, \
824 .enable_shift = es, \
825 .get_rate = pfx##_get_rate, \
826 .set_rate = pfx##_set_rate, \
827 .set_parent = pfx##_set_parent, \
828 .enable = _clk_max_enable, \
829 .disable = _clk_max_disable, \
830 .parent = p, \
831 .secondary = s, \
832 }
833
834#define CLK_GET_RATE(name, nr, bitsname) \
835static unsigned long clk_##name##_get_rate(struct clk *clk) \
836{ \
837 u32 reg, pred, podf; \
838 \
839 reg = __raw_readl(MXC_CCM_CSCDR##nr); \
840 pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK) \
841 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
842 podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK) \
843 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
844 \
845 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), \
846 (pred + 1) * (podf + 1)); \
847}
848
849#define CLK_SET_PARENT(name, nr, bitsname) \
850static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
851{ \
852 u32 reg, mux; \
853 \
854 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, \
855 &pll3_sw_clk, &lp_apm_clk); \
856 reg = __raw_readl(MXC_CCM_CSCMR##nr) & \
857 ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK; \
858 reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET; \
859 __raw_writel(reg, MXC_CCM_CSCMR##nr); \
860 \
861 return 0; \
862}
863
864#define CLK_SET_RATE(name, nr, bitsname) \
865static int clk_##name##_set_rate(struct clk *clk, unsigned long rate) \
866{ \
867 u32 reg, div, parent_rate; \
868 u32 pre = 0, post = 0; \
869 \
870 parent_rate = clk_get_rate(clk->parent); \
871 div = parent_rate / rate; \
872 \
873 if ((parent_rate / div) != rate) \
874 return -EINVAL; \
875 \
876 __calc_pre_post_dividers(div, &pre, &post, \
877 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >> \
878 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1, \
879 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >> \
880 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
881 \
882 /* Set sdhc1 clock divider */ \
883 reg = __raw_readl(MXC_CCM_CSCDR##nr) & \
884 ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK \
885 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK); \
886 reg |= (post - 1) << \
887 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
888 reg |= (pre - 1) << \
889 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
890 __raw_writel(reg, MXC_CCM_CSCDR##nr); \
891 \
892 return 0; \
893}
894
895/* UART */
896CLK_GET_RATE(uart, 1, UART)
897CLK_SET_PARENT(uart, 1, UART)
898
899static struct clk uart_root_clk = {
900 .parent = &pll2_sw_clk,
901 .get_rate = clk_uart_get_rate,
902 .set_parent = clk_uart_set_parent,
903};
904
905/* USBOH3 */
906CLK_GET_RATE(usboh3, 1, USBOH3)
907CLK_SET_PARENT(usboh3, 1, USBOH3)
908
909static struct clk usboh3_clk = {
910 .parent = &pll2_sw_clk,
911 .get_rate = clk_usboh3_get_rate,
912 .set_parent = clk_usboh3_set_parent,
913};
914
915/* eCSPI */
916CLK_GET_RATE(ecspi, 2, CSPI)
917CLK_SET_PARENT(ecspi, 1, CSPI)
918
919static struct clk ecspi_main_clk = {
920 .parent = &pll3_sw_clk,
921 .get_rate = clk_ecspi_get_rate,
922 .set_parent = clk_ecspi_set_parent,
923};
924
925/* eSDHC */
926CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
927CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
928CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
929
930CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
931CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
932CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
933
934#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
935 static struct clk name = { \
936 .id = i, \
937 .enable_reg = er, \
938 .enable_shift = es, \
939 .get_rate = gr, \
940 .set_rate = sr, \
941 .enable = e, \
942 .disable = d, \
943 .parent = p, \
944 .secondary = s, \
945 }
946
947#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
948 DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
780 949
781/* Shared peripheral bus arbiter */ 950/* Shared peripheral bus arbiter */
782DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET, 951DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
783 NULL, NULL, &ipg_clk, NULL); 952 NULL, NULL, &ipg_clk, NULL);
784 953
785/* UART */ 954/* UART */
786DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
787 NULL, NULL, &uart_root_clk, NULL);
788DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
789 NULL, NULL, &uart_root_clk, NULL);
790DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
791 NULL, NULL, &uart_root_clk, NULL);
792DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET, 955DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
793 NULL, NULL, &ipg_clk, &aips_tz1_clk); 956 NULL, NULL, &ipg_clk, &aips_tz1_clk);
794DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET, 957DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
795 NULL, NULL, &ipg_clk, &aips_tz1_clk); 958 NULL, NULL, &ipg_clk, &aips_tz1_clk);
796DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, 959DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
797 NULL, NULL, &ipg_clk, &spba_clk); 960 NULL, NULL, &ipg_clk, &spba_clk);
961DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
962 NULL, NULL, &uart_root_clk, &uart1_ipg_clk);
963DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
964 NULL, NULL, &uart_root_clk, &uart2_ipg_clk);
965DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
966 NULL, NULL, &uart_root_clk, &uart3_ipg_clk);
798 967
799/* GPT */ 968/* GPT */
800DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
801 NULL, NULL, &ipg_clk, NULL);
802DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, 969DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
803 NULL, NULL, &ipg_clk, NULL); 970 NULL, NULL, &ipg_clk, NULL);
971DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
972 NULL, NULL, &ipg_clk, &gpt_ipg_clk);
804 973
805/* I2C */ 974/* I2C */
806DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET, 975DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
@@ -814,6 +983,52 @@ DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
814DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, 983DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
815 NULL, NULL, &ipg_clk, NULL); 984 NULL, NULL, &ipg_clk, NULL);
816 985
986/* NFC */
987DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
988 clk_nfc, &emi_slow_clk, NULL);
989
990/* SSI */
991DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
992 NULL, NULL, &ipg_clk, NULL);
993DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
994 NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
995DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
996 NULL, NULL, &ipg_clk, NULL);
997DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
998 NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
999
1000/* eCSPI */
1001DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1002 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1003 &ipg_clk, &spba_clk);
1004DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
1005 NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
1006DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
1007 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1008 &ipg_clk, &aips_tz2_clk);
1009DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
1010 NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
1011
1012/* CSPI */
1013DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1014 NULL, NULL, &ipg_clk, &aips_tz2_clk);
1015DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
1016 NULL, NULL, &ipg_clk, &cspi_ipg_clk);
1017
1018/* SDMA */
1019DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
1020 NULL, NULL, &ahb_clk, NULL);
1021
1022/* eSDHC */
1023DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
1024 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1025DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
1026 clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
1027DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
1028 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1029DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
1030 clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
1031
817#define _REGISTER_CLOCK(d, n, c) \ 1032#define _REGISTER_CLOCK(d, n, c) \
818 { \ 1033 { \
819 .dev_id = d, \ 1034 .dev_id = d, \
@@ -837,6 +1052,18 @@ static struct clk_lookup lookups[] = {
837 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) 1052 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
838 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) 1053 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
839 _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) 1054 _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
1055 _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
1056 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1057 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
1058 _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
1059 _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
1060 _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
1061 _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
1062 _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
1063 _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
1064 _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
1065 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
1066 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
840}; 1067};
841 1068
842static void clk_tree_init(void) 1069static void clk_tree_init(void)
@@ -880,6 +1107,14 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
880 /* set the usboh3_clk parent to pll2_sw_clk */ 1107 /* set the usboh3_clk parent to pll2_sw_clk */
881 clk_set_parent(&usboh3_clk, &pll2_sw_clk); 1108 clk_set_parent(&usboh3_clk, &pll2_sw_clk);
882 1109
1110 /* Set SDHC parents to be PLL2 */
1111 clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1112 clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
1113
1114 /* set SDHC root clock as 166.25MHZ*/
1115 clk_set_rate(&esdhc1_clk, 166250000);
1116 clk_set_rate(&esdhc2_clk, 166250000);
1117
883 /* System timer */ 1118 /* System timer */
884 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), 1119 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
885 MX51_MXC_INT_GPT); 1120 MX51_MXC_INT_GPT);
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 2d37785e3857..eaacb6e9b5d0 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -70,6 +70,25 @@ int mx51_revision(void)
70} 70}
71EXPORT_SYMBOL(mx51_revision); 71EXPORT_SYMBOL(mx51_revision);
72 72
73#ifdef CONFIG_NEON
74
75/*
76 * All versions of the silicon before Rev. 3 have broken NEON implementations.
77 * Dependent on link order - so the assumption is that vfp_init is called
78 * before us.
79 */
80static int __init mx51_neon_fixup(void)
81{
82 if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) {
83 elf_hwcap &= ~HWCAP_NEON;
84 pr_info("Turning off NEON support, detected broken NEON implementation\n");
85 }
86 return 0;
87}
88
89late_initcall(mx51_neon_fixup);
90#endif
91
73static int __init post_cpu_init(void) 92static int __init post_cpu_init(void)
74{ 93{
75 unsigned int reg; 94 unsigned int reg;
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
new file mode 100644
index 000000000000..5cc910e60538
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -0,0 +1,42 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/mx51.h>
10#include <mach/devices-common.h>
11
12extern const struct imx_fec_data imx51_fec_data __initconst;
13#define imx51_add_fec(pdata) \
14 imx_add_fec(&imx51_fec_data, pdata)
15
16extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
17#define imx51_add_imx_i2c(id, pdata) \
18 imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
19
20extern const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst;
21#define imx51_add_imx_ssi(id, pdata) \
22 imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
23
24extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst;
25#define imx51_add_imx_uart(id, pdata) \
26 imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
27
28extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst;
29#define imx51_add_mxc_nand(pdata) \
30 imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
31
32extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
33#define imx51_add_cspi(pdata) \
34 imx_add_spi_imx(&imx51_cspi_data, pdata)
35
36extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
37#define imx51_add_ecspi(id, pdata) \
38 imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
39
40extern const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst;
41#define imx51_add_esdhc(id, pdata) \
42 imx_add_esdhc(&imx51_esdhc_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 1920ff4963b2..4c7be87a7c9d 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -17,120 +17,6 @@
17#include <mach/imx-uart.h> 17#include <mach/imx-uart.h>
18#include <mach/irqs.h> 18#include <mach/irqs.h>
19 19
20static struct resource uart0[] = {
21 {
22 .start = MX51_UART1_BASE_ADDR,
23 .end = MX51_UART1_BASE_ADDR + 0xfff,
24 .flags = IORESOURCE_MEM,
25 }, {
26 .start = MX51_MXC_INT_UART1,
27 .end = MX51_MXC_INT_UART1,
28 .flags = IORESOURCE_IRQ,
29 },
30};
31
32struct platform_device mxc_uart_device0 = {
33 .name = "imx-uart",
34 .id = 0,
35 .resource = uart0,
36 .num_resources = ARRAY_SIZE(uart0),
37};
38
39static struct resource uart1[] = {
40 {
41 .start = MX51_UART2_BASE_ADDR,
42 .end = MX51_UART2_BASE_ADDR + 0xfff,
43 .flags = IORESOURCE_MEM,
44 }, {
45 .start = MX51_MXC_INT_UART2,
46 .end = MX51_MXC_INT_UART2,
47 .flags = IORESOURCE_IRQ,
48 },
49};
50
51struct platform_device mxc_uart_device1 = {
52 .name = "imx-uart",
53 .id = 1,
54 .resource = uart1,
55 .num_resources = ARRAY_SIZE(uart1),
56};
57
58static struct resource uart2[] = {
59 {
60 .start = MX51_UART3_BASE_ADDR,
61 .end = MX51_UART3_BASE_ADDR + 0xfff,
62 .flags = IORESOURCE_MEM,
63 }, {
64 .start = MX51_MXC_INT_UART3,
65 .end = MX51_MXC_INT_UART3,
66 .flags = IORESOURCE_IRQ,
67 },
68};
69
70struct platform_device mxc_uart_device2 = {
71 .name = "imx-uart",
72 .id = 2,
73 .resource = uart2,
74 .num_resources = ARRAY_SIZE(uart2),
75};
76
77static struct resource mxc_fec_resources[] = {
78 {
79 .start = MX51_MXC_FEC_BASE_ADDR,
80 .end = MX51_MXC_FEC_BASE_ADDR + 0xfff,
81 .flags = IORESOURCE_MEM,
82 }, {
83 .start = MX51_MXC_INT_FEC,
84 .end = MX51_MXC_INT_FEC,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89struct platform_device mxc_fec_device = {
90 .name = "fec",
91 .id = 0,
92 .num_resources = ARRAY_SIZE(mxc_fec_resources),
93 .resource = mxc_fec_resources,
94};
95
96static struct resource mxc_i2c0_resources[] = {
97 {
98 .start = MX51_I2C1_BASE_ADDR,
99 .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1,
100 .flags = IORESOURCE_MEM,
101 }, {
102 .start = MX51_MXC_INT_I2C1,
103 .end = MX51_MXC_INT_I2C1,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108struct platform_device mxc_i2c_device0 = {
109 .name = "imx-i2c",
110 .id = 0,
111 .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
112 .resource = mxc_i2c0_resources,
113};
114
115static struct resource mxc_i2c1_resources[] = {
116 {
117 .start = MX51_I2C2_BASE_ADDR,
118 .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1,
119 .flags = IORESOURCE_MEM,
120 }, {
121 .start = MX51_MXC_INT_I2C2,
122 .end = MX51_MXC_INT_I2C2,
123 .flags = IORESOURCE_IRQ,
124 },
125};
126
127struct platform_device mxc_i2c_device1 = {
128 .name = "imx-i2c",
129 .id = 1,
130 .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
131 .resource = mxc_i2c1_resources,
132};
133
134static struct resource mxc_hsi2c_resources[] = { 20static struct resource mxc_hsi2c_resources[] = {
135 { 21 {
136 .start = MX51_HSI2C_DMA_BASE_ADDR, 22 .start = MX51_HSI2C_DMA_BASE_ADDR,
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index e509cfaad1d4..af1d07c0bbc1 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -1,12 +1,6 @@
1extern struct platform_device mxc_uart_device0;
2extern struct platform_device mxc_uart_device1;
3extern struct platform_device mxc_uart_device2;
4extern struct platform_device mxc_fec_device;
5extern struct platform_device mxc_usbdr_host_device; 1extern struct platform_device mxc_usbdr_host_device;
6extern struct platform_device mxc_usbh1_device; 2extern struct platform_device mxc_usbh1_device;
7extern struct platform_device mxc_usbdr_udc_device; 3extern struct platform_device mxc_usbdr_udc_device;
8extern struct platform_device mxc_wdt; 4extern struct platform_device mxc_wdt;
9extern struct platform_device mxc_i2c_device0;
10extern struct platform_device mxc_i2c_device1;
11extern struct platform_device mxc_hsi2c_device; 5extern struct platform_device mxc_hsi2c_device;
12extern struct platform_device mxc_keypad_device; 6extern struct platform_device mxc_keypad_device;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index ffa93d1d6ef8..a2e6e8c39d25 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -30,6 +30,7 @@
30 30
31#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
32 32
33#include "devices-imx51.h"
33#include "devices.h" 34#include "devices.h"
34 35
35#define MBIMX51_TSC2007_GPIO (2*32 + 30) 36#define MBIMX51_TSC2007_GPIO (2*32 + 30)
@@ -112,9 +113,25 @@ static struct pad_desc mbimx51_pads[] = {
112 MX51_PAD_KEY_COL1__KEY_COL1, 113 MX51_PAD_KEY_COL1__KEY_COL1,
113 MX51_PAD_KEY_COL2__KEY_COL2, 114 MX51_PAD_KEY_COL2__KEY_COL2,
114 MX51_PAD_KEY_COL3__KEY_COL3, 115 MX51_PAD_KEY_COL3__KEY_COL3,
116
117 /* SD 1 */
118 MX51_PAD_SD1_CMD__SD1_CMD,
119 MX51_PAD_SD1_CLK__SD1_CLK,
120 MX51_PAD_SD1_DATA0__SD1_DATA0,
121 MX51_PAD_SD1_DATA1__SD1_DATA1,
122 MX51_PAD_SD1_DATA2__SD1_DATA2,
123 MX51_PAD_SD1_DATA3__SD1_DATA3,
124
125 /* SD 2 */
126 MX51_PAD_SD2_CMD__SD2_CMD,
127 MX51_PAD_SD2_CLK__SD2_CLK,
128 MX51_PAD_SD2_DATA0__SD2_DATA0,
129 MX51_PAD_SD2_DATA1__SD2_DATA1,
130 MX51_PAD_SD2_DATA2__SD2_DATA2,
131 MX51_PAD_SD2_DATA3__SD2_DATA3,
115}; 132};
116 133
117static struct imxuart_platform_data uart_pdata = { 134static const struct imxuart_platform_data uart_pdata __initconst = {
118 .flags = IMXUART_HAVE_RTSCTS, 135 .flags = IMXUART_HAVE_RTSCTS,
119}; 136};
120 137
@@ -158,9 +175,11 @@ struct tsc2007_platform_data tsc2007_data = {
158 175
159static struct i2c_board_info mbimx51_i2c_devices[] = { 176static struct i2c_board_info mbimx51_i2c_devices[] = {
160 { 177 {
161 I2C_BOARD_INFO("tsc2007", 0x48), 178 I2C_BOARD_INFO("tsc2007", 0x49),
162 .irq = MBIMX51_TSC2007_IRQ, 179 .irq = MBIMX51_TSC2007_IRQ,
163 .platform_data = &tsc2007_data, 180 .platform_data = &tsc2007_data,
181 }, {
182 I2C_BOARD_INFO("tlv320aic23", 0x1a),
164 }, 183 },
165}; 184};
166 185
@@ -172,8 +191,8 @@ void __init eukrea_mbimx51_baseboard_init(void)
172 mxc_iomux_v3_setup_multiple_pads(mbimx51_pads, 191 mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
173 ARRAY_SIZE(mbimx51_pads)); 192 ARRAY_SIZE(mbimx51_pads));
174 193
175 mxc_register_device(&mxc_uart_device1, NULL); 194 imx51_add_imx_uart(1, NULL);
176 mxc_register_device(&mxc_uart_device2, &uart_pdata); 195 imx51_add_imx_uart(2, &uart_pdata);
177 196
178 gpio_request(MBIMX51_LED0, "LED0"); 197 gpio_request(MBIMX51_LED0, "LED0");
179 gpio_direction_output(MBIMX51_LED0, 1); 198 gpio_direction_output(MBIMX51_LED0, 1);
@@ -197,4 +216,7 @@ void __init eukrea_mbimx51_baseboard_init(void)
197 set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); 216 set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
198 i2c_register_board_info(1, mbimx51_i2c_devices, 217 i2c_register_board_info(1, mbimx51_i2c_devices,
199 ARRAY_SIZE(mbimx51_i2c_devices)); 218 ARRAY_SIZE(mbimx51_i2c_devices));
219
220 imx51_add_esdhc(0, NULL);
221 imx51_add_esdhc(1, NULL);
200} 222}
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 000000000000..2b48f5190830
--- /dev/null
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,166 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24
25#include <linux/gpio.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <linux/leds.h>
29#include <linux/platform_device.h>
30#include <linux/gpio_keys.h>
31#include <linux/input.h>
32#include <linux/i2c.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/mach/map.h>
38
39#include <mach/hardware.h>
40#include <mach/common.h>
41#include <mach/imx-uart.h>
42#include <mach/iomux-mx51.h>
43#include <mach/audmux.h>
44
45#include "devices-imx51.h"
46#include "devices.h"
47
48#define MBIMXSD_GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, \
49 MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
50
51static struct pad_desc eukrea_mbimxsd_pads[] = {
52 /* LED */
53 MX51_PAD_NANDF_D10__GPIO_3_30,
54 /* SWITCH */
55 MBIMXSD_GPIO_3_31,
56 /* UART2 */
57 MX51_PAD_UART2_RXD__UART2_RXD,
58 MX51_PAD_UART2_TXD__UART2_TXD,
59 /* UART 3 */
60 MX51_PAD_UART3_RXD__UART3_RXD,
61 MX51_PAD_UART3_TXD__UART3_TXD,
62 MX51_PAD_KEY_COL4__UART3_RTS,
63 MX51_PAD_KEY_COL5__UART3_CTS,
64 /* SD */
65 MX51_PAD_SD1_CMD__SD1_CMD,
66 MX51_PAD_SD1_CLK__SD1_CLK,
67 MX51_PAD_SD1_DATA0__SD1_DATA0,
68 MX51_PAD_SD1_DATA1__SD1_DATA1,
69 MX51_PAD_SD1_DATA2__SD1_DATA2,
70 MX51_PAD_SD1_DATA3__SD1_DATA3,
71};
72
73#define GPIO_LED1 (2 * 32 + 30)
74#define GPIO_SWITCH1 (2 * 32 + 31)
75
76static struct gpio_led eukrea_mbimxsd_leds[] = {
77 {
78 .name = "led1",
79 .default_trigger = "heartbeat",
80 .active_low = 1,
81 .gpio = GPIO_LED1,
82 },
83};
84
85static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
86 .leds = eukrea_mbimxsd_leds,
87 .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
88};
89
90static struct platform_device eukrea_mbimxsd_leds_gpio = {
91 .name = "leds-gpio",
92 .id = -1,
93 .dev = {
94 .platform_data = &eukrea_mbimxsd_led_info,
95 },
96};
97
98static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
99 {
100 .gpio = GPIO_SWITCH1,
101 .code = BTN_0,
102 .desc = "BP1",
103 .active_low = 1,
104 .wakeup = 1,
105 },
106};
107
108static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
109 .buttons = eukrea_mbimxsd_gpio_buttons,
110 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
111};
112
113static struct platform_device eukrea_mbimxsd_button_device = {
114 .name = "gpio-keys",
115 .id = -1,
116 .num_resources = 0,
117 .dev = {
118 .platform_data = &eukrea_mbimxsd_button_data,
119 }
120};
121
122static struct platform_device *platform_devices[] __initdata = {
123 &eukrea_mbimxsd_leds_gpio,
124 &eukrea_mbimxsd_button_device,
125};
126
127static const struct imxuart_platform_data uart_pdata __initconst = {
128 .flags = IMXUART_HAVE_RTSCTS,
129};
130
131static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
132 {
133 I2C_BOARD_INFO("tlv320aic23", 0x1a),
134 },
135};
136
137/*
138 * system init for baseboard usage. Will be called by cpuimx51sd init.
139 *
140 * Add platform devices present on this baseboard and init
141 * them from CPU side as far as required to use them later on
142 */
143void __init eukrea_mbimxsd51_baseboard_init(void)
144{
145 if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
146 ARRAY_SIZE(eukrea_mbimxsd_pads)))
147 printk(KERN_ERR "error setting mbimxsd pads !\n");
148
149 imx51_add_imx_uart(1, NULL);
150 imx51_add_imx_uart(2, &uart_pdata);
151
152 imx51_add_esdhc(0, NULL);
153
154 gpio_request(GPIO_LED1, "LED1");
155 gpio_direction_output(GPIO_LED1, 1);
156 gpio_free(GPIO_LED1);
157
158 gpio_request(GPIO_SWITCH1, "SWITCH1");
159 gpio_direction_input(GPIO_SWITCH1);
160 gpio_free(GPIO_SWITCH1);
161
162 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
163 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
164
165 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
166}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 18:10:11 -0500